CN1384546B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN1384546B
CN1384546B CN021185042A CN02118504A CN1384546B CN 1384546 B CN1384546 B CN 1384546B CN 021185042 A CN021185042 A CN 021185042A CN 02118504 A CN02118504 A CN 02118504A CN 1384546 B CN1384546 B CN 1384546B
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China
Prior art keywords
film transistor
thin
electrically
gate electrode
impurity range
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CN021185042A
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Chinese (zh)
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CN1384546A (en
Inventor
浅见宗广
长尾祥
棚田好文
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株式会社半导体能源研究所
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Priority to JP2001133431A priority Critical patent/JP4785271B2/en
Priority to JP133431/01 priority
Application filed by 株式会社半导体能源研究所 filed Critical 株式会社半导体能源研究所
Publication of CN1384546A publication Critical patent/CN1384546A/en
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Publication of CN1384546B publication Critical patent/CN1384546B/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

Abstract

There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance ( 205 ) is provided between a gate and a source of a TFT ( 203 ) connected to an output node, and a circuit formed of TFTs ( 201 ) and ( 202 ) has a function to bring a node alpha into a floating state. When the node alpha is in the floating state, a potential of the node alpha is caused higher than VDD by using gate-source capacitance coupling of the TFT ( 203 ) through the capacitance ( 205 ), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Description

Semiconductor device

Invention field

The present invention relates to semiconductor device.This semiconductor device is meant any device that can utilize characteristic of semiconductor work.The present invention is specifically related to the drive circuit of display device.The present invention also comprises the electronic equipment that the drive circuit with this display device is assembled into.Display device described in this paper specification comprises the liquid crystal display device that obtains as pixel with liquid crystal cell, and uses the light-emitting display device that obtains such as organic electroluminescent (EL) element etc. self light-emitting component.Drive circuit is meant for demonstration carries out a kind of circuit of handling to received image signal to the pixel that is arranged in the display device, and comprises such as shift register isopulse circuit with such as amplifier or the like amplifying circuit.

Background technology

In recent years, particularly form the semiconductor device (display device) of a semiconductive thin film at an insulator on a glass substrate, the active matrix type display spare of particularly a kind of employing thin-film transistor (below be called TFT) is widely used.Adopt the active matrix type display spare of TFT to comprise hundreds thousand of and even millions of pixels, pixel is arranged to matrix shape, controls the electric charge of each pixel by the TFT that is arranged in each pixel, thereby demonstrates an image.

And then, as technology recently, the technology of relevant a kind of multi-crystal TFT is development to some extent, except the pixel TFT that constitutes pixel, also form a drive circuit simultaneously with TFT therein in pixel parts zone on every side, its miniaturization of devices of going a long way greatly, and can reduce the electrical power that consumes, its result makes this display device become a kind of indispensable device in the display part of personal digital assistant device, and its application has had significant expansion in recent years.

As semiconductor device (drive circuit of display device), normally adopt the cmos circuit that has made up N-type TFT and P-type TFT therein.This cmos circuit is characterised in that following 2 points: only have electric current to flow in the moment that changes logic, and do not have electric current to flow in the time period that keeps certain logic; And only there is electric current to flow, and very little leakage current (although desirable leakage current is zero) only arranged in the time period that keeps certain logic in the moment that changes logic.This cmos circuit has above-mentioned two kinds of features, and the advantage of bringing for this cmos circuit is to reduce the entire circuit consumed current thus, and can carry out high-speed driving satisfactorily.

Described term " logic " is meant H (height) level and L (low) level.And term " logic variation " is meant that the H level becomes the L level or the L level becomes the H level.

It is littler lighter that mobile electronic device is becoming, the demand of the display device that adopts liquid crystal or self light-emitting component is being increased rapidly, yet, but be difficult to manufacturing cost is reduced to enough low level from aspects such as output.Following demand obviously also can further increase rapidly, therefore just needs the display device that can provide cheap more.

As the method for making drive circuit on insulator, it is to the active layer composition that a kind of universal method is arranged, and forms lead or the like by carry out exposure-processed and etching with a plurality of photomasks.Yet the quantity of performed step can directly have influence on manufacturing cost in this course, and therefore, the desirable technology of making this device is that step number is few more good more.Normally the drive circuit that is made of cmos circuit constitutes with TFT, and its conductivity belongs to N type or P type.Adopt this method just can omit a part of ion doping step, and the quantity of photomask also can reduce.

Yet, if the TFT that belongs to N type or P type with conductivity constitutes drive circuit, problem hereinafter described will appear.

Fig. 9 A represents a kind of CMOS inverter (I) of being commonly used and adopts polarity is the inverter (II) that constitutes of the TFT of one of N type or P type and some examples (III).Inverter (II) is a kind of TFT support type inverter, and inverter (III) is a kind of ohmic load type inverter.Below to introduce operation separately.

Fig. 9 B represents to import the signal waveform of this inverter.Suppose that input signal amplitude is VDD-GND (GND<VDD).Just suppose GND=0[V specifically].

This scope of current potential that described term " VDD-GND " expression is represented to GND from the current potential of VDD representative.In this article, the scope of this current potential is to be used in GND, and on behalf of the given symbol "-" in the centre of each current potential, VDD or the like represent.For example, GND-VDD1 representative that scope from the current potential of GND indication to the current potential of VDD1 indication.In addition, in this article, as an exception of grid-source voltage, having symbol in the middle of grid and source electrode is the situation of "-".Grid-source voltage in this case represent the voltage that produces between a transistorized gate electrode and the source electrode rather than represent grid and source electrode between scope.

Below want the working method of rendering circuit.For explain clear and simple and direct and hypothesis to constitute the threshold voltage of the N-type TFT of a circuit be irregular, and on average be defined as VthN.Equally, the threshold voltage of P-type TFT on average is defined as VthP.

If be at the current potential of input signal under the state of H level (VDD) signal shown in Fig. 9 B is input to the CMOS inverter, P-type TFT901 just is turned off, and N-type TFT902 then is switched on, and the current potential on the output node has L level (GND).Otherwise if input signal is in the L level, P-type TFT901 just is switched on, and N-type TFT902 then is turned off, and the current potential on the output node just becomes H level (Fig. 9 C).

Below to explain the working method of TFT support type inverter (II).Situation shown in the input signal of being considered and Fig. 9 B is similar.At first, when input signal was in the L level, N-type TFT904 was turned off.On the other hand, a load TFT works under saturation condition all the time, makes the output node current potential rise towards H level direction.On the other hand, when input signal was in the H level, N-type TFT904 was switched on.The current capacity of N-type TFT904 is arranged on enough highlyer than load TFT903 herein, the current potential of output node then descends to L level direction.

Similarly situation is fit to ohmic load type inverter (III) equally, if be arranged on the conduction resistance value of a N-type TFT906 enough lower than load resistance 905, when input signal was in the H level, N-type TFT906 was switched on, and the current potential of output node then descends to L level direction.When input signal was in the L level, N-type TFT906 was turned off, and the current potential of output node then rises to H level direction.

Yet, following problem can appear when adopting TFT support type inverter or ohmic load type inverter.Fig. 9 D represents the output waveform of TFT support type inverter.When output was in the H level, its current potential can be than the amount shown in the low numeral 907 of VDD.In load TFT903, if the terminal of output node one side is a source electrode, and the terminal of power vd D one side is drain electrode, and gate electrode and drain region just are joined together.Therefore, gate electrode current potential at this moment is VDD.Also have, allowing load TFT to be under the condition of conducting state, the grid-source voltage of TFT903 can be greater than VthN, causes the current potential of output node almost to rise to and deduct the value (VDD-VthN) that VthN obtains from VDD.That is to say that the value of being represented by numeral 907 equals VthN.And then according to the current capacity ratio of load TFT903 and N-type TFT904, when output potential was in the L level, this current potential became than GND and exceeds an amount shown in the numeral 908.In order to make it enough near GND, the current capacity of N-type TFT904 must be arranged on enough higher than load TFT903.Equally, Fig. 9 E represents the output waveform of ohmic load type inverter.According to the ratio of the conducting resistance of the resistance value of load resistance 905 and N-type TFT906, this current potential can exceed the amount shown in the numeral 909.That is to say that if the inverter that only is made of a kind of TFT of polarity shown in the employing figure, output signal will amplitude fading occur with respect to the amplitude of input signal.In order to constitute drive circuit, must obtain not have the output of amplitude fading.

Summary of the invention

The present invention proposes at the problems referred to above, the purpose of this invention is to provide a kind of semiconductor device (drive circuit of display device), it can by low cost with one of N-type or P-type only a kind of TFT of polarity make, thereby the minimizing manufacturing step, and can obtain not have the output of amplitude fading.

In the above-mentioned TFT support type inverter (II) shown in Fig. 9 A, be generally in output amplitude under the condition of VDD-GND and take in.At first press the circuit shown in Figure 1A, when the current potential of output signal became the H level, it only was enough low that the resistance value between power supply GND and the output node is compared with the resistance value between power vd D and the output node, therefore made this current potential enough near GND.That is to say that N-type TFT101 only just is in the OFF state in N-type TFT102 is in time period of ON state.Secondly, when the current potential of output signal becomes the H level, equal VDD in order to make this current potential, the absolute value of the grid-source voltage of N-type TFT101 only requires to surpass all the time VthN.That is to say that for the H level that satisfies output node becomes the state of VDD, the current potential of the gate electrode of N-type TFT101 must be set at and be higher than the value that current potential obtained (VDD+VthN) that threshold value VthN adds power vd D.The power supply that offers circuit only comprises two kinds of VDD and GND.Therefore, if there is not current potential to be higher than the 3rd power supply of VDD, just can't satisfy this condition.

For this reason, the present invention has imagined following way.Shown in Figure 1B, between the grid of N-type TFT101 and source electrode, an electric capacity 103 is set.The gate electrode of N-type TFT101 is in a certain current potential and enters quick condition, and the current potential of output node is raised, and causes the current potential of output node to raise, and the current potential of the gate electrode of N-type TFT101 also can raise because of the capacitive coupling of electric capacity 103.Utilize this effect just can make the current potential of the gate electrode of N-type TFT101 be higher than VDD, the current potential that just is higher than threshold value VthN more precisely adds the value that current potential obtained (VDD+VthN) of power vd D.So just can make the current potential of output node be enough to rise to VDD.

For the electric capacity shown in Figure 1B 103, can adopt the capacitive part of actual fabrication, or the grid of TFT101 and the parasitic capacitance between the source electrode.

Below to explain structure of the present invention.

Be characterised in that according to semiconductor device of the present invention it comprises: the first transistor with first impurity range that is connected to first power supply; Transistor seconds with first impurity range that is connected to second source; The 3rd transistor with first impurity range that is connected to first power supply; And the 4th transistor with first impurity range that is connected to second source, this wherein: first to the 4th transistor has identical conduction type; Second impurity range of the first transistor and second impurity range of transistor seconds are connected to a terminal of an electric capacity; The 3rd transistorized second impurity range, the gate electrode of the 4th transistorized second impurity range and the first transistor is connected to another terminal of this electric capacity; The gate electrode of transistor seconds and the 4th transistorized gate electrode are connected to an input signal cable; And the 3rd transistorized gate electrode is connected to first power supply.

Be characterised in that according to semiconductor device of the present invention it comprises: the first transistor with first impurity range that is connected to first power supply; Transistor seconds with first impurity range that is connected to second source; The 3rd transistor with first impurity range that is connected to first power supply; The 4th transistor with first impurity range that is connected to second source; And an electric capacity, this wherein: first to the 4th transistor has identical conduction type; Second impurity range of the first transistor and second impurity range of transistor seconds are connected to a terminal of electric capacity; The 3rd transistorized second impurity range, the gate electrode of the 4th transistorized second impurity range and the first transistor is connected to another terminal of this electric capacity; The gate electrode of transistor seconds and the 4th transistorized gate electrode are connected to first input signal cable; And the 3rd transistorized gate electrode is connected to second input signal cable.

According to an aspect of the present invention, provide a kind of semiconductor device to comprise: to comprise the pixel portion of the pixel of pixel thin film transistor comprising on the substrate; Drive circuit on the substrate, and be electrically connected to pixel, this drive circuit comprises: the first film transistor with first impurity range that is electrically connected to first power supply; Second thin-film transistor with first impurity range that is electrically connected to second source; The 3rd thin-film transistor with first impurity range that is electrically connected to first power supply; The 4th thin-film transistor with first impurity range that is electrically connected to second source, this wherein: first to the 4th thin-film transistor has identical conduction type with pixel thin film transistor; Second impurity range of transistorized second impurity range of the first film and second thin-film transistor is electrically connected to a terminal of an electric capacity; Second impurity range of the 3rd thin-film transistor, second impurity range of the 4th thin-film transistor and the transistorized gate electrode of the first film are electrically connected to another terminal of this electric capacity; The gate electrode of the gate electrode of second thin-film transistor and the 4th thin-film transistor is electrically connected to first input signal cable; And the gate electrode of the 3rd thin-film transistor is electrically connected to second input signal cable; And first input signal cable be electrically connected to the imported circuit of list that comprises thin-film transistor with identical conduction type.

According to a further aspect in the invention, provide a kind of display device, having comprised: comprised the pixel portion of the pixel of pixel thin film transistor comprising on the substrate; Drive circuit on the substrate, and be electrically connected to pixel, this drive circuit comprises: the first film transistor with first impurity range that is electrically connected to first power supply; Second thin-film transistor with first impurity range that is electrically connected to second source; The 3rd thin-film transistor with first impurity range that is electrically connected to first power supply; The 4th thin-film transistor with first impurity range that is electrically connected to second source, this wherein: first to the 4th thin-film transistor has identical conduction type with pixel thin film transistor; Second impurity range of transistorized second impurity range of the first film and second thin-film transistor is electrically connected to a terminal of an electric capacity; Second impurity range of the 3rd thin-film transistor, second impurity range of the 4th thin-film transistor and the gate electrode of the first transistor are electrically connected to another terminal of this electric capacity; The gate electrode of the gate electrode of second thin-film transistor and the 4th thin-film transistor is electrically connected to first input signal cable; And the gate electrode of the 3rd thin-film transistor is electrically connected to second input signal cable; And first input signal cable be electrically connected to the imported circuit of list that comprises thin-film transistor with identical conduction type.

According to a further aspect in the invention, provide a kind of semiconductor device, having comprised: comprised the pixel portion of the pixel of pixel thin film transistor comprising on the substrate; Drive circuit on the substrate, and be electrically connected to pixel, this drive circuit comprises: the first film transistor with first impurity range that is electrically connected to first power supply; Second thin-film transistor with first impurity range that is electrically connected to second source; Output amplitude compensating circuit with input terminal and lead-out terminal, wherein lead-out terminal is electrically connected to the transistorized gate electrode of the first film, and wherein: the channel formation region of first and second thin-film transistors and pixel thin film transistor has identical conduction type; Second impurity range of transistorized second impurity range of the first film and second thin-film transistor is electrically connected to output signal line; The input terminal of the gate electrode of second thin-film transistor and output amplitude compensating circuit is electrically connected to input signal cable; And input signal cable is electrically connected to the imported circuit of list that comprises the thin-film transistor with identical conduction type.

According to a further aspect in the invention, provide a kind of display device, having comprised: comprised the pixel portion of the pixel of pixel thin film transistor comprising on the substrate; Drive circuit on the substrate, and be electrically connected to pixel, this drive circuit comprises: the first film transistor with first impurity range that is electrically connected to first power supply; Second thin-film transistor with first impurity range that is electrically connected to second source; Output amplitude compensating circuit with input terminal and lead-out terminal, wherein lead-out terminal is electrically connected to the transistorized gate electrode of the first film, and wherein: the channel formation region of first and second thin-film transistors and pixel thin film transistor has identical conduction type; Second impurity range of transistorized second impurity range of the first film and second thin-film transistor is electrically connected to output signal line; The input terminal of the gate electrode of second thin-film transistor and output amplitude compensating circuit is electrically connected to input signal cable; And input signal cable is electrically connected to the imported circuit of list that comprises the thin-film transistor with identical conduction type.

Description of drawings

Figure 1A and 1B are the schematic diagrames that is used for explaining semiconductor device of the present invention (drive circuit of display device) operation principle.

Fig. 2 A represents a kind of inverter of fundamental mode of semiconductor device of the present invention (drive circuit of display device) and the waveform of input/output signal thereof to the schematic diagram of 2D.

Fig. 3 A represents that to the schematic diagram of 3C a kind of inverter of the fundamental mode of semiconductor device of the present invention (drive circuit of display device) is connected to the connected mode when multistage.

The schematic diagram of Fig. 4 A and 4D is represented as the level shifter of an example of the semiconductor device (drive circuit of display device) of invention and the waveform of input/output signal thereof.

The schematic diagram of Fig. 5 A and 5B is used to explain the operation principle of level shifter and the topology example of level shifter respectively.

The schematic diagram of Fig. 6 is represented the topology example of a two point form level shifter under the situation that comprises an inversion signal.

The schematic diagram of Fig. 7 is represented a kind of display device made from the present invention.

Fig. 8 A has represented to adopt the example of the electronic equipment of semiconductor device of the present invention (drive circuit of display device) to the schematic diagram of 8G.

Fig. 9 A represents the structure of a kind of common CMOS inverter and support type inverter and the waveform of input/output signal separately to the schematic diagram of 9E.

The schematic diagram of Figure 10 A and 10B is used to explain the input signal and the circuit theory of four-TFT type inverter and three-TFT type inverter.

Embodiment

Fig. 2 A represents a kind of semiconductor device of the present invention (drive circuit of display device), and its circuit function is an inverter.This circuit is made up of N-type TFT201 to 204 and an electric capacity 205, and that part of being surrounded by frame of broken lines 206 is equivalent to the circuit shown in Figure 1A.That part of being surrounded by frame of broken lines 210 constitutes an output amplitude compensating circuit.The effect of output amplitude compensating circuit 210 is to make the gate electrode of N-type TFT203 enter quick condition, so long as can obtain same function, its circuit is not limited only to the structure of Fig. 2 A.

In the circuit of Fig. 2 A, input signal is imported into the gate electrode of N-type TFT202 and N-type TFT204.TFT201 is as load for the N-type, and the output that provides of N-type TFT201 and 202 circuit of forming is imported into the gate electrode of N-type TFT203.Output with N-type TFT201 and 202 circuit of forming in Fig. 2 A is called α.

Below to explain the operation of this circuit successively.Represent power supply potential with VDD and GND, and represent the amplitude of input signal with VDD (H level)-GND (L level).At first, when the current potential of input signal was the H level, N-type TFT202 and 204 was switched on.At this moment, because gate electrode and drain region are joined together, N-type TFT201 is operated in saturation condition, yet the current capacity of N-type TFT202 is set at the current capacity that is higher than N-type TFT201, causes the current potential of node alpha to drop to GND.Therefore, N-type TFT203 is turned off, and the output of L level appears on the output node.

Then, when the current potential of input signal was the L level, N-type TFT202 and 204 was turned off.Therefore, the current potential on the node alpha will rise to VDD one side, and becomes when power vd D deducts the value (VDD-VthN) that threshold value VthN obtained when this potential value, just forms quick condition once more.On the other hand, when the current potential of node a began to rise, N-type TFT203 was by conducting in advance, and the current potential of output node rises to VDD one side.When node alpha entered quick condition, the current potential of output node continued to rise.Therefore, along with the rising of output node current potential, the current potential that is in the node alpha of quick condition also can rise because of there is gate-to-source electric capacity 205 in N-type TFT203.So just can make the current potential of node alpha be higher than power vd D and add the value (VDD+VthN) that upper threshold VthN is obtained.Will on output node, occur the output of H level like this, and the current potential of this moment equals VDD.

Just can obtain not have the output amplitude of decay with respect to input signal amplitude by aforesaid operations.The method that the capacitive coupling that above-mentioned utilization formed between 2 o'clock promotes current potential is called as the bootstrapping method.The waveform of the input signal of circuit shown in Fig. 2 B presentation graphs 2A, Fig. 2 C represents the waveform of current potential on the node alpha, and Fig. 2 D represents the waveform of output signal.In Fig. 2 C, are current potentials (VDD-VthN) with the current potentials of numeral 208 representatives, and make amount that the current potential of node alpha promotes shown in numeral 207 by bootstrapping than the low VthN of VDD.Therefore, shown in Fig. 2 D, when output node was in the H level, current potential rose to VDD, just can obtain the output signal that amplitude is VDD-GND thus.

In semiconductor device of the present invention (drive circuit of display device), although be amplitude compensation with the output signal carried out with the bootstrapping method as basic operation, simultaneously also hypothesis to adopt the gate electrode of capacity coupled TFT be to be in quick condition.Figure 10 A and 10B represent the basic structure of semiconductor device of the present invention (drive circuit of display device), and its node alpha is in quick condition, thereby promote the current potential of node a with the gate-to-source electric capacity of TFT1003, compensate the amplitude of output signal then with it.Figure 10 B represents the circuit formed with three TFT, and its node alpha is in quick condition equally, thereby with the current potential of the gate-to-source electric capacity 1009 lifting node β of TFT1007, compensates the amplitude of output signal then with it.

The amplitude and the power supply potential of input signal below will be discussed.The power supply potential that will be in high level one side herein is called VDD; The power supply potential that is in low level one side is called GND; And inb represents the inversion signal of input signal.It is the state of under the amplitude of input signal and inb is respectively done for oneself the situation of VDD3-GND, considering node alpha and node β herein.Power supply GND, power vd D3, power vd D, threshold value VthN and to deduct the satisfied relation of value (VDD-VthN) that threshold value VthN obtained from power vd D be GND<VthN<VDD3<(VDD-VthN).In Figure 10 A, when signal inb was in the H level, the gate electrode current potential of N-type TFT1001 just became VDD3.Satisfy VthN<VDD3, the result just can make N-type TFT1001 conducting, and the current potential of node alpha rises to VDD one side, and becomes at this current potential subsequently and obtain quick condition when deducting the value (VDD3-VthN) that threshold value VthN obtained from power vd D3.That is to say,, just can guarantee that node alpha enters quick condition, and finish the action of the gate electrode current potential that promotes N-type TFT1003 by bootstrapping if signal inbH level surpasses VthN.On the other hand, in Figure 10 B, the gate electrode current potential of N-type TFT1006 is VDD all the time.Therefore, when signal inb was in the H level, the current potential of node β will rise to VDD3.Yet, satisfy at this moment that VDD3<(VDD-VthN), the result makes N-type TFT1006 remain conducting state, irrelevant with the current potential of input signal.Like this, node β just can not enter quick condition.Therefore just can not promote the current potential of node β with bootstrapping.That is to say under the situation shown in Figure 10 B, a lowest term that makes node β enter quick condition is arranged, that is to say, when the L of signal inb level was GND, its H level was not less than (VDD-VthN) at least.Therefore, the fluctuation from low voltage drive and TFT characteristic is imperfect.

As mentioned above, under the situation of amplitude less than supply voltage of input signal, under certain actual conditions, the structure shown in Figure 10 B also exists node β can not enter the risk of quick condition.On the other hand, the advantage that structure of the present invention obtained shown in Figure 10 A is to guarantee that node alpha enters quick condition.

The present invention with said structure can provide a kind of semiconductor device, it can by low cost with one of N-type or P-type only a kind of TFT of polarity make, thereby reduce manufacturing step, and can obtain not have the output of amplitude fading.

Below example of the present invention to be described.

[example 1]

To a kind of circuit that connect into multistage inverter with the present invention be described to 3C with reference to Fig. 3 A in this example.

Be connected with multistage inverter in the circuit that Fig. 3 A represents, each level all is the pattern of semiconductor device of the present invention (drive circuit of display device).In the drive circuit of this display device, often sort circuit is used as buffer.In the semiconductor device of the present invention shown in Fig. 3 A,, reduced manufacturing step, thereby can reduce manufacturing cost owing to be to adopt only a kind of TFT of polarity of one of N-type or P-type.And then can also obtain not have the output of amplitude fading.Yet, under the situation that adopts circuit shown in Fig. 3 A, a bit merit attention in addition from the angle of the electrical power of circuitry consumes.

In Fig. 3 A, when input signal was in the H level, N-type TFT302 was switched on.At this moment, N-type TFT301 by the load of short circuit, and always works in saturation condition as a grid and drain electrode.Therefore, when N-type TFT302 conducting, there is electric current between VDD and GND, to flow.To TFT303 at different levels, 304 and 305,306 also is the same.Consequently consumed current becomes very big.

For fear of this problem, shown in Fig. 3 B, can consider to adopt the method for two imported inverters.For the sort circuit that TFT is arranged between VDD and the GND, the polarity of input signal is opposite each other all the time, just carries out ETTHER-OR operation, thereby does not have electric current and flow through.

Yet under the situation that adopts circuit shown in Fig. 3 B, the signal that anti-phase and noninverting two kinds of phase places need be provided is as input signal.

Then, as the two combining structure of semiconductor device shown in semiconductor device shown in Fig. 3 A and Fig. 3 B, shown in Fig. 3 C, the first order adopts the imported inverter of list of the present invention, and the second level is used two imported inverters later on.As partial input, the output signal of prime is imported as one of them, and the input signal of prime is imported as another.Such circuit can be used as an imported buffer of list, and the electric current that will flow through is suppressed at minimum.

In having the semiconductor device of the present invention of said structure,, reduced manufacturing step, thereby can reduce manufacturing cost, and can obtain not have the output of amplitude fading owing to be to adopt only a kind of TFT of polarity of one of N-type or P-type.

[example 2]

Semiconductor device of the present invention (drive circuit of display device) is easy to as level shifter, and a promptly given current potential different with the amplitude current potential of input signal is as the power supply potential that offers circuit.It below is exactly an example.

At first considering will be such as GND, and three kinds of current potentials of VDD1 and VDD2 are as power supply potential, and supposes that their magnitude relationship is GND<VDD1<VDD2.The situation that this place is considered is that amplitude of input is the signal of GND-VDD1 and is transformed into the signal that amplitude is GND-VDD2, extracts this signal then.

Fig. 4 A represents an example.The structure of circuit is identical with the embodiment of example 1.The amplitude of input signal is GND-VDD1, and the power supply potential that is connected to impurity range one end of N-type TFT401 and 403 is expressed as VDD2.

Below want the operation of rendering circuit.Fig. 4 B represents the waveform of input signal.Amplitude is the gate electrode that the input signal of GND-VDD1 is imported into N-type TFT402 and 404.When input signal was in the H level, N-type TFT402 and 404 was switched on, and the current potential on the node alpha is dropped to GND one side, and N-type TFT403 is turned off.Like this, the current potential on the output node will become the L level.

When input signal was in the L level, N-type TFT402 and 404 was turned off, and the current potential on the output node α rises to VDD2 one side.Like this, N-type TFT403 just is switched on, and the current potential of output node is risen.On the other hand, on node alpha, when current potential becomes when power vd D2 deducts the value (the threshold voltage absolute value of VDD2-N-type TFT403) that the threshold voltage absolute value of N-type TFT403 obtained, it will enter quick condition.Then, along with the rising of output node current potential, the current potential of node alpha is present in the grid of N-type TFT403 and the capacitive coupling between the source electrode further promotes, and reaches the current potential (Fig. 4 C) that is higher than VDD2 then.Like this, the current potential of output node will become the H level, and output amplitude is the signal (solid line among Fig. 4 D) of GND-VDD2.

Why be used as the reason of level shifter easily as for the circuit shown in this example, the signal input that can notice the low-voltage value does not offer the TFT401 that is connected to high potential one side power supply (VDD2) and 403 gate electrode.In two imported circuit shown in Fig. 5 A, even the signal of low-voltage value is inputed to the TFT501 that is connected to high potential one side power supply (VDD2), the current potential of node β is the highest also to be risen near VDD1.Therefore, TFT503 just is not enough to be switched on, and just can't promote the gate electrode current potential of TFT503 like this with capacitive coupling, therefore just can't finish its normal running.

Therefore, shown in Fig. 5 B, applying heavy duty immediately and need after the level shifter shown in this example with regard to needing to use the imported circuit of list of secondary, makes all amplitudes of input signal all become the high voltage amplitude under a kind of like this situation of buffer structure then.In Fig. 5 B, the TFT that is transfused to the low-voltage amplitude signal only limits to that part of TFT that surrounded by frame of broken lines 506, when connecting into the imported circuit of secondary list, the signal of high voltage amplitude is imported into two inputs (being input to the gate electrode of TFT507 and 508) of the third level, so just can carry out normal operation.

Comprise at the signal that is used for carrying out the amplitude conversion under the situation of inversion signal and can adopt a kind of like this structure, use of the anti-phase input of mutual output signal therein as next stage.Fig. 6 represents an example, represents input signal with " in " and " inb ", and they are imported into the gate electrode of TFT602 and 614 respectively.The output of first order level shifter 650 is imported into second level TFT606 and 617, and the output of first order level shifter 660 is imported into second level TFT605 and 618.Being input to partial two signals all is the high voltage amplitude, and therefore, back level shift unit just can play the effect of buffer, obtains output signal " out " and " outb " from final stage then.

According to semiconductor device of the present invention,, reduced manufacturing step, thereby can reduce manufacturing cost, and can obtain not have the output of amplitude fading owing to be to adopt only a kind of TFT of polarity of one of N-type or P-type with said structure.

[example 3]

Will provide an example in this example, display device wherein is to adopt semiconductor device of the present invention (drive circuit of display device) to make.

Fig. 7 is the schematic diagram of a display device.Source signal line drive circuit 701, signal line drive circuit 702 and a pixel parts 703 are concentrated to be produced on the substrate 700.In pixel parts, represented a pixel by the part that dotted line 710 surrounds.The example of Fig. 7 is represented a pixel of liquid crystal display device, is offered the electric charge of an electrode of liquid crystal display cells by a TFT (hereinafter referred to as pixel TFT) control.The signal that is input to source signal line drive circuit 701 and signal line drive circuit 702 provides from the outside by a flexible print circuit (FPC) 704.

Substrate with pixel TFT and drive circuit can be made according to known method, for example described in the U.S. Pat 5,889,291 of authorizing people such as Koyama.Can also utilize a kind of metallic element that promotes crystallization to make the semiconductor thin film crystallization of the active layer that is used as TFT, can certainly adopt the additive method that impels crystallization.For example, in the U.S. Pat 5,643,826 of authorizing people such as Ohtani, disclose a kind of method of using metallic element.U.S. Pat 5,889,291 and US5,643,826 full text can be used as the reference of this paper.

Display device shown in this example is to constitute with semiconductor device of the present invention (drive circuit of display device), and composition comprises that the drive circuit of the whole display device of pixel parts is to make of only a kind of TFT of polarity (for example being N-type TFT) identical with pixel TFT.So just can save is the ion doping step that a semiconductor layer is given the P type, thereby helps to reduce the raising of manufacturing cost and output.

Although forming the polarity of the TFT of this routine display device is the N type,, much less also can only form drive circuit and pixel TFT with P type TFT according to the present invention.Just can save in this case is the ion doping step that a semiconductor layer is given the N type.The present invention not only can be applied to liquid crystal display device, concentrates the method that forms drive circuit to make on an insulator so long as adopt, and it can also be used for any device.

[example 4]

Semiconductor device of the present invention (drive circuit of display device) can be used for making the display device that uses for various electronic equipments.These electronic equipments comprise portable data assistance (electronic memo, mobile computer, cell-phone or the like), video camera, digital camera, personal computer, television set, cell-phone or the like.Fig. 8 A represents these examples to 8G.

Fig. 8 A represents by shell 3001, bracing frame 3002, a kind of LCD (LCD) that display part 3003 grades are formed.Semiconductor device of the present invention (drive circuit of display device) can be used for making display part 3003.

Fig. 8 B represents by main body 3011, display part 3012, audio frequency importation 3013, console switch 3014, battery 3015, a kind of video camera that image receiving unit 3016 grades are formed.Semiconductor device of the present invention (drive circuit of display device) can be used for making display part 3012.

Fig. 8 C represents by main body 3021, shell 3022, display part 3023, a kind of notebook-sized personal computer that keyboard 3024 grades are formed.Semiconductor device of the present invention (drive circuit of display device) can be used for making display part 3023.

Fig. 8 D represents by main body 3031, input pen 3032, display part 3033, action button 3034, the portable data assistance that external interface 3035 grades are formed.Semiconductor device of the present invention (drive circuit of display device) can be used for making display part 3033.

Fig. 8 E represents a kind of sound-reproducing system, specifically is by main body 3041, display part 3042, console switch 3043 and a kind of vehicle audible devices of forming such as 3044.Semiconductor device of the present invention (drive circuit of display device) can be used for making display part 3042.In addition, although expression in this example is vehicle audible device, the present invention also can be used for hand-held or family expenses acoustics.

Fig. 8 F represents by main body 3051, display part (A) 3052, eyepiece part 3053, console switch 3054, display part (B) 3055, a kind of digital camera that battery 3056 grades are formed.Semiconductor device of the present invention (drive circuit of display device) can be used for making display part (A) 3052 and display part (B) 3055.

Fig. 8 G represents that audio output part divides 3062 by main body 3061, audio frequency importation 3063, display part 3064, a kind of cell-phone that console switch 3065 and antenna 3066 etc. are formed.Semiconductor device of the present invention (drive circuit of display device) can be used for making display part 3064.

Above-described only is some examples, and the present invention is not limited only to these application.

According to semiconductor device of the present invention (drive circuit of display device), can be only form the drive circuit of display device and the pixel parts of display device with a kind of TFT of conduction type.Can also reduce the manufacturing step of display device, thereby by means of reducing cost and improving output.So just can provide more cheap display device.In addition, adopt the present invention that a kind of semiconductor device can also be provided, it can obtain not have the output of amplitude fading.

Claims (20)

1. a semiconductor device comprises:
The single imported circuit of the first order, the single imported circuit in the second level and the third level two imported circuit comprise separately:
The first film transistor with first impurity range that is electrically connected to first power supply;
Second thin-film transistor with first impurity range that is electrically connected to second source;
The 3rd thin-film transistor with first impurity range that is electrically connected to described first power supply;
The 4th thin-film transistor with first impurity range that is electrically connected to described second source, wherein:
Described first to the 4th thin-film transistor has the identical conduction type;
Second impurity range of transistorized second impurity range of described the first film and described second thin-film transistor is electrically connected to a terminal of an electric capacity;
Second impurity range of described the 3rd thin-film transistor, second impurity range of described the 4th thin-film transistor and the transistorized gate electrode of described the first film are electrically connected to another terminal of described electric capacity;
The gate electrode of second thin-film transistor and the gate electrode of described the 4th thin-film transistor are electrically connected to first input signal cable described in the single imported circuit of the wherein said first order;
The gate electrode of the 3rd thin-film transistor is electrically connected to described first power supply described in the single imported circuit of the wherein said first order;
The gate electrode of the gate electrode of second thin-film transistor and described the 4th thin-film transistor is electrically connected to the lead-out terminal of the single imported circuit of the described first order described in the single imported circuit in the wherein said second level,
The gate electrode of the 3rd thin-film transistor is electrically connected to described first power supply described in the single imported circuit in the wherein said second level,
The gate electrode of the gate electrode of second thin-film transistor and described the 4th thin-film transistor described in the wherein said third level two imported circuit is electrically connected to the lead-out terminal of the single imported circuit in the described second level, and
The gate electrode of the 3rd thin-film transistor described in the wherein said third level two imported circuit is electrically connected to the lead-out terminal of the single imported circuit of the described first order.
2. according to the semiconductor device of claim 1, the electric capacity between wherein said electric capacity one of adopts in transistorized gate electrode of described the first film and the described impurity range.
3. according to the semiconductor device of claim 1, wherein said electric capacity is by using the electric capacity that any two kinds of materials are formed in a kind of active layer material, a kind of material that constitutes described gate electrode and a kind of conductor material.
4. according to the semiconductor device of claim 1, wherein said the sort of conduction type is the N-channel-type.
5. according to the semiconductor device of claim 1, wherein said the sort of conduction type is the P-channel-type.
6. according to the semiconductor device of claim 1, wherein:
Described the sort of conduction type is the N-channel-type;
Current potential when input signal is in high level equals the 3rd power supply potential, and the current potential when described input signal is in low level equals the 4th power supply potential; And
Satisfy the relation of second source current potential≤the 4th power supply potential<the 3rd power supply potential≤first power supply potential.
7. according to the semiconductor device of claim 1, wherein:
Described the sort of conduction type is the P-channel-type;
Current potential when input signal is in high level equals the 3rd power supply potential, and the current potential when described input signal is in low level equals the 4th power supply potential; And
Satisfy the relation of first power supply potential≤the 4th power supply potential<the 3rd power supply potential≤second source current potential.
8. according to the semiconductor device of claim 1, wherein said semiconductor device is a level shifter.
9. according to the semiconductor device of claim 1, wherein said semiconductor device is applied to being selected from by a kind of electronic equipment in LCD, the group that video camera, notebook-sized personal computer, portable data assistance, vehicle audible device, digital camera and cell-phone constituted.
10. display device comprises:
The single imported circuit of the first order, the single imported circuit in the second level and the third level two imported circuit comprise separately:
The first film transistor with first impurity range that is electrically connected to first power supply;
Second thin-film transistor with first impurity range that is electrically connected to second source;
The 3rd thin-film transistor with first impurity range that is electrically connected to described first power supply;
The 4th thin-film transistor with first impurity range that is electrically connected to described second source, wherein:
Described first to the 4th thin-film transistor has the identical conduction type;
Second impurity range of transistorized second impurity range of described the first film and described second thin-film transistor is electrically connected to a terminal of an electric capacity;
Second impurity range of described the 3rd thin-film transistor, second impurity range of described the 4th thin-film transistor and the transistorized gate electrode of described the first film are electrically connected to another terminal of described electric capacity;
The gate electrode of second thin-film transistor and the gate electrode of described the 4th thin-film transistor are electrically connected to first input signal cable described in the single imported circuit of the wherein said first order;
The gate electrode of the 3rd thin-film transistor is electrically connected to described first power supply described in the single imported circuit of the wherein said first order;
The gate electrode of the gate electrode of second thin-film transistor and described the 4th thin-film transistor is electrically connected to the lead-out terminal of the single imported circuit of the described first order described in the single imported circuit in the wherein said second level,
The gate electrode of the 3rd thin-film transistor is electrically connected to described first power supply described in the single imported circuit in the wherein said second level,
The gate electrode of the gate electrode of second thin-film transistor and described the 4th thin-film transistor described in the wherein said third level two imported circuit is electrically connected to the lead-out terminal of the single imported circuit in the described second level, and
The gate electrode of the 3rd thin-film transistor described in the wherein said third level two imported circuit is electrically connected to the lead-out terminal of the single imported circuit of the described first order.
11. a semiconductor device comprises:
The single imported circuit of the single imported circuit of the first order and the second level comprises separately:
The first film transistor with first impurity range that is electrically connected to first power supply;
Second thin-film transistor with first impurity range that is electrically connected to second source;
Output amplitude compensating circuit with input terminal and lead-out terminal, wherein said lead-out terminal are electrically connected to the transistorized gate electrode of described the first film,
Wherein:
The channel formation region of described first and second thin-film transistors has the identical conduction type;
Second impurity range of transistorized second impurity range of described the first film and described second thin-film transistor is electrically connected to output signal line;
The gate electrode of second thin-film transistor and the input terminal of described output amplitude compensating circuit are electrically connected to input signal cable described in the single imported circuit of the wherein said first order;
The input terminal of the gate electrode of second thin-film transistor and described output amplitude compensating circuit is electrically connected to the lead-out terminal of the single imported circuit of the described first order described in the single imported circuit in the wherein said second level, and
The lead-out terminal of the single imported circuit of the lead-out terminal of the single imported circuit of the wherein said first order and the described second level is electrically connected to the third level two imported circuit.
12. according to the semiconductor device of claim 11, wherein said output amplitude compensating circuit comprises:
The 3rd thin-film transistor with first impurity range that is electrically connected to described first power supply;
The 4th thin-film transistor with first impurity range that is electrically connected to described second source.
13. according to the semiconductor device of claim 12, the gate electrode of wherein said the 3rd thin-film transistor is electrically connected to first impurity range of described the 3rd thin-film transistor.
14. according to the semiconductor device of claim 12, the gate electrode of wherein said the 4th thin-film transistor is electrically connected to described input signal cable.
15. according to the semiconductor device of claim 12, second impurity range of wherein said the 3rd thin-film transistor and second impurity range of described the 4th thin-film transistor are electrically connected to the transistorized gate electrode of described the first film.
16. a display device comprises:
The single imported circuit of the single imported circuit of the first order and the second level comprises separately:
The first film transistor with first impurity range that is electrically connected to first power supply;
Second thin-film transistor with first impurity range that is electrically connected to second source;
Output amplitude compensating circuit with input terminal and lead-out terminal, wherein said lead-out terminal are electrically connected to the transistorized gate electrode of described the first film,
Wherein:
The channel formation region of described first and second thin-film transistors has the identical conduction type;
Second impurity range of transistorized second impurity range of described the first film and described second thin-film transistor is electrically connected to output signal line;
The gate electrode of second thin-film transistor and the input terminal of described output amplitude compensating circuit are electrically connected to input signal cable described in the single imported circuit of the wherein said first order;
The input terminal of the gate electrode of second thin-film transistor and described output amplitude compensating circuit is electrically connected to the lead-out terminal of the single imported circuit of the described first order described in the single imported circuit in the wherein said second level,
The lead-out terminal of the single imported circuit of the lead-out terminal of the single imported circuit of the wherein said first order and the described second level is electrically connected to the third level two imported circuit.
17. according to the display device of claim 16, wherein said output amplitude compensating circuit comprises:
The 3rd thin-film transistor with first impurity range that is electrically connected to described first power supply;
The 4th thin-film transistor with first impurity range that is electrically connected to described second source.
18. according to the display device of claim 17, the gate electrode of wherein said the 3rd thin-film transistor is electrically connected to first impurity range of described the 3rd thin-film transistor.
19. according to the display device of claim 17, the gate electrode of wherein said the 4th thin-film transistor is electrically connected to described input signal cable.
20. according to the display device of claim 17, second impurity range of wherein said the 3rd thin-film transistor and second impurity range of described the 4th thin-film transistor are electrically connected to the transistorized gate electrode of described the first film.
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US8284151B2 (en) 2012-10-09
US9136385B2 (en) 2015-09-15

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