CN1588819B - Information transmission system and method and its output signal driving device - Google Patents
Information transmission system and method and its output signal driving device Download PDFInfo
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- CN1588819B CN1588819B CN 200410083430 CN200410083430A CN1588819B CN 1588819 B CN1588819 B CN 1588819B CN 200410083430 CN200410083430 CN 200410083430 CN 200410083430 A CN200410083430 A CN 200410083430A CN 1588819 B CN1588819 B CN 1588819B
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Abstract
A signal transmission system includes a signal output unit and a receive unit, among which, the output unit receives a first signal and outputs a second, the receive unit receives a second signal and outputs a third. The signal output unit includes an inverter and an output signal drive device, the inverter receives a first signal and outputs a first inversion signal, the output-signal drive device receives a first inversion signal and outputs a second signal including a first and second NMOS transistors, the drain of the first NMOS is biased on the first voltage and its grid receives the control signal, the grid of the second receives the first inverted signal which source is biased on a second voltage, its drain is coupled with the source of the first and outputs the second signal.
Description
Technical field
The relevant a kind of signal transmission system of the present invention, and particularly about a kind of signal transmission system and method and output signal driving device thereof.
Background technology
Generally during by long transmission line signal, can cause suitable power dissipation at circuit.Because signal when transmission, the power of consumption be proportional to voltage square, so can use a kind of signal transmission system usually; first at output with the signal step-down; with lower voltage level transmission signals, to reduce the loss of power, it is accurate signal to be risen to original position at receiving terminal then again during transmission.
Please refer to Fig. 1, it is the Organization Chart of classical signal transmission system.Signal transmission system 100 comprises classical signal output unit 110 and signal receiving unit 120.After classical signal output unit 110 receives the first signal S1, the less position of output device accurate but with the secondary signal S2 of the first signal S1 homophase.Receive secondary signal S2 by signal receiving unit 120 again, and export the 3rd signal S3, and the 3rd signal S3 is identical with the first signal S1.With the signal step-down, after the reception signal is risen back the purpose of original position standard when promptly reaching transmission.
Please refer to Fig. 2, it is the circuit diagram of expression classical signal transmission system.Classical signal output unit 110 comprises anti-phase device 112 and anti-phase device 114.Anti-phase device 112 is to be an existing C MOS inverter, and in order to receive the first signal S1 and to export the first inversion signal S1 ', the first inversion signal S1 ' is anti-phase with the first signal S1.Anti-phase device 112 comprises N type metal oxide semiconductor (NMOS) transistor T 1 and P-type mos (PMOS) transistor T 2, and the source electrode of PMOS transistor T 2 is biased in principal voltage Vh.
Anti-phase device 114 also is an existing C MOS inverter, in order to receive the first inversion signal S1 ' and to export secondary signal S2.Anti-phase device 114 comprises nmos pass transistor T3 and PMOS transistor T 4, and the source electrode of PMOS transistor T 4 is biased in a principal voltage V1, and principal voltage V1 is little than the first principal voltage Vh.Because of principal voltage V1 is little than principal voltage Vh, then can reach the secondary signal S2 and the first signal S1 homophase, and the position of secondary signal S2 is accurate little than the first signal S1.
Though above-mentioned signal transmission system can be avoided power loss when transmission, yet, because transmission line 130 itself has suitable length, so make transmission line 130 equivalent resistances and the pairing time constant of equivalent capacity to produce certain influence to the transmission speed of signal.The MOS transistor that so, then needs to have than high current drive capability just can make the position standard of transmission line 130 promptly be promoted to desired position standard.
Yet in traditional CMOS inverter 114, because the rough electron mobility μ n that equals 1/3 times NMOS of electron mobility μ p of PMOS, so the transistorized service speed of PMOS is slower, and current driving ability is relatively poor.If will allow the PMOS transistor produce bigger electric current, to increase its current driving ability, (aspect ratio W/L), and makes classical signal output unit 110 take bigger area then must to increase its transistor outward appearance breadth length ratio.Therefore, the area that how to reduce signal output unit is one of problem of endeavouring of industry.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of signal transmission system and signal output unit, can
When transmission signals,, and again signal is risen back the original position standard,, improve driving force and speed transmission speed to reach the saving area at receiving terminal with the signal step-down.
According to an aspect of the present invention, propose a kind of signal transmission system, comprise signal output unit and signal receiving unit.Signal output unit in order to receive the less position of first signal and output device accurate and with the secondary signal of the first signal homophase.Signal receiving unit is in order to receive secondary signal and output three signal identical with first signal.Signal output unit comprises anti-phase device and output signal driving device.Anti-phase device is in order to receive first inversion signal of first signal and the output and first signal inversion.Output signal driving device is in order to receive first inversion signal and to export secondary signal to signal receiving unit.Output signal driving device comprises first nmos pass transistor and second nmos pass transistor.The drain bias of first nmos pass transistor is in first voltage, and its grid receives the control signal with the first signal homophase, and the drain electrode of its source electrode and second nmos pass transistor couples, and exports a secondary signal.The grid of second nmos pass transistor receives first inversion signal, and its source electrode is biased in second voltage little than first voltage.
According to a further aspect of the invention, propose a kind of method for transmitting signals, be used for an output signal driving device.Output signal driving device and anti-phase device electrically connect, and anti-phase device receives first signal and exports first inversion signal, and output signal driving device is exported secondary signal after receiving first inversion signal.Output signal driving device comprises first nmos pass transistor and second nmos pass transistor.The source electrode of first nmos pass transistor and the 2nd PMOS transistor drain couple and in order to output secondary signal.The drain bias of first nmos pass transistor is in first voltage, and the grid of first nmos pass transistor receives control signal, and control signal is and the first signal homophase.The source electrode of second nmos pass transistor is biased in second voltage, and second voltage is less than first voltage.The grid of second nmos pass transistor is in order to receive first inversion signal.At first, when first signal was first low level, control signal was the control signal low level, and first nmos pass transistor ends, the second nmos pass transistor conducting.And work as first signal is first high levels, and control signal is the control signal high levels, the first nmos pass transistor conducting, and second nmos pass transistor ends, the source electrode output of first nmos pass transistor and the secondary signal of the first signal homophase.
For above-mentioned purpose of the present invention, characteristics and advantage can be become apparent, will be elaborated to preferred embodiment of the present invention in conjunction with the accompanying drawings down.
Description of drawings
Fig. 1 is the Organization Chart of classical signal transmission system.
Fig. 2 is the circuit diagram of classical signal transmission system.
Fig. 3 is the Organization Chart according to the signal transmission system of one first embodiment of the present invention.
Fig. 4 is the Organization Chart according to the signal transmission system of one second embodiment of the present invention.
Fig. 5 is the Organization Chart according to the signal transmission system of one the 3rd embodiment of the present invention.
Fig. 6 is the Organization Chart according to the signal transmission system of one the 4th embodiment of the present invention.
Fig. 7 is the Organization Chart according to the signal transmission system of one the 5th embodiment of the present invention.
Fig. 8 is the Organization Chart according to the signal transmission system of one the 6th embodiment of the present invention.
Fig. 9 is the analog result figure of classical signal transmission system and the 3rd embodiment.
Figure 10 is another illustration intention of anti-phase device.
Figure 11 is the schematic diagram that expression signal transmission system of the present invention is applied to display panels.
Embodiment
Embodiment one
Please refer to Fig. 3, it is the Organization Chart according to the signal transmission system of one first embodiment of the present invention.Signal transmission system 300 comprises signal output unit 310 and signal receiving unit 320.Signal output unit 310 receives the first signal P1, and the secondary signal P2 of the output and the first signal P1 homophase is to signal receiving unit 320, and first high levels of the first signal P1 (for example being 7V) is greater than second high levels (for example being 3V) of secondary signal P2.Then, signal receiving unit 320 receives secondary signal P2, and exports the 3rd signal P3.First high levels of the first signal P1 is identical with the 3rd high levels of the 3rd signal P3.
Signal output unit 310 comprises anti-phase device 312 and output signal driving device 314.Anti-phase device 312 is in order to receive the first anti-phase inversion signal P1 ' of the first signal P1 and output and the first signal P1 to output signal driving device 314.Output signal driving device 314 is according to first inversion signal P1 ' output secondary signal P2.Anti-phase device 312 for example is the CMOS inverter, be made up of nmos pass transistor Q1 and PMOS transistor Q2, and the source electrode of nmos pass transistor Q1 is biased in a low-voltage Vss, and the source electrode of PMOS transistor Q2 is biased in principal voltage Vh (for example being 7V).Wherein, low-voltage Vss for example is earthed voltage (ground).
314 of output signal driving devices comprise nmos pass transistor Q3 and nmos pass transistor Q4.The drain bias of nmos pass transistor Q3 is in principal voltage V1 (for example being 3V), and its grid receives the control signal Pcon with the first signal P1 homophase, and its source electrode is that the drain electrode with nmos pass transistor Q4 couples, and output secondary signal P2.The grid of nmos pass transistor Q4 receives the first inversion signal P1 ', and its source electrode is biased in low-voltage Vss.The magnitude relationship of principal voltage Vh, principal voltage V1 and low-voltage Vss is as follows: principal voltage Vh is greater than principal voltage V1, and principal voltage V1 is greater than low-voltage Vss.Wherein, output signal driving device 314 satisfy following condition can normal running: control signal Pcon when a control signal high levels, this control signal high levels must be greater than limit voltage (the Threshold Voltage of second high levels and nmos pass transistor Q3, Vtn) sum, nmos pass transistor Q3 conducting this moment, not conducting of nmos pass transistor Q4.
Now the principle with above-mentioned condition is summarized as follows: as control signal Pcon during in the control signal high levels, the voltage of transmission line 330 reaches as high as second high levels, and second high levels equals or approaches principal voltage V1 at this moment, and the condition that need nmos pass transistor Q3 to continue conducting this moment is:
Vgs (Q3) (grid of nmos pass transistor Q3 and the voltage level of source electrode are poor)＞Vtn;
Control signal high levels-second high levels＞Vtn of Vgs (Q3)=control signal Pcon;
Control signal high levels＞second high levels+Vtn, promptly above-mentioned condition.
Signal transmission system that the above embodiment of the present invention disclosed and output signal driving device can reach script and require to reduce outside the signal power loss purpose, and have following advantage again: signaling rate is very fast, and area occupied is less and current driving ability is strong.So, can meet high speed transmission of signals and the light little purpose of electronic installation requirement now.
Embodiment two
Please refer to Fig. 4, it is the Organization Chart according to the signal transmission system of one second embodiment of the present invention.With embodiment one difference be in output signal driving device 314, the grid of nmos pass transistor Q3 receives control signal Pcon; And in the output signal driving device 414, the grid of nmos pass transistor Q3 receives the first signal P1, and other conditions are identical.In embodiment one, requiring of control signal Pcon is as follows: 1. control signal Pcon must be greater than second high levels and Vtn value sum when high levels.2. the control signal Pcon and the first signal P1 must homophases.If first high levels of the first signal P1 promptly greater than the Vtn value sum of second high levels and nmos pass transistor Q3, then can replace control signal Pcon with the first signal P1.
Known in embodiment one, control signal Pcon is when the control signal high levels, and the high charge of transmission line 330 is to principal voltage V1, if the condition that needs nmos pass transistor Q3 to continue conducting is:
Control signal high levels＞second high levels+Vtn.
And in present embodiment, be with the first signal P1 as control signal Pcon, so following formula is:
First high levels＞second high levels+Vtn.
Because first high levels equals principal voltage Vh, so can get:
Principal voltage Vh＞second high levels+Vtn.
And second high levels equals principal voltage V1 in fact, can get following formula:
Principal voltage Vh＞principal voltage V1+Vtn.When the grid of nmos pass transistor received the first signal P1 with replacement reception control signal Pcon, can get condition: principal voltage Vh needed greater than principal voltage V1 and Vtn sum.
Embodiment three
Please refer to Fig. 5, it is the Organization Chart of the signal transmission system of expression one the 3rd embodiment.With embodiment one difference is to increase PMOS transistor Q5 in output signal driving device 514 than output signal driving device 314.The source electrode of PMOS transistor Q5 is that the drain electrode with nmos pass transistor Q3 couples, and its grid is that the grid with nmos pass transistor Q4 couples, and its drain electrode is that the source electrode with this nmos pass transistor Q3 couples, and other conditions are identical.And among this embodiment, the condition of control signal high levels＞second high levels+Vtn is also arranged.
Please refer to Fig. 9, it is the analog result figure for classical signal transmission system and the 3rd embodiment.Signal OUT1 is the output signal for anti-phase device 114, and signal OUT2 is the output signal for output signal driving device 514, and signal IN is the signal of while input signal output unit 110 and signal output unit 510.(aspect ratio W/L) can have influence on the transmission speed and the driving force of signal, and therefore following simulation is to confirm the advantage of present embodiment because of transistor outward appearance breadth length ratio.
The W/L such as the following setting of the MOS transistor in the anti-phase device 114 of output signal driving device 514 and prior art: the W/L value of the PMOS transistor T 4 of anti-phase device 114 is 1000um/6um, the W/L value of the PMOS transistor Q5 of output signal driving device 514 is 1000um/6um, the W/L value of nmos pass transistor Q3 is 50um/6um, and other conditions are identical.And by among Fig. 9 as can be known, the rise time of signal OUT1 (rise time) is about 1us, and the rise time of signal OUT2 is 0.6us.This moment with the area of the area of PMOS transistor T 4 and nmos pass transistor Q3 and PMOS transistor Q5 with make comparisons, the area of nmos pass transistor Q3 and PMOS transistor Q5 and only increase by 5% than the area of PMOS transistor T 4, find obviously that but the signal OUT2 of output has reduced 40% than the rise time of signal OUT1 when same input signal IN.Thus, can obviously find out the improvement of driving force of present embodiment and the lifting of transmission speed.
On the other hand, if desire is adjusted by the rise time of signal OUT2 and the rise time of signal OUT1 is all 1us.Through experimentation, the W/L value of PMOS transistor Q5 only needs 200um/6um, and the W/L value of nmos pass transistor Q3 only needs 50um/6um, its transistor area and be (250um*6um), much smaller than the area (1000um*6um) of PMOS transistor T 4, reach the purpose of saving the signal transmission system area.
Embodiment four
Please refer to Fig. 6, it is the Organization Chart of the signal transmission system of expression one the 4th embodiment.With the 3rd embodiment difference be in output signal driving device 514, the grid of nmos pass transistor Q3 receives control signal Pcon; And in the output signal driving device 614, the grid of nmos pass transistor Q3 receives the first signal P1, and other conditions are identical.And among this embodiment as embodiment two, also must meet the condition of principal voltage Vh greater than principal voltage V1 and Vtn sum.
Embodiment five
Please refer to Fig. 7, it is the Organization Chart for the signal transmission system of one the 5th embodiment.Be that with the 3rd embodiment difference output signal driving device 714 has more an accurate translation device (Level shifter) 716 than output signal driving device 514.The position standard that the accurate translation device 716 in position receives the 4th signal P4 and amplifies the 4th signal P4 is with the grid of output control signal Pcon to nmos pass transistor Q3.And the 4th signal P4 and the first signal P1 homophase.Certainly, as embodiment three, this embodiment also must meet the condition of control signal high levels greater than second high levels and Vtn sum.
Embodiment six
Please refer to Fig. 8, it is the Organization Chart for the signal transmission system of one the 6th embodiment.Be that with the 5th embodiment difference the 4th signal P4 that the accurate translation device 716 in position receives replaces with the first signal P1.And among this embodiment, the condition of principal voltage Vh greater than principal voltage V1 and Vtn sum also arranged.
Please refer to Figure 10, it is another example of the anti-phase device of expression.Anti-phase device 912 includes x CMOS inverter, comprises CMOS inverter C1, CMOS inverter C2 to CMOS inverter Cx, and x is odd number.More than anti-phase device 312 among each embodiment, all can the current driving ability of signal output unit be increased, and then promote the transmission speed of signal by 912 replacements of anti-phase device.Yet if make anti-phase device 912 replace anti-phase device 312, control signal Pcon also can be by the input signal replacement of m CMOS inverter Cm in the anti-phase device 912 except can the first signal P1 substituting, and wherein m is an odd number and less than x.And condition is principal voltage Vhm＞principal voltage V1+Vtn, and principal voltage Vhm is the principal voltage of CMOS inverter Cm.
Please refer to Figure 11, it is the schematic diagram that expression signal transmission system of the present invention is applied to display panels.Display panels 111 comprises time schedule controller (Timing controller) 11a, data driver (Data driver) 11b, scanner driver (Scan driver) 11c and display floater 11d.The picture element signal that time schedule controller 11a is required with data driver 11b transfers to data driver 11b, drives display floater 11d by data driver 11b according to picture element signal again.Perhaps, the time schedule controller 11a sweep signal that scanner driver 11c is required transfers to scanner driver 11c, drives display floater 11d by scanner driver 11c according to sweep signal again.And when time schedule controller 11a outputs signal to data driver 11b or scanner driver 11c, must be by the transmission line 11e and the transmission line 11f of equivalent length.For avoiding signal to produce power dissipation concerns, can use aforesaid signal transmission system to be applied to this display panels.Signal output unit for example can be time schedule controller 11a, and signal receiving unit for example is data driver 11b or scanner driver 11c.And signal transmission system of the present invention is when being applied to display panels, nmos pass transistor Q1 wherein, nmos pass transistor Q3, nmos pass transistor Q4, PMOS transistor Q2 and PMOS transistor Q5 can reach by thin-film transistor (Thin Film Transistor, TFT LCD).
In sum; though the present invention discloses as above with a preferred embodiment; yet it is not in order to limit the present invention; any person skilled in the art person without departing from the spirit and scope of the present invention; when the change that can do various equivalences or replacement, so protection scope of the present invention is when looking accompanying being as the criterion that the application's claim scope defined.
Claims (10)
1. output signal driving device, itself and an anti-phase device electrically connect, this anti-phase device receives one first signal and exports one first inversion signal, and this output signal driving device receives this first inversion signal and exports a secondary signal, and this output signal driving device comprises:
One the one N type metal oxide semiconductor nmos pass transistor, the drain electrode of this first nmos pass transistor are to be biased in one first voltage, and the grid of this first nmos pass transistor is to receive a control signal, and this control signal is and this first signal homophase; And
One second nmos pass transistor, the grid of this second nmos pass transistor receives this first inversion signal, the source electrode of this second nmos pass transistor is biased in one second voltage, this second voltage is less than this first voltage, the drain electrode of the source electrode of this first nmos pass transistor and this second nmos pass transistor couples, and export this secondary signal, this secondary signal is and this first signal homophase;
One P-type mos PMOS transistor, the drain electrode of the transistorized source electrode of this PMOS and this first nmos pass transistor couples, the grid of the transistorized grid of this PMOS and this second nmos pass transistor couples, and the source electrode of this PMOS transistor drain and this first nmos pass transistor couples.
2. output signal driving device as claimed in claim 1 is characterized in that this control signal is this first signal.
3. output signal driving device as claimed in claim 1, it is characterized in that this output signal driving device also comprises an accurate translation device, this accurate translation device receives one the 3rd signal and amplifies the position standard of the 3rd signal, to export the grid that this controls signal to this first nmos pass transistor, the 3rd signal is and this first signal homophase.
4. output signal driving device as claimed in claim 3 is characterized in that the 3rd signal is this first signal.
5. signal transmission system comprises:
One signal output unit, in order to receive one first signal and to export a secondary signal, this signal output unit comprises:
One anti-phase device receives this first signal and exports one first inversion signal; And
One output signal driving device, in order to receive this first inversion signal and to export this secondary signal, this output signal driving device comprises:
One first nmos pass transistor, the drain bias of this first nmos pass transistor is in one first voltage, and the grid of this first nmos pass transistor receives a control signal, and this control signal is and this first signal homophase; And
One second nmos pass transistor, the grid of this second nmos pass transistor receives this first inversion signal, the source electrode of this second nmos pass transistor is biased in one second voltage, this second voltage is less than this first voltage, the drain electrode of the source electrode of this first nmos pass transistor and this second nmos pass transistor couples, and export a secondary signal, this secondary signal is and this first signal homophase;
One signal receiving unit in order to receiving this secondary signal, and is exported one the 3rd signal according to this, and the 3rd high levels of the 3rd signal is identical with first high levels of this first signal;
One PMOS transistor, the drain electrode of the transistorized source electrode of this PMOS and this first nmos pass transistor couples, and the grid of the transistorized grid of this PMOS and this second nmos pass transistor couples, and the source electrode of this PMOS transistor drain and this first nmos pass transistor couples;
Wherein, first high levels of this first signal is greater than second high levels of this secondary signal.
6. signal transmission system as claimed in claim 5 is characterized in that this anti-phase device comprises N CMOS inverter, and wherein N is an odd number.
7. signal transmission system as claimed in claim 5, it is characterized in that this output signal driving device also comprises an accurate translation device, this accurate translation device receives one the 4th signal and amplifies the position standard of the 4th signal, to export the grid that this controls signal to this first nmos pass transistor, the 4th signal is and this first signal homophase.
8. signal transmission system as claimed in claim 5 is characterized in that this signal output unit is the clock pulse controller of a display panels.
9. signal transmission system as claimed in claim 8 is characterized in that this signal receiving unit is the data driver of this display panels.
10. signal transmission system as claimed in claim 8 is characterized in that this signal receiving unit is the one scan driver of this display panels.
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| CN 200410083430 CN1588819B (en) | 2004-09-28 | 2004-09-28 | Information transmission system and method and its output signal driving device |
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| CN 200410083430 CN1588819B (en) | 2004-09-28 | 2004-09-28 | Information transmission system and method and its output signal driving device |
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| CN1588819B true CN1588819B (en) | 2010-12-08 |
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| CN100437729C (en) * | 2004-03-12 | 2008-11-26 | 新巨企业股份有限公司 | Voltage transformer pseudo-position drive circuit |
| CN101072050B (en) * | 2007-06-19 | 2010-08-25 | 北京意科通信技术有限责任公司 | System for data transmission via metal pipeline |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5095230A (en) * | 1990-05-28 | 1992-03-10 | Nec Corporation | Data output circuit of semiconductor device |
| US5896044A (en) * | 1997-12-08 | 1999-04-20 | Lucent Technologies, Inc. | Universal logic level shifting circuit and method |
| US6133757A (en) * | 1998-07-16 | 2000-10-17 | Via Technologies, Inc. | High-speed and low-noise output buffer |
| CN1351421A (en) * | 2000-10-30 | 2002-05-29 | 株式会社日立制作所 | Level shift circuit and semiconductor integrated circuits |
-
2004
- 2004-09-28 CN CN 200410083430 patent/CN1588819B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5095230A (en) * | 1990-05-28 | 1992-03-10 | Nec Corporation | Data output circuit of semiconductor device |
| US5896044A (en) * | 1997-12-08 | 1999-04-20 | Lucent Technologies, Inc. | Universal logic level shifting circuit and method |
| US6133757A (en) * | 1998-07-16 | 2000-10-17 | Via Technologies, Inc. | High-speed and low-noise output buffer |
| CN1351421A (en) * | 2000-10-30 | 2002-05-29 | 株式会社日立制作所 | Level shift circuit and semiconductor integrated circuits |
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