CN101388187B - Reset circuit apply to computer opening/closing - Google Patents
Reset circuit apply to computer opening/closing Download PDFInfo
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- CN101388187B CN101388187B CN2007101542248A CN200710154224A CN101388187B CN 101388187 B CN101388187 B CN 101388187B CN 2007101542248 A CN2007101542248 A CN 2007101542248A CN 200710154224 A CN200710154224 A CN 200710154224A CN 101388187 B CN101388187 B CN 101388187B
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- driver
- display
- gating pulse
- switch
- reset circuit
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Abstract
The invention provides a circuit which is used to reset a display which is equipped with at least a driver, wherein the driver outputs driving voltage to a corresponding data line of a panel via an output channel, the circuit comprises a first switch and a second switch, the first switch uses a control pulse to actuate, thereby transferring reset voltage to the data line of the panel. The second switch uses the control pulse to actuate, thereby insulating the output channel of the driver and the data line of the panel by electricity, the control pulse is produced in transient periods which are caused by power-on and power-off of the display.
Description
Technical field
The present invention relates to a kind of reset circuit that is applied to switching on and shutting down, and more particularly, The present invention be more particularly directed to a kind of in the source electrode driver of LCD (Liquid Crystal Display) panel the employed reset circuit that is applied to switching on and shutting down.
Background technology
That LCD (LCD) has is bright, thin, the feature of small size, low radiation and power saving.These features allow to reduce in office or the employed space of family, and help to reduce and continued long-time and kopiopia that cause owing to staring lcd screen.Therefore, in smooth display device, LCD has the potential that substitutes existing CRT (cathode-ray tube (CRT)).Fig. 1 shows employed LCD module among LCD monitor/TV.This LCD module comprises panel 2, source electrode driver unit 3, gate drivers unit 4 and time schedule controller 5.Time schedule controller 5 is by sending a control signal to the sequential and the sequence of demonstration that source electrode driver unit 3 and gate drivers unit 4 come the pixel of control chart picture.Writing in the pixel (figure does not show) of source electrode driver in the source electrode driver unit 3 control pixel value to the panel 2.Gate drivers in the gate drivers unit 4 is controlled the transistorized on/off operation of the metal-oxide semiconductor (MOS) (MOS) that is associated with pixel by signal GS.When energising of LCD monitor/TV or outage, power supply and from time schedule controller 5 signal to source electrode driver unit 3 unstable usually or be in a unknown state.Therefore, the output signal SS of source electrode driver unit 3 is in unknown state, thereby causes the noise like image on the panel 2.
The complaint that provides high quality image to show and reduce the consumer, the noise like when being necessary to eliminate switching on and shutting down on panel (noise-like) image are provided.
Summary of the invention
One aspect of the present invention is for providing a kind of circuit that is applied to replacement display when the switching on and shutting down, this circuit is by coming the corresponding data line of outputting drive voltage to panel based on the existing sequential (the existing timings of ananalog power supply and a digital power supply) of analog power and digital power via delivery channel, to eliminate the noise like image on the display.
Another aspect of the present invention is provides a kind of circuit that is applied to replacement display when switching on and shutting down, this circuit is by coming the corresponding data line of outputting drive voltage to panel based on the existing sequential of analog power and digital power via a plurality of channels, to eliminate the noise like image on the display.
A kind of described reset circuit of switching on and shutting down that is applied to of first embodiment of the invention, a display with at least one driver is used to reset, this at least one driver is exported a corresponding data line of driving voltage to a panel via a delivery channel, this reset circuit comprises: first switch, and it is to activate a reset voltage is transferred to this data line of this panel by a gating pulse; And second switch, it is to activate with this delivery channel of this driver and this data line electrical isolation of this panel by this gating pulse; Wherein, this gating pulse is to produce between the rising that start or shutdown caused of this display or decrement phase, wherein, be before the line buffer output of this driver, to finish between the rising stage that this start caused at first latch data by this display, wherein, be when the level drops of analog power is low to moderate a predetermined level, to begin between this decrement phase that this shutdown caused by this display.
A kind of described reset circuit of switching on and shutting down that is applied to of second embodiment of the invention, be used to reset and have the display of at least one driver, whenever this at least one driver is via one first output channel and one second delivery channel and export two corresponding data lines of two driving voltage to panels, this reset circuit comprises: first switch is to activate so that this first output channel is electrically connected with this second output channel by a gating pulse; Second switch is to activate with this two corresponding data line electrical isolation with this second output channel and this panel by this gating pulse; And the 3rd switch, it is to activate by this gating pulse, makes to export a reset voltage via this first output channel; Wherein, this gating pulse is to produce between the rising that start or shutdown caused of this display or decrement phase, wherein, be before the line buffer output of this driver, to finish between the rising stage that this start caused at first latch data by this display, wherein, be when the level drops of an analog power is low to moderate a predetermined level, to begin between the decrement phase that this shutdown caused by this display.
Description of drawings
Fig. 1 shows employed LCD module among LCD monitor/TV;
Fig. 2 shows the described reset circuit of the monitor switch machine that is applied to of first embodiment of the invention;
Fig. 3 shows about the gating pulse of the start/power-down sequence of display and the sequential chart of signal;
Fig. 4 shows the described reset circuit of the monitor switch machine that is applied to of second embodiment of the invention;
Fig. 5 shows the described reset circuit of the monitor switch machine that is applied to of third embodiment of the invention; And
Fig. 6 shows the described reset circuit of the monitor switch machine that is applied to of fourth embodiment of the invention.
The reference numeral explanation
1,1a, 1b, 1c driver
2 panels
3 source electrode driver unit
4 gate drivers unit
5 time schedule controllers
10 first switches
11 second switches
12,13 ", 14 ' the 3rd switches
13 line buffers
13 ', 14 the 4th switches.
Embodiment
Fig. 2 shows the described reset circuit of the monitor switch machine that is applied to of first embodiment of the invention.This display is equipped with at least one driver 1, and each driver 1 is exported the corresponding data line of a driving voltage (being equivalent to the data on the data bus) to panel via a delivery channel.Although driver 1 comprises a plurality of output channels and a plurality of corresponding data line in actual applications, for convenience of explanation, in Fig. 2, only show a delivery channel and a data line.This circuit comprises first switch 10 (being a MOS transistor in the present embodiment) and second switch 11.First switch 10 is to activate (actuate) a reset voltage VG is transferred to the data line of panel by a gating pulse CRL.Second switch 11 is to activate so that the delivery channel of driver 1 and the data line of panel are electrically insulated from each other by this gating pulse CRL, wherein, this gating pulse CRL by display switching on and shutting down caused produces during instantaneous.
Fig. 3 shows about the gating pulse CRL of the start/power-down sequence (a power on/off sequence) of display and the sequential chart of signal.Caused during by display starting instantaneous during T1 be end before line buffer (line buffer) 13 output of the self-driven device 1 of one first latch data.Caused during by the shutdown of display instantaneous during T2 begin when being reduced to a predetermined level PL at the level (for example, the variation range of this analog power VDDA is from 0V to 8.0V or 13.5V) of an analog power VDDA.The level of one gating pulse CRL is that root should change according to analog power VDDA and a digital power VDDD (variation range of this digital power VDDD is from 0V to 2.3V or 3.6V).When T1 began during instantaneous, the level of this gating pulse CRL was from time t
0To time t
1Increase to the high level of this digital power VDDD from an earth level (VSSD or digital grounding (digital ground)), and follow from time t
1To time t
3Remain on the high level of this digital power VDDD.Simultaneously, the level of this analog power VDDA is from time t
2To time t
4Increase to the high level of this analog power VDDA from this earth level (VSSA or analogue ground (analog ground)), wherein, time t
2Be ahead of time t
3At time t
3, the level of this gating pulse CRL changes along with the level of this analog power VDDA, and at time t
4Increase to the high level of this analog power VDDA, and from time t
4To time t
5Remain on the high level of this analog power VDDA.When the level drops of this analog power VDDA is low to moderate this predetermined level PL, instantaneous during T2 from time t
6Beginning.Simultaneously, the level with this predetermined level PL produces this gating pulse CRL.Then, the level of this gating pulse CRL will descend along with this analog power VDDA, until at time t
7Reach the high level of this digital power VDDD.Then, the level of this gating pulse CRL is from time t
7To time t
8Remain on the high level of this digital power VDDD.Finally, the level of this gating pulse CRL is lagging behind time t
8Time t
9Drop to this earth level VSSD.Notice that this gating pulse CRL can produce by driver 1 or by the time schedule controller (timing controller) of display.Again, reset voltage VG can be the external stability voltage that the outside provided of self-driven device 1.
Join Fig. 2 and 3 again, when display starting, instantaneous during T1 begin and produce gating pulse CRL to connect first switch 10, reset voltage VG is transferred to the data line of panel.Simultaneously, second switch 11 is to activate with the delivery channel of driver 1 and the data line electrical isolation of panel by gating pulse CRL.This gating pulse CRL is at time t
5Deenergize (disabled), and then, the line buffer 13 of the self-driven device 1 of first latch data exports level shifter to.Therefore, all outputs of driver 1 have same level (meaning promptly has the level of reset voltage VG).Therefore, the noise like image on the display is eliminated.With a similar fashion, when display shuts down, instantaneous during T2 at time t
6The beginning and produce this gating pulse CRL to connect first switch 10, reset voltage VG is transferred to the data line of panel.Simultaneously, second switch 11 is to activate with the delivery channel of driver 1 and the data line electrical isolation of panel by this gating pulse CRL.Therefore, when this gating pulse CRL T1 and T2 during instantaneous were activated to high level, all outputs of driver 1 had same level (meaning promptly has the level of reset voltage VG).Therefore, the noise like image on the display is eliminated.Reset voltage VG can be gamma electric voltage (gammavoltage) that self-driven device 1 provided and in the scope (for example, from 0V to 13.5V) of this analog power VDDA.
Fig. 4 shows the described reset circuit of the monitor switch machine that is applied to of second embodiment of the invention.This display is equipped with at least one driver 1a, each driver 1a via first and second delivery channel outputting drive voltage to the corresponding data line of panel.Although driver 1 a comprises a plurality of output channels and a plurality of corresponding data line in actual applications, in Fig. 4, only show two delivery channels and two data lines for ease of explanation.This circuit comprises first switch 10 (being a MOS transistor in the present embodiment), second switch 11 and the 3rd switch 13.First switch 10 is to activate so that first delivery channel is electrically connected with second delivery channel by a gating pulse CRL.Second switch 11 is to activate with first and second data line electrical isolation with second output channel and panel by this gating pulse CRL.The 3rd switch 12, be coupling between the output buffer OP1 of a digital/analog converter DAC1 and driver 1a, and CRL activates by this gating pulse, make a reset voltage VG export via first output channel, caused when wherein, this gating pulse CRL is switching on and shutting down by display instantaneous during produce.The class of operation of second embodiment is similar to the operation of first embodiment among Fig. 2 among Fig. 4.Anticipate promptly, the sequential chart of Fig. 3 also can be applicable to second embodiment.In addition, when stopping using (de-actuate) the 3rd switch 12 (when the output of this digital/analog converter DAC1 that anticipates is electrically connected the input of this output buffer OP1), the driving voltage on first data bus can be exported via first output channel.Therefore, when this gating pulse CRL was activated to high level during instantaneous T1 and T2, all outputs of driver 1a had same level (meaning promptly has the level of reset voltage VG).Therefore, the noise like image on the display is eliminated.
Fig. 5 shows the described reset circuit of the monitor switch machine that is applied to of third embodiment of the invention.This display is equipped with at least one driver 1b, each driver 1b via first and second delivery channel outputting drive voltage to the corresponding data line of panel.Although driver 1b comprises a plurality of output channels and a plurality of corresponding data line in actual applications,, in Fig. 5, only show two delivery channels and two data lines for ease of explanation.This circuit comprises first switch 10 (being a MOS transistor in the present embodiment), second switch 11, the 3rd switch 13 " and the 4th switch 13 '.First switch 10 is to activate so that first delivery channel is electrically connected with second delivery channel by a gating pulse CRL.Second switch 11 is to activate with first and second data line electrical isolation with second output channel and panel by this gating pulse CRL.The 3rd switch 13 " is to activate by this gating pulse CRL, makes reset voltage VG export via first output channel.The 4th switch 13 ' be to activate by this gating pulse CRL, make this reset voltage VG export via second output channel.Again, the sequential chart of Fig. 3 can be applicable to the 3rd embodiment.In addition, when inactive the 3rd switch 13 " and 13 ' time of the 4th switch, the driving voltage on first and second data bus is exported via first and second output channel respectively.Therefore, when this gating pulse CRL T1 and T2 during instantaneous were activated to high level, all outputs of driver 1c had same level.Therefore, the noise like image on the display is eliminated.Notice that in other embodiment of circuit, the 3rd switch 13 " is configured between the first latch LA11 and the second latch LA12 that is coupled in driver 1b.
Fig. 6 shows the described reset circuit of the monitor switch machine that is applied to of fourth embodiment of the invention.The configuration of the 4th embodiment is similar to the configuration of the 3rd embodiment, difference is: the 3rd switch 14 ' be coupled between the first shift register REG1 and the latch 13, and beyond the 4th switch 14 is coupled between the second shift register REG2 and the latch 13.
With regard to above embodiment, reset voltage VG can be gamma electric voltage that self-driven device provides and in the scope (for example, from 0V to 13.5V) of analog power.Again, reset voltage VG can be an external stability voltage, and gating pulse CRL can produce by the time schedule controller or the driver of display.MOS transistor (anticipating promptly first switch) is to receive this gating pulse VG at its grid.
According to above embodiment, all outputs of the driver of panel have same voltage level (anticipating promptly reset voltage) during the switching on and shutting down of display, and it is based on the existing sequential of analog power and digital power.By this, the noise like image on the panel is eliminated.
Technology contents of the present invention and technical characterstic disclose as above, yet the personage who is familiar with this technology still may be based on teaching of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to those disclosed embodiments, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by claim of the present invention.
Claims (7)
1. one kind is applied to the described reset circuit of switching on and shutting down, the display with at least one driver that is used to reset, and this at least one driver is exported a corresponding data line of driving voltage to a panel via a delivery channel, and this reset circuit comprises:
First switch, it is to activate a reset voltage is transferred to this data line of this panel by a gating pulse; And
Second switch, it is to activate with this delivery channel of this driver and this data line electrical isolation of this panel by this gating pulse;
Wherein, this gating pulse is to produce between the rising that start or shutdown caused of this display or decrement phase,
Wherein, be before the line buffer output of this driver, to finish between the rising stage that this start caused at first latch data by this display,
Wherein, be when the level drops of analog power is low to moderate a predetermined level, to begin between this decrement phase that this shutdown caused by this display.
2. reset circuit according to claim 1, wherein, this gating pulse is that the time schedule controller by this display produces.
3. reset circuit according to claim 1, wherein, this gating pulse is to produce by this driver.
4. reset circuit according to claim 1, wherein, this reset voltage is one from gamma electric voltage that this driver provided and in the variation range of an analog power.
5. reset circuit according to claim 1, wherein this reset voltage is an external stability voltage.
6. reset circuit according to claim 1, wherein this first switch is a metal oxide semiconductor transistor, this MOS transistor is to receive this gating pulse with its grid.
7. one kind is applied to the described reset circuit of switching on and shutting down, be used to reset and have the display of at least one driver, whenever this at least one driver is via one first output channel and one second delivery channel and export two corresponding data lines of two driving voltage to panels, and this reset circuit comprises:
First switch is to activate so that this first output channel is electrically connected with this second output channel by a gating pulse;
Second switch is to activate with this two corresponding data line electrical isolation with this second output channel and this panel by this gating pulse; And
The 3rd switch, it is to activate by this gating pulse, makes to export a reset voltage via this first output channel;
Wherein, this gating pulse is to produce between the rising that start or shutdown caused of this display or decrement phase,
Wherein, be before the line buffer output of this driver, to finish between the rising stage that this start caused at first latch data by this display,
Wherein, be when the level drops of an analog power is low to moderate a predetermined level, to begin between the decrement phase that this shutdown caused by this display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101542248A CN101388187B (en) | 2007-09-11 | 2007-09-11 | Reset circuit apply to computer opening/closing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101542248A CN101388187B (en) | 2007-09-11 | 2007-09-11 | Reset circuit apply to computer opening/closing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101388187A CN101388187A (en) | 2009-03-18 |
| CN101388187B true CN101388187B (en) | 2010-08-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101542248A Active CN101388187B (en) | 2007-09-11 | 2007-09-11 | Reset circuit apply to computer opening/closing |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290032A (en) * | 2010-06-18 | 2011-12-21 | 群康科技(深圳)有限公司 | Liquid crystal display |
| TWI530926B (en) * | 2011-05-03 | 2016-04-21 | 天鈺科技股份有限公司 | Source driver and display apparatus |
| CN102222486B (en) * | 2011-06-09 | 2013-06-26 | 深圳市英威腾电源有限公司 | Display control method and display equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1862641A (en) * | 2005-05-11 | 2006-11-15 | 友达光电股份有限公司 | Data driving circuit |
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- 2007-09-11 CN CN2007101542248A patent/CN101388187B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1862641A (en) * | 2005-05-11 | 2006-11-15 | 友达光电股份有限公司 | Data driving circuit |
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| CN101388187A (en) | 2009-03-18 |
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