CN111833792B

CN111833792B - Level converter

Info

Publication number: CN111833792B
Application number: CN202010297049.3A
Authority: CN
Inventors: 杨毓群
Original assignee: Sitronix Technology Corp
Current assignee: Sitronix Technology Corp
Priority date: 2019-04-15
Filing date: 2020-04-15
Publication date: 2023-08-08
Anticipated expiration: 2040-04-15
Also published as: TW202040938A; TWI779277B; CN111833792A

Abstract

The invention relates to a level converter, which comprises a conversion circuit and a plurality of switching circuits. The conversion circuit converts a voltage level of an input signal. The switching circuits are coupled between a plurality of reference voltages and the conversion circuit, and the switching circuits switch the reference voltages and provide the reference voltages to the conversion circuit.

Description

Level converter

Technical Field

The present invention relates to a level shifter, and more particularly, to a level shifter capable of reducing the number of high voltage differential resistant electronic components.

Background

The level shifter (LEVEL SHIFTER) is widely used in circuits of different fields, such as a driving circuit of a display panel, and is mainly used for shifting the voltage level of a signal, so as to provide a signal with a proper voltage level, so that the circuit can normally operate. However, in the voltage level conversion process of the level converter, the internal electronic components of the level converter need to bear a high voltage difference, such as a transistor, so that the internal electronic components of the level converter are almost high voltage difference resistant electronic components, that is, the high voltage difference resistant electronic components with large size are used for voltage level conversion, so that more instantaneous current is consumed, and because the high voltage difference resistant electronic components have large size, the layout needs to use a larger circuit area to separate related circuits of high voltage and low voltage. In addition, the high pressure difference resistant electronic component can be manufactured only by using high pressure resistant process, thereby causing the problem of high manufacturing cost

In view of the above, the present invention provides a level shifter, which can be applied to various circuits that need to shift the voltage level of the input signal, and can reduce the number of high voltage differential resistant electronic components to reduce the circuit size, thereby reducing the circuit area and the cost.

Disclosure of Invention

The present invention provides a level converter, which converts the voltage level of an input signal by using a plurality of reference voltages with different voltage levels, thereby reducing the number of high voltage difference resistant electronic components used and reducing the circuit area and the cost.

Drawings

Fig. 1: a circuit diagram of a first embodiment of the level shifter of the present invention;

fig. 2: a circuit diagram of a second embodiment of the level shifter of the present invention;

fig. 3: a circuit diagram of an embodiment of the level shifter controlling a buffer circuit according to the present invention; a kind of electronic device with high-pressure air-conditioning system

Fig. 4: which is a circuit diagram of an embodiment of the level shifter applied to a display device.

[ figure number control description ]

10. Level converter

20. Input circuit

21. Enabling circuit

22. Conversion circuit

30. First switching circuit

31. Second switching circuit

32. First switching circuit

33. Second switching circuit

40. Display panel

41. Source electrode driving circuit

42. Gate driving circuit

43. Controller for controlling a power supply

A1 to A8 source lines

B1-B6 grid line

CLK clock signal

DATA DATA

EN enable signal

G1-G6 gate signals

M11-M18 transistors

M21-M28 transistors

M31-M32 transistors

O output end

OL inverted output terminal

S input signal

S1-S8 source signals

Sub-Pixel

VDDK first reference level

VDDL first reference level

VDDM third reference level

VDDN third reference level

VSSK second reference level

VSSL second reference level

VSSM fourth reference level

VSSN fourth reference level

XEN enable signal

XO inverting output terminal

XOL inverting output terminal

XS input signal

Detailed Description

For a further understanding and appreciation of the structural features and advantages achieved by the present invention, the following description is provided with reference to the preferred embodiments and in connection with the accompanying detailed description:

certain terms are used throughout the description and claims to refer to particular components, however, it should be understood by one of ordinary skill in the art that manufacturers may refer to a component by different names, and that the description and claims do not rely on differences in names to distinguish the components, but rather on differences in the overall technology. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" as used herein includes any direct or indirect connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.

Please refer to fig. 1, which is a circuit diagram of a level shifter according to a first embodiment of the present invention. As shown, the level converter 10 includes a plurality of switching circuits 30, 31, and the switching circuits 30, 31 are coupled to a plurality of reference voltages. The reference voltages include a first reference voltage and a second reference voltage. The level shifter 10 includes a shift circuit 22, and the shift circuit 22 shifts the voltage level of an input signal S/XS. The switching circuits 30 and 31 are coupled between the reference voltages and the converting circuit 22, so that the switching circuits 30 and 31 can switch the reference voltages and provide one of the reference voltages to the converting circuit 22. Furthermore, the level shifter 10 includes an input circuit 20. The input circuit 20 receives the input signal S/XS, and the input signal XS and the input signal S are inverted signals. The level shifter 10 can shift the voltage level of the input signal S/XS received by the input circuit 20 to different voltage levels, wherein the input signal S/XS can be a voltage signal or a data signal in the embodiment because the level shifter 10 can be applied to various circuits that need to shift the voltage level of the input signal S/XS, such as a source driving circuit or a gate driving circuit for driving the display panel.

In this embodiment, the conversion circuit 22 is coupled to the input circuit 20 and coupled to the first reference voltage or the second reference voltage via the switching circuits 30 and 31, wherein the first reference voltage includes a first reference level VDDL and a second reference level VSSL, and the second reference voltage includes a third reference level VDDM and a fourth reference level VSSM. Moreover, the level difference between the first reference level VDDL and the second reference level VSSL may be equal to or close to the level difference between the third reference level VDDM and the fourth reference level VSSM. For example, the level of the first reference level VDDL is 6V and the level of the second reference level VSSL is 0V, and the level difference between the two levels is 6V, i.e. the first reference voltage may be 6V. The level of the third reference level VDDM is 15V and the level of the fourth reference level VSSM is 9V, and the level difference is 6V, i.e. the second reference voltage may be 6V, but the level of the second reference voltage is different from the level of the first reference voltage, in an embodiment of the present invention, the level of the second reference voltage is greater than the level of the first reference voltage. In addition, the first reference level VDDL, the second reference level VSSL, the third reference level VDDM, the fourth reference level VSSM, the levels of the first reference voltage and the second reference voltage are merely for illustration, and the first reference voltage and the second reference voltage may be supplied by the same or different power circuits, for example, two power circuits independent of each other, or one power circuit provides different reference levels, so the above examples are not limiting embodiments of the present invention.

Referring back to fig. 1, the first switching circuit 30 is coupled to the first reference level VDDL and the third reference level VDDM, the second switching circuit 31 is coupled to the second reference level VSSL and the fourth reference level VSSM, and the switching circuits 30 and 31 switch the first reference level VDDL, the second reference level VSSL, the third reference level VDDM and the fourth reference level VSSM, and provide the first reference level VDDL and the second reference level VSSL to the switching circuit 22, or provide the third reference level VDDM and the fourth reference level VSSM to the switching circuit 22, i.e. the switching circuits 30 and 31 provide the first reference voltage or the second reference voltage to the switching circuit 22. Therefore, during the period when the converting circuit 22 is coupled to the first reference voltage, for example, between 6V (the first reference level VDDL) and 0V (the second reference level VSSL), the converting circuit 22 converts the voltage level of the input signal S/XS to a first voltage level according to the level of the first reference voltage, i.e., the first reference level VDDL or the second reference level VSSL, for example, 6V or 0V. During the period when the converting circuit 22 is coupled to the second reference voltage, for example, 15V (the third reference level VDDM) and 9V (the fourth reference level VSSM), the converting circuit 22 converts the voltage level of the input signal S/XS from the first voltage level (6V/0V) to a second voltage level (15V/9V) according to the level of the second reference voltage, i.e., from the first reference level VDDL to the third reference level VDDM or from the second reference level VSSL to the fourth reference level VSSM. In other words, the level shifter 10 shifts the voltage level of the input signal S/XS to the first voltage level according to the first reference voltage, and shifts the voltage level of the input signal S/XS from the first voltage level to the second voltage level according to the second reference voltage. Thus, the converting circuit 22 of the level shifter 10 can output the input signal S and the input signal XS with the second voltage level at an output terminal O and an inverting output terminal XO.

In the embodiment, when the level of the input signal S is a high level (1) and the level of the input signal XS is a low level (0), the output terminal O outputs the input signal S with the second voltage level being the third reference level VDDM, and the inverting output terminal XO outputs the input signal XS with the second voltage level being the fourth reference level VSSM. When the input signal S is at the low level (0) and the input signal XS is at the high level (1), the output terminal O outputs the input signal S at the second voltage level of the fourth reference level VSSM, and the inverting output terminal XO outputs the input signal XS at the second voltage level of the third reference level VDDM.

The first switching circuit 30 and the second switching circuit 31 are coupled to the switching circuit 22, the first reference voltage and the second reference voltage, and the switching circuit 22 is coupled to the first reference voltage or the second reference voltage through the first switching circuit 30 and the second switching circuit 31. Therefore, the first switching circuit 30 and the second switching circuit 31 switch the first reference voltage coupled to the switching circuit 22, the voltage level of the input signal S/XS can be switched to the first voltage level, and the first switching circuit 30 and the second switching circuit 31 switch the second reference voltage coupled to the switching circuit 22, and the voltage level of the input signal S/XS can be switched from the first voltage level to the second voltage level. One embodiment of the first switching circuit 30 and the second switching circuit 31 may include a plurality of switches, respectively, and the on-switching circuit 22 is coupled to the path of the first reference voltage or the second reference voltage, and the off-switching circuit 22 is coupled to the path of the first reference voltage or the second reference voltage.

Furthermore, the level shifter 10 may include an enable circuit 21 that receives the enable signal EN to enable the level shifter 10 to have the function of latching the voltage level of the input signal S/XS level-shifted on the output terminal O and the inverted output terminal XO. The enable circuit 21 is coupled between the conversion circuit 22 and the input circuit 20, and controls the conversion circuit 22 to latch the levels of the output terminal O and the inverting output terminal XO. The enabling circuit 21 controls the converting circuit 22 to latch the second voltage level converted by the level at the output terminal O and the inverting output terminal XO, that is, to latch the third reference level VDDM (15V) or the fourth reference level VSSM (9V) at the output terminal O and the inverting output terminal XO, wherein each reference level may be other levels corresponding to different circuit requirements in addition to the above-mentioned values.

For example, when the first switching circuit 30 and the second switching circuit 31 switch the first reference level VDDL and the second reference level VSSL to be coupled to the switching circuit 22, that is, when the switching circuit 22 is coupled to the first reference voltage, if the enable signal EN is at the high level (1) and the input signal S is at the high level and the input signal XS is at the low level (0), a gate of the transistor M11 of the input circuit 20 is controlled by the input signal S and the transistor M11 is in the on state, a gate of the transistor M17 of the input circuit 20 is controlled by the input signal XS and the transistor M17 is in the off state, and a gate of the transistor M12 and the transistor M18 of the enable circuit 21 are both controlled by the enable signal EN and the transistors M12 and M18 are in the on state. A source of the transistors M11 and M17 is coupled to a second reference level VSSL, which may be a ground level, but is not limited to the ground level. A source of the transistors M12 and M18 is coupled to a drain of the transistors M11 and M17, respectively, and the transistors M11, M12, M17, M18 may be NMOS transistors. Thus, the level of the inverting output terminal XO coupled to a drain of the transistor M12 of the enabling circuit 21 is at the level of the second reference level VSSL. Furthermore, a gate of a transistor M16 and a gate of a transistor M15 of the converting circuit 22 are coupled to the inverting output XO, and the transistor M16 may be a PMOS transistor and the transistor M15 may be an NMOS transistor.

Therefore, when the level of the inverting output terminal XO is the level of the second reference level VSSL, the transistor M16 is in the on state, and the transistor M15 is in the off state. Thus, the first switching circuit 30 coupled to a source of the transistor M16 provides the first reference level VDDL, which rises through the output terminal O of the drain charge conversion circuit 22 of the transistor M16. In other words, the voltage level of the input signal S is converted to the level of the first reference level VDDL by the conversion circuit 22. The output terminal O may be a drain of the transistor M16, a drain of the transistor M15 and a drain of the transistor M18 are coupled to the drain of the transistor M16, a source of the transistor M15 is coupled to the second switching circuit 31, and a source of the transistor M15 is coupled to the second reference level VSSL through the second switching circuit 31. In addition, the drain of the transistor M18 is also coupled to the output terminal O. The first reference level VDDL is higher than the second reference level VSSL, the third reference level VDDM is higher than the fourth reference level VSSM, the third reference level VDDM is higher than the first reference level VDDL, and the fourth reference level VSSM is higher than the second reference level VSSL.

A gate of the transistor M14 and a gate of the transistor M13 of the converting circuit 22 are coupled to the output terminal O, and a source and a drain of the transistor M14 are respectively coupled to the first switching circuit 30 and the inverting output terminal XO, and the transistor 14 may be a PMOS transistor, and a source and a drain of the transistor M13 are respectively coupled to the second switching circuit 31 and the inverting output terminal XO, and the transistor M13 may be an NMOS transistor. Therefore, when the level of the output terminal O is the level of the first reference level VDDL, the transistor M14 is in the off state, and the transistor M13 is in the on state. Thus, the first reference level VDDL coupled to the source of the transistor M14 via the first switching circuit 30 does not charge the inverting output terminal XO of the switching circuit 22, and the transistor M13 is in the on state to keep the inverting output terminal XO at the level of the second reference level VSSL via the second switching circuit 31. The drain of the transistor M13, the drain of the transistor M14 and the drain of the transistor M12 are coupled to each other to form an inverting output XO.

Therefore, when the first switching circuit 30 and the second switching circuit 31 switch the coupling between the first reference level VDDL (6V) and the second reference level VSSL (0V) and the switching circuit 22, the voltage difference required by the four transistors M13, M14, M15, M16 of the switching circuit 22 and the transistor M18 on the right side thereof is the level difference between the first reference level VDDL and the second reference level VSSL, for example, 6V, or less than the level difference between the first reference level VDDL and the second reference level VSSL. Furthermore, the input signal S with the first voltage level is to be raised to a higher level, and before the level of the input signal S is changed to a low level, the level of the enable signal EN is changed to a low level (0), and the first switching circuit 30 and the second switching circuit 31 switch the third reference level VDDM (15V) and the fourth reference level VSSM (9V) to be coupled to the switching circuit 22, i.e. the switching circuit 22 is coupled to the second reference voltage, so that the voltage level of the input signal S at the output terminal O can be raised from the first voltage level (6V) to the second voltage level (15V), and the voltage level of the input signal XS at the inverting output terminal XO can be raised from the first voltage level (0V) to the second voltage level (9V). The voltage difference to be born by the four transistors M13, M14, M15, M16 of the switching circuit 22 is a level difference between the third reference level VDDM and the fourth reference level VSSM, for example, 6V, or less than the level difference between the third reference level VDDM and the fourth reference level VSSM. However, the transistors M12 and M18 are subjected to high voltage drop.

In other words, when the level converter 10 is to raise the voltage level of the input signal S to the second voltage level, the voltage level of the second reference voltage is higher than the voltage level of the first reference voltage, but the voltage level of the conversion circuit 22 can be kept the same, for example, 6V, for the transistors M13, M14, M15, M16 of the conversion circuit 22, or the voltage level is kept within a predetermined range, for example, a range where the middle and low voltage differential electronic components can withstand voltage, regardless of the coupling of the first reference voltage or the second reference voltage. Thus, the electronic component of the conversion circuit 22 does not need to be a high-voltage-difference-resistant electronic component, i.e. an electronic component manufactured by a high-voltage-difference-resistant process is not needed, so that the electronic component has a smaller size, the number of the high-voltage-difference-resistant electronic components is reduced, and the reduction of the circuit area and the cost is achieved. As can be seen from the embodiment of fig. 1, the level shifter 10 converts the voltage levels of the input signal S/XS by using a plurality of reference voltages, so that the level shifter 22 does not need to use the high voltage differential resistant electronic components, and thus the level shifter 10 of the present invention can greatly reduce the number of the high voltage differential resistant electronic components.

Referring to fig. 1 again, when the level of the input signal S is low (0) and the level of the input signal XS is high (1), and the level of the enable signal EN is also high (1), the transistor M11 of the input circuit 20 is in an off state, and the transistor M17 of the input circuit 20 is in an on state. The transistor M12 and the transistor M18 of the enabling circuit 21 are in a conductive state, and the level of the output terminal O of the switching circuit 22 is the level of the second reference level VSSL. Moreover, the transistor M14 is in an on state, and the transistor M13 is in an off state, so that the level of the inverting output terminal XO is the level of the first reference level VDDL, and when the switching circuits 30, 31 switch the third reference level VDDM and the fourth reference level VSSM and the level of the enable signal EN transitions to the low level (0), the inverting output terminal XO of the third reference level VDDM charges the inverting output terminal XO of the converting circuit 22, the level of the inverting output terminal XO rises from the first reference level VDDL to the level of the third reference level VDDM, and the level of the output terminal O of the converting circuit 22 rises from the second reference level VSSL to the level of the fourth reference level VSSM. In addition, in an embodiment of the present invention, when the level of the input signal S received by the input circuit 20 is changed from the high level (1) to the low level (0) and the level of the input signal XS is changed from the low level (0) to the high level (1), the discharging capability (the capability of pulling down the level) of the transistor M17 to the output terminal O is higher than the charging capability (the capability of raising the level) of the third reference level VDDM to the output terminal O through the transistor M16 because the level of the inverted output terminal XO has not yet risen to the capability of turning off the transistor M16, so that the switching of the high and low levels of the output terminal O can be facilitated by adjusting the third reference level VDDM to limit the charging capability of the third reference level VDDM to the output terminal O through the transistor M16. Similarly, when the level of the input signal S received by the input circuit 20 changes from the low level (0) to the high level (1) and the level of the input signal XS changes from the high level (1) to the low level (0), the charge capability of the third reference level VDDM to the inverting output terminal XO through the transistor M14 is limited to facilitate the switching of the high voltage level and the low voltage level of the inverting output terminal XO.

Please refer to fig. 2, which is a circuit diagram of a level shifter according to a second embodiment of the present invention. As shown in the drawing, the input circuit 20 and the enable circuit 21 of the level shifter 10 can be implemented by the NMOS transistors M11, M17, M12, M18 of fig. 1, instead of the PMOS transistors M21, M27, M22, M28, and the connection relationship is unchanged, while the transistors M13, M14, M15, M16 of fig. 1 implementing the shift circuit 22 are of the same type as the transistors M24, M23, M26, M25 of fig. 2, and the connection relationship is unchanged. The enable circuit 21 of fig. 2 is coupled to the enable signal XEN, and the enable signal XEN and the enable signal EN are opposite signals. Furthermore, the embodiment of fig. 1 is used for converting the positive voltage level, the embodiment of fig. 2 is used for converting the negative voltage level, and the converting circuit 22 of fig. 2 is coupled to the first reference voltage and the second reference voltage through the first switching circuit 32 and the second switching circuit 33. The first reference voltage and the second reference voltage of this embodiment can be negative voltages and include a first reference level VDDK, a second reference level VSSK, a third reference level VDDN, and a fourth reference level VSSN, such as 0V, -6V, and-9V, -15V, respectively. Furthermore, the sources of the transistors M21 and M27 of the input circuit 20 of the embodiment of fig. 2 are coupled to the first reference level VDDK, the output terminal of the level shifter 10 is denoted as OL, the inverted output terminal is denoted as XOL, and the levels of the output terminal OL and the inverted output terminal XOL after the level is converted by the conversion circuit 22 can be the second voltage level, i.e. the third reference level VDDN or the fourth reference level VSSN. The remaining techniques are similar to the description of fig. 1 and will not be repeated. In addition, the first reference level VDDK and the second reference level VSSK may be replaced by the first reference level VDDL and the second reference level VSSL in the first embodiment, so it can be known that the first reference level VDDK, the second reference level VSSK, the third reference level VDDN, and the fourth reference level VSSN may be designed according to the requirements of use.

Please refer to fig. 3, which is a circuit diagram illustrating an embodiment of the level shifter controlling a buffer circuit according to the present invention. As shown, the buffer circuit includes a transistor M32 and a transistor M31, wherein a source of the transistor M32 is coupled to the first switching circuit 30, a gate of the transistor M32 is coupled to the output terminal O of the level shifter 10 of the embodiment of fig. 1, a source of the transistor M31 is coupled to the second switching circuit 33, and a gate of the transistor M31 is coupled to the output terminal OL of the level shifter 10 of the embodiment of fig. 2, and a drain of the transistor M32 is coupled to a drain of the transistor M31. Furthermore, the buffer circuit shown in fig. 3 can be used as a driver for driving the gate driving circuit of the display device to output gate signals (e.g. g. 4G1, G2, G3, G4, G5, G6) to the display panel. The buffer circuit is coupled to the first reference level VDDL or the third reference level VDDM via the first switching circuit 30, and the buffer circuit is coupled to the second reference level VSSK and the fourth reference level VSSN via the second switching circuit 33. Furthermore, the first switching circuit 30 in fig. 1 and 3 is switched synchronously, so that the first switching circuit 30 in fig. 1 switches the first reference level VDDL or the third reference level VDDM to be coupled to the level converter 10 in fig. 1, so that when the level of the output terminal O of the level converter 10 in fig. 1 is the first voltage level (the first reference level VDDL) or the second voltage level (the third reference level VDDM), the first switching circuit 30 in fig. 3 is also switched, so that the source of the transistor M32 is also the first voltage level (the first reference level VDDL) or the second voltage level (the third reference level VDDM), and thus the transistor M32 does not need to bear a higher voltage difference, i.e. the transistor M32 does not need to be a high voltage difference resistant electronic component, and the size and the circuit area of the electronic component can be reduced.

As mentioned above, the second switching circuit 33 in fig. 2 and 3 is synchronously switched, so that the second switching circuit 33 in fig. 2 switches the second reference level VSSK or the fourth reference level VSSN to be coupled to the level converter 10 in fig. 2, so that when the level of the output terminal OL of the level converter 10 in fig. 2 is the first voltage level (the second reference level VSSK) or the second voltage level (the fourth reference level VSSN), the second switching circuit 33 in fig. 3 is also switched, so that the source of the transistor M31 is the first voltage level (the second reference level VSSK) or the second voltage level (the fourth reference level VSSN), and the transistor M31 does not need to bear a higher voltage difference, i.e. the transistor M31 does not need to be a high voltage difference electronic component, and the number of high voltage difference electronic components can be reduced. In addition, the switching circuits of fig. 1, fig. 2 and fig. 3 may be different independent switching circuits, i.e. the switching circuit of fig. 2 is changed to a third switching circuit and a fourth switching circuit, and the switching circuit of fig. 3 is changed to a fifth switching circuit and a sixth switching circuit, but the switching manner is the same as that of the fifth switching circuit and the sixth switching circuit, so that the electronic component does not need to bear a higher voltage difference, and only needs to bear a low voltage difference to maintain the electronic component.

Please refer to fig. 4, which is a circuit diagram of an embodiment of the level shifter applied to a display device. As shown, the display device includes a display panel 40, a source driving circuit 41, a gate driving circuit 42 and a controller 43. The display panel 40 includes a plurality of Sub-pixels, a plurality of source lines A1, A2, A3, A4, A5, A6, A7, A8, and a plurality of gate lines B1, B2, B3, B4, B5, B6. The source lines A1 to A8 and the gate lines B1 to B6 surround the Sub-pixels. The source signals S1 to S8 outputted from the source driving circuit 41 are transmitted to the Sub-pixels via the source lines A1 to A8, and the gate signals G1, G2, G3, G4, G5, G6 outputted from the gate driving circuit 42 are transmitted to the Sub-pixels via the gate lines B1 to B6. The Sub-pixels display images according to the source signals S1 to S8 under the control of the gate signals G1 to G6. Furthermore, in the embodiment, the gate driving circuit 42 may include the level converter 10 of fig. 1 and 2, however, during driving the display panel 40, the levels of the gate signals G1 to G6 are the scan levels or the disable levels to scan the gate lines B1, B2, B3, B4, B5, and B6, so that the gate driving circuit 42 may cooperate with the level converter 10 to drive the buffer to output the gate signals G1 to G6 with the scan levels or the disable levels as shown in fig. 3 when the voltage levels of the gate signals G1 to G6 are changed, the scan levels may be positive voltage levels, and the disable levels may be negative voltage levels. In other words, the level shifter 10 of the present invention can be applied to various circuits that need to shift the voltage level of the signal.

Referring back to fig. 4, the controller 43 generates a clock signal CLK and a DATA to the source driving circuit 41, wherein the DATA may be provided by the controller 43 or not provided by the controller 43, which are alternative designs. In addition, the controller 43 outputs the clock signal CLK to the gate driving circuit 42 to control the operation timings of the source driving circuit 41 and the gate driving circuit 42.

In summary, the present invention relates to a level shifter, which includes a shift circuit and a plurality of switching circuits. The conversion circuit converts a voltage level of an input signal. The switching circuits are coupled between a plurality of reference voltages and the conversion circuit, and the switching circuits switch the reference voltages and provide the reference voltages to the conversion circuit so as to convert the voltage level of the input signal.

The foregoing description of the preferred embodiments of the present invention is not intended to limit the scope of the invention, but rather to cover all equivalent variations and modifications in shape, construction, characteristics and spirit according to the scope of the present invention as defined in the appended claims.

Claims

1. A level shifter, comprising:

an input circuit for receiving an input signal;

a conversion circuit for converting the voltage level of the input signal;

an enabling circuit coupled between the input circuit and the conversion circuit for controlling the conversion circuit to latch the voltage level of the converted input signal; a kind of electronic device with high-pressure air-conditioning system

The switching circuits are coupled between a plurality of reference voltages and the conversion circuit, and are used for switching the reference voltages and providing the reference voltages to the conversion circuit;

the switching circuits comprise a first switching circuit and a second switching circuit, the reference voltages comprise a first reference voltage and a second reference voltage, the first switching circuit and the second switching circuit switch the first reference voltage to be coupled with the switching circuit, the voltage level of the input signal is converted to a first voltage level, the first switching circuit and the second switching circuit switch the second reference voltage to be coupled with the switching circuit, and the voltage level of the input signal is converted from the first voltage level to a second voltage level.

2. The level shifter of claim 1, wherein the reference voltages comprise a first reference voltage and a second reference voltage, the switching circuits provide the first reference voltage or the second reference voltage to the shift circuit, the shift circuit shifts the voltage level of the input signal to a first voltage level according to the first reference voltage, and shifts the voltage level of the input signal from the first voltage level to a second voltage level according to the second reference voltage.

3. The level shifter of claim 1, wherein the reference voltages comprise a first reference voltage and a second reference voltage, the first reference voltage comprises a first reference level and a second reference level, the second reference voltage comprises a third reference level and a fourth reference level, the switching circuits are coupled to the first reference level, the second reference level, the third reference level and the fourth reference level, and the switching circuits switch the first reference level, the second reference level, the third reference level and the fourth reference level and provide the first reference level and the second reference level to the shifter circuit or the third reference level and the fourth reference level to the shifter circuit.

4. The level shifter of claim 1, wherein the reference voltages comprise a first reference voltage and a second reference voltage, the first reference voltage comprises a first reference level and a second reference level, the second reference voltage comprises a third reference level and a fourth reference level, and the level difference between the first reference level and the second reference level is equal to the level difference between the third reference level and the fourth reference level.

5. The level shifter of claim 1, wherein the reference voltages comprise a first reference voltage and a second reference voltage, the second reference voltage having a higher voltage level than the first reference voltage, the shifter circuit being coupled to the first reference voltage or the second reference voltage via the switching circuits and maintaining a voltage across the shifter circuit within a predetermined range.