CN111787710A - Preparation method of ceramic circuit board - Google Patents
Preparation method of ceramic circuit board Download PDFInfo
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- CN111787710A CN111787710A CN202010699709.0A CN202010699709A CN111787710A CN 111787710 A CN111787710 A CN 111787710A CN 202010699709 A CN202010699709 A CN 202010699709A CN 111787710 A CN111787710 A CN 111787710A
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- 239000000919 ceramic Substances 0.000 title claims abstract description 86
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 49
- 229910000679 solder Inorganic materials 0.000 claims abstract description 44
- 239000011888 foil Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 35
- 238000005476 soldering Methods 0.000 claims abstract description 4
- 239000000945 filler Substances 0.000 claims abstract 6
- 238000000034 method Methods 0.000 claims description 35
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 26
- 239000011889 copper foil Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000007921 spray Substances 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 238000011946 reduction process Methods 0.000 claims description 4
- 238000007650 screen-printing Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 238000003486 chemical etching Methods 0.000 description 7
- 238000000608 laser ablation Methods 0.000 description 4
- 238000003701 mechanical milling Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- AHGIVYNZKJCSBA-UHFFFAOYSA-N [Ti].[Ag].[Cu] Chemical compound [Ti].[Ag].[Cu] AHGIVYNZKJCSBA-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/0405—Solder foil, tape or wire
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
技术领域technical field
本发明涉及一种陶瓷电路板的制备方法;更具体地,是涉及一种AMB陶瓷电路板的制备方法。The invention relates to a preparation method of a ceramic circuit board; more particularly, to a preparation method of an AMB ceramic circuit board.
背景技术Background technique
陶瓷电路板具有高导热、低膨胀的优点,近年来在新能源汽车、动力机车、航空航天等领域得到越来越广泛的应用。活性金属钎焊(Active Mteal Bonding,AMB)连接技术,依靠活性钎料来实现陶瓷基板与金属导电线路的冶金结合,具有结合强度高、冷热循环可靠性好等优点。Ceramic circuit boards have the advantages of high thermal conductivity and low expansion. In recent years, they have been more and more widely used in new energy vehicles, power locomotives, aerospace and other fields. Active metal brazing (AMB) connection technology relies on active solder to achieve metallurgical bonding of ceramic substrates and metal conductive lines, and has the advantages of high bonding strength and good reliability of cold and heat cycles.
AMB陶瓷电路板一般具有较厚的导电图形,图形厚度可达0.2毫米甚至1毫米以上。现有AMB陶瓷电路板的制备方法,通常是先利用AMB连接技术将整块金属箔焊接到陶瓷基板上,然后对金属箔进行化学蚀刻而得到导电图形,最后再利用不同于金属箔蚀刻的蚀刻工艺去除导电线路之间的活性钎料,而活性钎料的蚀刻工艺往往需要较长的蚀刻时间,成本高且极易对导电线路造成损伤。AMB ceramic circuit boards generally have thicker conductive patterns, and the pattern thickness can reach 0.2 mm or even more than 1 mm. The preparation method of the existing AMB ceramic circuit board is usually to first use the AMB connection technology to weld a whole piece of metal foil to the ceramic substrate, then chemically etch the metal foil to obtain a conductive pattern, and finally use an etching method different from the metal foil etching. The process removes the active solder between the conductive lines, and the etching process of the active solder often requires a long etching time, is costly, and easily damages the conductive lines.
发明内容SUMMARY OF THE INVENTION
针对现有技术的不足,本发明提供了一种陶瓷电路板的制备方法,该陶瓷电路板包括陶瓷基板和通过活性钎料焊接在陶瓷基板上的导电图形;所述制备方法包括以下步骤:In view of the deficiencies of the prior art, the present invention provides a preparation method of a ceramic circuit board, the ceramic circuit board comprises a ceramic substrate and a conductive pattern welded on the ceramic substrate by an active solder; the preparation method comprises the following steps:
S1,提供用于形成所述导电图形的金属箔,并从所述金属箔的第一主表面对非导电图形区域进行厚度减薄处理;S1, providing a metal foil for forming the conductive pattern, and performing a thickness reduction process on the non-conductive pattern area from the first main surface of the metal foil;
S2,在所述陶瓷基板上设置活性钎料;其中,所述活性钎料仅设置在所述陶瓷基板上用于连接所述导电图形的区域;S2, disposing active solder on the ceramic substrate; wherein, the active solder is only arranged on the ceramic substrate in the area for connecting the conductive patterns;
S3,以所述陶瓷基板面对所述金属箔的第一主表面,将所述导电图形放置到所述活性钎料上,并使所述导电图形通过所述活性钎料焊接到所述陶瓷基板上;S3, with the ceramic substrate facing the first main surface of the metal foil, placing the conductive pattern on the active solder, and soldering the conductive pattern to the ceramic through the active solder on the substrate;
S4,从所述金属箔的第二主表面去除步骤S1中厚度减薄后的所述非导电图形区域。S4, removing the non-conductive pattern region whose thickness is reduced in step S1 from the second main surface of the metal foil.
其中,对步骤S1和S2的顺序不作限制。The sequence of steps S1 and S2 is not limited.
优选的,所述金属箔为铜箔;所述金属箔的厚度大于等于0.1毫米小于等于2毫米。Preferably, the metal foil is copper foil; the thickness of the metal foil is greater than or equal to 0.1 mm and less than or equal to 2 mm.
优选的,所述陶瓷基板为氮化铝或者氮化硅陶瓷基板。Preferably, the ceramic substrate is an aluminum nitride or silicon nitride ceramic substrate.
优选的,所述陶瓷基板的双面均设置有导电图形。Preferably, conductive patterns are provided on both sides of the ceramic substrate.
本发明中,步骤S1可以通过机械铣切、化学蚀刻或激光烧蚀等方法对金属箔的非导电图形区域进行厚度减薄处理,步骤S4可以通过机械铣切、化学蚀刻或激光烧蚀等方法去除经步骤S1厚度减薄后的非导电图形区域。根据本发明的一种具体实施方式,步骤S1中通过第一蚀刻工艺对所述非导电图形区域进行厚度减薄处理,步骤S4中通过第二蚀刻工艺去除步骤S1中厚度减薄后的所述非导电图形区域。In the present invention, in step S1, a method such as mechanical milling, chemical etching or laser ablation can be used to reduce the thickness of the non-conductive pattern area of the metal foil, and in step S4, a method such as mechanical milling, chemical etching or laser ablation can be used. The non-conductive pattern area after the thickness reduction in step S1 is removed. According to a specific embodiment of the present invention, in step S1, a first etching process is used to perform a thickness reduction process on the non-conductive pattern region, and in step S4, a second etching process is used to remove the thickness-reduced part of the non-conductive pattern region in step S1. Non-conductive pattern area.
优选的,步骤S4中通过喷淋蚀刻工艺去除步骤S1中厚度减薄后的所述非导电图形区域。Preferably, in step S4, the non-conductive pattern region whose thickness is reduced in step S1 is removed by a spray etching process.
更优选的,步骤S4中,在蚀穿所述金属箔之后,继续对所述导电图形的侧壁进行蚀刻,以削减所述侧壁的凸出残铜。More preferably, in step S4, after the metal foil is etched through, the sidewall of the conductive pattern is continuously etched, so as to reduce the protruding copper residue on the sidewall.
根据本发明的一种具体实施方式,步骤S1中将所述非导电图形的厚度减薄30-80%。According to a specific embodiment of the present invention, in step S1, the thickness of the non-conductive pattern is reduced by 30-80%.
优选的,步骤S1中将所述非导电图形的厚度减薄40-70%。Preferably, in step S1, the thickness of the non-conductive pattern is reduced by 40-70%.
根据本发明的一种具体实施方式,步骤S2中以丝网印刷工艺在所述陶瓷基板上设置活性钎料。According to a specific embodiment of the present invention, in step S2, active solder is provided on the ceramic substrate by a screen printing process.
本发明的陶瓷电路板制备方法,通过对金属箔进行两步加工制作导电图形,且该两步加工分别在活性钎料焊接前后从金属箔的两个表面进行,使得活性钎料可仅设置在陶瓷基板上用于连接所述导电图形的区域,减少了活性钎料的使用量;无需活性钎料的化学蚀刻步骤,缩短加工时间,减少化学污染,避免了化学蚀刻活性钎料时对导电图形的损伤,提高图形精度。In the method for preparing a ceramic circuit board of the present invention, the conductive pattern is produced by performing two-step processing on the metal foil, and the two-step processing is carried out respectively from both surfaces of the metal foil before and after the active solder is welded, so that the active solder can only be arranged on the surface of the metal foil. The area used to connect the conductive patterns on the ceramic substrate reduces the amount of active solder used; the chemical etching step of active solder is not required, the processing time is shortened, chemical pollution is reduced, and the conductive pattern is avoided during chemical etching of active solder. damage and improve graphics accuracy.
为了更清楚地说明本发明的目的、技术方案和优点,下面结合附图和具体实施方式对本发明作进一步的详细说明。In order to illustrate the objectives, technical solutions and advantages of the present invention more clearly, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
附图说明Description of drawings
图1是本发明陶瓷电路板实施例1的结构示意图;1 is a schematic structural diagram of Embodiment 1 of a ceramic circuit board of the present invention;
图2是本发明陶瓷电路板实施例2的结构示意图;2 is a schematic structural diagram of Embodiment 2 of the ceramic circuit board of the present invention;
图3是本发明陶瓷电路板制备方法实施例的流程图;3 is a flow chart of an embodiment of a method for preparing a ceramic circuit board of the present invention;
图4是在金属箔的第一表面贴附抗蚀膜的结构示意图;4 is a schematic structural diagram of attaching a resist film to the first surface of the metal foil;
图5是金属箔第一表面蚀刻后的结构示意图;5 is a schematic structural diagram of the first surface of the metal foil after etching;
图6是在陶瓷基板的第一表面设置活性钎料的结构示意图;6 is a schematic structural diagram of disposing active solder on the first surface of the ceramic substrate;
图7是第一次蚀刻后的金属箔焊接到陶瓷基板第一表面的结构示意图;7 is a schematic structural diagram of the metal foil after the first etching being welded to the first surface of the ceramic substrate;
图8在金属箔的第二表面贴附抗蚀膜的结构示意图;8 is a schematic structural diagram of attaching a resist film to the second surface of the metal foil;
图9是将金属箔从其第二表面蚀穿时的结构示意图;FIG. 9 is a schematic view of the structure when the metal foil is etched through the second surface thereof;
图10是导电图形侧壁的凸出残铜被削减后的结构示意图。FIG. 10 is a schematic view of the structure of the sidewall of the conductive pattern after the protruding copper residues are cut.
具体实施方式Detailed ways
图1是本发明陶瓷电路板实施例1的结构示意图。如图1所示,该陶瓷电路板为单面线路的陶瓷电路板,包括陶瓷基板20和导电图形10,陶瓷基板20具有第一表面21,导电图形10通过活性钎料30与陶瓷基板20的第一表面21焊接连接。导电图形10包括相互之间具有间隙的一组导电线路11,例如导电线路111和导电线路112之间的间隙12。FIG. 1 is a schematic structural diagram of Embodiment 1 of the ceramic circuit board of the present invention. As shown in FIG. 1 , the ceramic circuit board is a single-sided circuit ceramic circuit board, including a
图2是本发明陶瓷电路板实施例2的结构示意图。如图2所示,实施例2的陶瓷电路板为双面线路的陶瓷电路板,包括陶瓷基板20、导电图形10和导电图形40;其中,导电图形10通过活性钎料30焊接在陶瓷基板20的第一表面21;导电图形40通过活性钎料30焊接在陶瓷基板20的第二表面22。导电图形10包括相互之间具有间隙的一组导电线路11,导电图形40包括相互之间具有间隙的一组导电线路41。FIG. 2 is a schematic structural diagram of Embodiment 2 of the ceramic circuit board of the present invention. As shown in FIG. 2 , the ceramic circuit board of Embodiment 2 is a double-sided circuit ceramic circuit board, including a
本发明的实施例中,导电图形的材质可以为铝、铜或者其合金等金属导电材料,优选为铜(包括纯铜或铜合金)。导电图形的厚度优选为0.1毫米至2毫米,更优选为0.2毫米至1.5毫米,但本发明并不以此为限。导电图形10和导电图形40可以具有相同或不同的图形设计、材质及厚度,通常情况下二者的图形设计是不同的,而材质及图形厚度则是相同的。In the embodiment of the present invention, the material of the conductive pattern may be a metal conductive material such as aluminum, copper or its alloy, preferably copper (including pure copper or copper alloy). The thickness of the conductive pattern is preferably 0.1 mm to 2 mm, more preferably 0.2 mm to 1.5 mm, but the present invention is not limited thereto. The
本发明的实施例中,陶瓷基板20优选为氮化铝或氮化硅陶瓷基板,其厚度可以根据实际需要选择,优选为0.2毫米至2毫米,例如0.25毫米、0.635毫米、1毫米或1.5毫米,但本发明并不以此为限。In the embodiment of the present invention, the
本发明的实施例中,活性钎料30可采用例如银铜钛活性钎料,但本发明并不以此为限,只要该活性钎料能够实现导电图形和陶瓷基板20之间的可靠连接即可。In the embodiment of the present invention, the
以下,结合附图3-10对本发明陶瓷电路板的制备方法实施例进行说明。Hereinafter, embodiments of the preparation method of the ceramic circuit board of the present invention will be described with reference to the accompanying drawings 3-10.
如图3所示,本发明陶瓷电路板的制备方法实施例包括从金属箔的第一表面将非导电图形区域减薄至预定厚度的步骤S1。步骤S1中,提供用于形成导电图形的金属箔,并从金属箔的第一主表面对非导电图形区域进行厚度减薄处理。As shown in FIG. 3 , an embodiment of the method for preparing a ceramic circuit board of the present invention includes the step S1 of thinning the non-conductive pattern area from the first surface of the metal foil to a predetermined thickness. In step S1, a metal foil for forming a conductive pattern is provided, and a thickness reduction process is performed on the non-conductive pattern area from the first main surface of the metal foil.
优选地,步骤S1采用化学蚀刻方法对非导电图形区域进行厚度减薄处理,在此以对用于形成导电图形10的铜箔进行蚀刻减薄为例说明。首先,如图4所示,提供用于形成导电图形10的铜箔10’,在铜箔10’的第一表面101上对应于导电图形10的区域覆盖第一抗蚀膜RF1,即第一表面101露出于抗蚀膜RF1的区域为铜箔10’的非导电图形区域。Preferably, the chemical etching method is used to reduce the thickness of the non-conductive pattern region in step S1 , and the copper foil used for forming the
然后,如图5所示,通过第一蚀刻工艺(例如喷淋蚀刻工艺)对非导电图形区域进行厚度减薄处理,将非导电图形区域的厚度减薄30-80%,优选为40-70%,例如图5所示将非导电图形区域的厚度减薄大约50%,厚度减薄后在铜箔10’的第一表面101形成间隙槽121。Then, as shown in FIG. 5, the thickness of the non-conductive pattern area is reduced by a first etching process (such as a spray etching process), and the thickness of the non-conductive pattern area is reduced by 30-80%, preferably 40-70% %, for example, as shown in FIG. 5, the thickness of the non-conductive pattern area is reduced by about 50%, and after the thickness is reduced, a
步骤S1的第一蚀刻工艺中,设图形线路的目标间距(例如导电线路111和导电线路112之间的间隙12)为L,抗蚀膜RF1的开窗间距为D1,蚀刻深度为H1,则控制L=D1+H1。In the first etching process of step S1, set the target spacing of the pattern lines (for example, the
本发明陶瓷电路板的制备方法实施例还包括在陶瓷基板上对应于导电图形的区域设置活性钎料的步骤S2。其中,可采用丝网印刷工艺在陶瓷基板上设置活性钎料,使得活性钎料仅设置在陶瓷基板上用于连接导电图形的区域。The embodiment of the method for preparing the ceramic circuit board of the present invention further includes the step S2 of disposing active solder on the area of the ceramic substrate corresponding to the conductive pattern. Wherein, the active solder can be arranged on the ceramic substrate by using a screen printing process, so that the active solder is only arranged on the area of the ceramic substrate for connecting the conductive patterns.
制备如图1所示的单面线路陶瓷电路板时,可以如图6所示,在陶瓷基板20的第一表面21上对应于导电图形10的区域丝网印刷活性钎料30。容易理解,在制备例如图2所示的双面线路陶瓷电路板时,还需要在陶瓷基板20的第二表面22上对应于导电图形40的区域丝网印刷活性钎料30;其中,陶瓷基板20两个表面的活性钎料30的丝网印刷是分别进行的。When preparing the single-sided circuit ceramic circuit board shown in FIG. 1 , as shown in FIG. 6 , the
本发明陶瓷电路板的制备方法实施例还包括将金属箔第一表面的导电图形区域焊接至陶瓷基板表面的步骤S3。即,步骤S3中以陶瓷基板面对金属箔的第一主表面,将导电图形放置到活性钎料上,并使导电图形通过活性钎料焊接到陶瓷基板上。The embodiment of the method for preparing the ceramic circuit board of the present invention further includes the step S3 of soldering the conductive pattern area on the first surface of the metal foil to the surface of the ceramic substrate. That is, in step S3, with the ceramic substrate facing the first main surface of the metal foil, the conductive pattern is placed on the active solder, and the conductive pattern is welded to the ceramic substrate through the active solder.
以导电图形10和陶瓷基板20的连接为例,如图7所示,以陶瓷基板20面对铜箔10’的第一主表面101(即铜箔10’的第二主表面102相对远离陶瓷基板20),将导电图形10放置到陶瓷基板20第一表面21的活性钎料30上,并使导电图形10通过活性钎料30焊接到陶瓷基板20上。由于导电图形的各个组成部分在步骤S3中以连接在一起的状态焊接到陶瓷基板上,因此导电图形中各个组成部分之间的相对位置可以精准的确定。Taking the connection between the
本发明陶瓷电路板的制备方法实施例还包括步骤S4:从金属箔的第二主表面去除经步骤S1厚度减薄后的非导电图形区域;优选地,步骤S4采用化学蚀刻方法去除步骤S1中厚度减薄后的非导电图形区域。The embodiment of the preparation method of the ceramic circuit board of the present invention further includes step S4: removing the non-conductive pattern area after the thickness reduction in step S1 from the second main surface of the metal foil; Non-conductive pattern area after thickness reduction.
在此,以蚀刻去除铜箔10’中经步骤S1厚度减薄后的非导电图形区域为例说明。首先,如图8所示,在铜箔10’的第二表面102上对应于导电图形10的区域覆盖第二抗蚀膜RF2,即第二表面101露出于抗蚀膜RF2的区域为铜箔10’中经步骤S1减薄后的非导电图形区域。然后,通过第二蚀刻工艺去除铜箔10’中厚度减薄后的非导电图形区域,第二蚀刻工艺同样可以为喷淋蚀刻工艺。Here, the non-conductive pattern area in the copper foil 10' whose thickness is reduced in step S1 is removed by etching as an example for description. First, as shown in FIG. 8, the area corresponding to the
优选的,步骤S4中,设图形线路的目标间距为L,抗蚀膜RF2的开窗间距为D2,蚀刻深度为H2,则控制L>D2+H2。相应地,步骤S4的喷淋蚀刻优选控制为包括两个阶段:即蚀穿铜箔10’的第一阶段和对导电图形10的侧壁进行蚀刻的第二阶段。如图9所示,在步骤S4的第一阶段,从铜箔10’的第二主表面102将铜箔10’蚀穿,使得导电图形10的各个组成部分相互分离形成间隙12,由于L>D2+H2,故在第一阶段蚀刻完成时,第二主表面102的图形线路间距小于目标间距L;并且,导电图形10的侧壁存在两次从不同面蚀刻所造成的凸出残铜122,凸出残铜122通常会对陶瓷电路板的电学性能造成不利影响。Preferably, in step S4, set the target spacing of the pattern circuit as L, the opening spacing of the resist film RF2 as D2, and the etching depth as H2, then control L>D2+H2. Correspondingly, the spray etching in step S4 is preferably controlled to include two stages: the first stage of etching through the copper foil 10' and the second stage of etching the sidewall of the
如图10所示,在步骤S4的第二阶段,即在蚀穿金属箔10’之后,继续对导电图形10的侧壁进行蚀刻,在此过程中,凸出残铜122的蚀刻速率会大于侧壁其他区域的蚀刻速率,经过一定时间的继续蚀刻后,第二主表面102的图形线路间距达到目标间距,同时凸出残铜122被蚀刻掉,使得导电图形10的侧壁近乎于垂直,图形精度更高。As shown in FIG. 10 , in the second stage of step S4 , that is, after etching through the
导电图形40的制作步骤可以参见上述导电图形10的制作,不再赘述。For the fabrication steps of the conductive pattern 40, reference may be made to the fabrication of the
上述的陶瓷电路板制备方法实施例中,金属箔分两次蚀刻,单次蚀刻量减少,与现有技术的一次蚀刻相比,菲林补偿可以减少一半,在相同蚀刻能力条件下,残铜宽度减小一半,最小图形间距减小。特别的,金属箔分两次蚀刻,且该两次蚀刻分别在活性钎料焊接前后从金属箔的两个表面进行,使得活性钎料可以仅设置在陶瓷基板上用于连接导电图形的区域,减少了活性钎料的使用量;无需活性钎料的化学蚀刻步骤,缩短加工时间,减少化学污染,避免了化学蚀刻活性钎料时对导电图形的损伤,提高图形精度。In the above-mentioned embodiment of the ceramic circuit board preparation method, the metal foil is etched in two times, and the single etching amount is reduced. Compared with the one-time etching in the prior art, the film compensation can be reduced by half. Reduced by half, the minimum pattern spacing is reduced. In particular, the metal foil is etched in two times, and the two etchings are carried out from both surfaces of the metal foil before and after the active solder is welded, so that the active solder can be arranged only on the area of the ceramic substrate for connecting the conductive patterns, The usage amount of active solder is reduced; the chemical etching step of active solder is not required, processing time is shortened, chemical pollution is reduced, damage to conductive patterns during chemical etching of active solder is avoided, and pattern accuracy is improved.
本发明的其他制备方法实施例中,步骤S1的厚度减薄处理也可采用例如机械铣切或激光烧蚀等方法,将非导电图形区域的厚度减薄30-80%,优选为40-70%;步骤S4也可采用例如机械铣切或激光烧蚀等金属材料去除方法去除步骤S1中厚度减薄后的非导电图形区域。In other preparation method embodiments of the present invention, the thickness reduction treatment in step S1 may also use methods such as mechanical milling or laser ablation to reduce the thickness of the non-conductive pattern area by 30-80%, preferably 40-70% %; Step S4 may also use a metal material removal method such as mechanical milling or laser ablation to remove the non-conductive pattern area after the thickness reduction in step S1.
虽然本发明以具体实施例揭露如上,但这些具体实施例并非用以限定本发明实施的范围。任何本领域的普通技术人员,在不脱离本发明的发明范围内,当可作些许的变化/替换,即凡是依照本发明所做的同等改变,应为本发明的保护范围所涵盖。Although the present invention is disclosed above with specific embodiments, these specific embodiments are not intended to limit the scope of implementation of the present invention. Any person of ordinary skill in the art can make some changes/replacements without departing from the scope of the present invention, that is, any equivalent changes made in accordance with the present invention should be covered by the protection scope of the present invention.
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CN114364133A (en) * | 2022-01-07 | 2022-04-15 | 井敏 | Metallized ceramic substrate and manufacturing method thereof |
CN114361301A (en) * | 2022-01-07 | 2022-04-15 | 井敏 | Method for interconnecting upper and lower conducting layers of ceramic substrate and substrate |
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CN108040435A (en) * | 2017-12-12 | 2018-05-15 | 北京科技大学 | A kind of aluminum nitride ceramic substrate circuit lithographic method |
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JPH06177507A (en) * | 1992-12-10 | 1994-06-24 | Tanaka Kikinzoku Kogyo Kk | Circuit board manufacturing method |
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