CN111739804A - Semiconductor packaging method - Google Patents

Semiconductor packaging method Download PDF

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Publication number
CN111739804A
CN111739804A CN202010519802.9A CN202010519802A CN111739804A CN 111739804 A CN111739804 A CN 111739804A CN 202010519802 A CN202010519802 A CN 202010519802A CN 111739804 A CN111739804 A CN 111739804A
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chip
layer
electrode
semiconductor packaging
packaging method
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CN202010519802.9A
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CN111739804B (en
Inventor
刘景宽
谢政吉
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support

Abstract

The application provides a semiconductor packaging method. The semiconductor packaging method comprises the following steps: attaching the electrode and at least one chip to be packaged on a carrier plate, wherein the front surface of the chip is close to the carrier plate, and the front surface of the chip is provided with a welding pad; the electrode comprises a first surface close to the carrier plate and a second surface opposite to the first surface; forming an encapsulating layer, wherein the encapsulating layer encapsulates the chip and the electrode, and the second surface of the electrode is exposed out of the encapsulating layer; stripping the carrier plate to expose the front surface of the chip and the first surface of the electrode; forming a seed layer on the front surface of the chip, wherein the seed layer covers the chip, the electrode and the exposed encapsulating layer; connecting the second surface of the electrode to a power supply, and carrying out an electroplating process to form a conductive layer on one side of the seed layer, which is far away from the chip, so as to form a conductive structure comprising the seed layer and the conductive layer; and carrying out graphical processing on the conductive structure to form a rewiring structure leading out the welding pad.

Description

Semiconductor packaging method
Technical Field
The present disclosure relates to semiconductor technologies, and in particular, to a semiconductor packaging method.
Background
The conventional semiconductor packaging technology, such as chip packaging technology, mainly includes the following processes: the front surface of the chip is bonded on the carrier plate through the adhesive tape, hot-press plastic package is carried out, the carrier plate is peeled off, then a rewiring structure is formed on the front surface of the chip, and packaging is carried out.
In the existing scheme, a rewiring structure is generally formed by an electroplating process, and when the electroplating process is performed, a seed layer is formed first and is used as a cathode to be connected with a negative electrode of a power supply. However, the seed layer is generally thin, the resistance is large, the current distribution uniformity is not good during electroplating, the current density is small, the electroplating efficiency is low, and the improvement of the packaging efficiency is not facilitated.
Disclosure of Invention
The embodiment of the application provides a semiconductor packaging method. The semiconductor packaging method comprises the following steps:
attaching an electrode and at least one chip to be packaged on a carrier plate, wherein the front surface of the chip is close to the carrier plate, and the front surface of the chip is provided with a welding pad; the electrode comprises a first surface close to the carrier plate and a second surface opposite to the first surface;
forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate, the encapsulating layer encapsulates the at least one chip to be encapsulated and the electrode, and the second surface of the electrode is exposed out of the encapsulating layer;
stripping the carrier plate to expose the front surface of the chip and the first surface of the electrode;
forming a seed layer on the front surface of the chip, wherein the seed layer covers the at least one chip to be packaged, the electrode and the exposed encapsulating layer;
connecting the second surface to a power supply, and carrying out an electroplating process to form a conductive layer on one side of the seed layer, which is far away from the chip, so as to form a conductive structure comprising the seed layer and the conductive layer;
and carrying out graphical processing on the conductive structure to form a rewiring structure leading out the welding pad.
In one embodiment, the electrodes are disposed at an edge of the carrier board, and/or the electrodes are disposed between two adjacent chips.
In one embodiment, the electrode comprises a plurality of strip-shaped electrode structures and/or a plurality of block-shaped electrode structures;
said connecting said second surface to a power source, comprising: connecting the second surface of each of the electrode structures to a power source.
In one embodiment, the forming an encapsulation layer comprises:
forming an encapsulation structure, wherein the encapsulation structure covers the carrier plate and encapsulates the at least one chip to be encapsulated and the electrode, and the distance from the surface of the encapsulation structure departing from the carrier plate to the carrier plate is greater than the distance from the second surface to the carrier plate;
and thinning one side of the encapsulation structure, which is far away from the carrier plate, to obtain the encapsulation layer so as to expose the second surface of the electrode.
In one embodiment, the distance from the second surface of the electrode to the carrier plate is greater than the distance from the side of the chip facing away from the carrier plate to the carrier plate; the side of the chip, which is far away from the carrier plate, does not expose the encapsulating layer.
In one embodiment, before the connecting the second surface to a power supply and performing an electroplating process to form a conductive layer on a side of the seed layer facing away from the chip, the semiconductor packaging method further includes:
forming a patterned light resistance layer on one side of the seed layer, which is far away from the chip;
the conducting layer is formed in the area of the seed layer which is not shielded by the photoresist layer;
after the connecting the second surface to a power supply and performing an electroplating process to form a conductive layer on a side of the seed layer facing away from the chip, the semiconductor packaging method further includes:
and removing the photoresist layer.
In one embodiment, the patterning the conductive structure includes:
and etching the area of the seed layer which is not shielded by the conductive layer, wherein the residual seed layer and the residual conductive layer are the rewiring structure.
In one embodiment, after the patterning process is performed on the conductive structure to form a rewiring structure leading out the bonding pad, the obtained structure is a semiconductor packaging structure, and the semiconductor packaging method further includes:
and cutting the semiconductor packaging structure, and removing the electrode.
In one embodiment, said connecting said second surface to a power source comprises:
a clamp is disposed on the second surface, through which the second surface is connected to a power source.
In one embodiment, before the mounting the electrodes and the at least one chip to be packaged on the carrier, the semiconductor packaging method further includes:
forming a protective layer on the front surface of the at least one chip to be packaged;
after the carrier plate is stripped, the semiconductor packaging method further comprises the following steps:
and removing the protective layer.
The embodiment of the application achieves the main technical effects that:
according to the semiconductor packaging method provided by the embodiment of the application, the electrode is arranged, the electrode is electrically connected with the seed layer, the resistance of the seed layer can be reduced due to the arrangement of the electrode, and when an electroplating process is carried out, the current can be uniformly distributed in the seed layer, the current density is high, the electroplating efficiency is favorably improved, and the semiconductor packaging efficiency is further improved; the second surface of the electrode is connected with the power supply when the electroplating process is carried out, the second surface of the electrode deviates from the front surface of the chip, the front surface of the chip cannot be influenced when the electrode is connected with the power supply, the distance between the electrode and the chip can be set to be smaller, so that more chips and electrodes can be arranged on the carrier plate, the more chips are arranged, the packaging efficiency is improved, the uniformity of current distribution on the seed layer can be further improved by arranging more electrodes, and the electroplating efficiency is further improved.
Drawings
FIG. 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;
fig. 2 is a schematic structural diagram of a first intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 3 is a schematic structural diagram of a carrier board according to an exemplary embodiment of the present application;
fig. 4 is a top view of a first intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
fig. 5 is a schematic structural diagram of a second intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 6 is a schematic structural diagram of a third intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 7 is a schematic structural diagram of a fourth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 8 is a schematic structural diagram of a fifth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 9 is a schematic structural diagram of a sixth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 10 is a schematic structural diagram of a seventh intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 11 is a schematic structural diagram of an eighth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 12 is a schematic structural diagram of a semiconductor package structure according to an exemplary embodiment of the present application.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The embodiment of the application provides a semiconductor packaging method. Referring to fig. 1, the semiconductor packaging method includes the following steps 110 to 160.
In step 110, attaching an electrode and at least one chip to be packaged to a carrier plate, wherein the front surface of the chip is close to the carrier plate, and a welding pad is arranged on the front surface of the chip; the electrode comprises a first surface close to the carrier plate and a second surface opposite to the first surface.
In step 120, an encapsulation layer is formed, the encapsulation layer covers the carrier, the encapsulation layer encapsulates the at least one chip to be packaged and the electrode, and the second surface of the electrode exposes the encapsulation layer.
In step 130, the carrier is peeled off to expose the front surface of the chip and the first surface of the electrode.
In step 140, a seed layer is formed on the front surface of the chip, and the seed layer covers the at least one chip to be packaged, the electrode, and the exposed encapsulating layer.
In step 150, the second surface is connected to a power source, and an electroplating process is performed to form a conductive layer on a side of the seed layer away from the chip, so as to form a conductive structure including the seed layer and the conductive layer.
In step 160, the conductive structure is patterned to form a rewiring structure leading out the pad.
According to the semiconductor packaging method provided by the embodiment of the application, the electrode is arranged, the electrode is electrically connected with the seed layer, the resistance of the seed layer can be reduced due to the arrangement of the electrode, when an electroplating process is carried out, the current can be uniformly distributed on the seed layer, the current density is high, the electroplating efficiency is favorably improved, and the semiconductor packaging efficiency is further improved. The second surface of the electrode is connected with the power supply when the electroplating process is carried out, the second surface of the electrode deviates from the front surface of the chip, the front surface of the chip cannot be influenced when the electrode is connected with the power supply, the distance between the electrode and the chip can be set to be smaller, therefore, more chips and electrodes can be arranged on the carrier plate, more chips are arranged to contribute to improving the packaging efficiency, the uniformity of current distribution on the seed layer can be further improved by arranging more electrodes, and the electroplating efficiency is further improved.
The semiconductor packaging method provided by the embodiment of the present application will be described in detail below.
In step 110, attaching an electrode and at least one chip to be packaged to a carrier plate, wherein the front surface of the chip is close to the carrier plate, and a welding pad is arranged on the front surface of the chip; the electrode comprises a first surface close to the carrier plate and a second surface opposite to the first surface.
A first intermediate structure as shown in fig. 2 may be obtained via step 110. In the embodiment shown in fig. 2, a plurality of chips 20 to be packaged are mounted on the carrier 10. In other embodiments, the number of the chips 20 to be packaged mounted on the carrier 10 may be one.
In one embodiment, referring to fig. 3, the carrier board 10 includes a mounting area 101 for mounting the chip 20 to be packaged, and a blank area 102 for mounting the electrode 30. The shape of the mounting area 101 is designed according to the layout of the chip 20 to be packaged on the whole carrier 10, and the shape of the mounting area 101 may include a circle, a rectangle or other shapes. The blank region 102 includes an edge region of the carrier 10 and a region between adjacent mounting regions 102. In the embodiment shown in fig. 3, the carrier board 10 includes four mounting areas 101. In other embodiments, the carrier board 10 may include more mounting areas 101.
In one embodiment, the chip 20 to be packaged may be obtained by dicing a silicon wafer. The silicon chip is provided with an active surface, and the active surface of the silicon chip is provided with a welding pad. The silicon wafer can be cut by adopting a mechanical cutting mode or a laser cutting mode. Optionally, before the silicon wafer is cut, a grinding device may be used to grind the back surface of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness.
The bonding pads of the chip 20 to be packaged are formed by conductive electrodes leading out from the internal circuit of the chip to the surface of the chip. The front surface of the chip 20 to be packaged may be provided with a plurality of pads. The bonding pad is arranged on the conductive electrode of the chip, and the conductive electrode of the chip 20 is led out.
In one embodiment, the shape of the carrier plate 10 may be circular, rectangular or other shape. The material of the carrier plate 10 may be iron-nickel alloy, or the material of the carrier plate 10 may also be stainless steel, polymer, etc.
In one embodiment, referring to fig. 4, the electrodes 30 are disposed at an edge region of the carrier board 10, and/or the electrodes 30 are disposed between two adjacent chips 20. When the plating process is performed in the subsequent step, the electrode 30 is connected to a power supply. The more the electrodes 30 are provided, the more the resistance of the seed layer formed in the subsequent step is reduced, the more the uniformity of the current distribution on the seed layer in the electroplating process performed in the subsequent step is facilitated, and the current density is facilitated to be improved, so that the electroplating efficiency is improved, the packaging efficiency is improved, and meanwhile, the thickness uniformity of the conductive layer formed by the electroplating process can be improved.
In some embodiments, the electrodes 30 are disposed at the edge of the carrier 10 and between two adjacent chips 20, so that the area of the electrodes 30 is larger, which makes the current distribution of the seed layer in the subsequent steps more uniform and the current density larger.
In one embodiment, the thickness of the electrode 30 is greater than the thickness of a subsequently formed seed layer, so that the electrode 30 can more effectively reduce the resistance of the seed layer.
In one embodiment, the electrodes 30 include a plurality of strip-shaped electrode structures and/or a plurality of block-shaped electrode structures. In step 110, an appropriate electrode structure may be selected according to the shape and area of the blank region 102. When the area of the blank area is fixed, the number of the conductive structures can be reduced by selecting the strip-shaped electrode structure, and the operation can be simplified to a certain extent; the block-shaped electrode structure is selected to facilitate uniform current flow to the seed layer.
In one embodiment, the material of the electrode 30 includes at least one of copper, nickel, titanium, and aluminum. With such an arrangement, the electrode 30 has better conductivity, which is more favorable for reducing the resistance of the seed layer and improving the current density.
In one embodiment, the chip 20 and the electrode 30 to be packaged may be attached to the carrier 10 by an adhesive layer, and the adhesive layer may be made of a material that is easy to peel off, so that the chip 20 and the electrode 30 to be packaged can be subsequently peeled off from the carrier 10, for example, the adhesive layer may be made of a thermal release material that can lose its adhesiveness by heating.
In step 120, an encapsulation layer is formed, the encapsulation layer covers the carrier, the encapsulation layer encapsulates the at least one chip to be packaged and the electrode, and the second surface of the electrode exposes the encapsulation layer.
A second intermediate structure as shown in fig. 5 may be obtained through step 120.
Referring to fig. 5, an encapsulation layer 40 is formed on the chip 20, the electrode 30 and the exposed carrier 10 for encapsulating the chip 20 and the electrode 30 to be packaged to reconstruct a flat plate structure, so that after the carrier 10 is peeled off, re-wiring and packaging can be continued on the reconstructed flat plate structure.
In one embodiment, before forming the encapsulating layer 40, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities from the chip 20, the electrode 30 and the surface of the carrier 10, so that the connection between the encapsulating layer 40 and the chip 20 to be packaged, the electrode 30 and the carrier 10 can be more intimate without delamination or cracking.
In one embodiment, the encapsulating layer 40 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding an epoxy compound.
In one embodiment, the step 120 of forming the encapsulation layer may include the steps of:
firstly, an encapsulation structure is formed, the encapsulation structure covers the carrier plate and encapsulates the at least one chip to be encapsulated and the electrode, and the distance from the surface of the encapsulation structure departing from the carrier plate to the carrier plate is greater than the distance from the second surface to the carrier plate. In this step, the thickness of the encapsulation structure is greater than the thickness of the chip 20 and the electrode 30, so that the encapsulation structure completely encapsulates the chip 20 and the electrode 30.
And then, thinning one side of the encapsulation structure, which is far away from the carrier plate, to obtain the encapsulation layer so as to expose the second surface of the electrode. In this step, the encapsulation structure may be thinned through a grinding process, so that the thickness of the encapsulation structure is reduced to be equal to the distance from the second surface of the electrode 30 to the carrier 10, thereby exposing the second surface of the electrode 30.
In one embodiment, the distance from the second surface of the electrode 30 to the carrier board 10 is greater than the distance from the side of the chip 20 facing away from the carrier board 10 to the carrier board 10; the side of the chip 20 facing away from the carrier 10 does not expose the encapsulation layer 40. Since the side of the chip 20 away from the carrier 10, that is, the back surface of the chip 20, does not expose the encapsulating layer 40, the encapsulating layer 40 can protect the back surface of the chip 20, and the back surface of the chip 20 can be prevented from being damaged due to the exposing of the encapsulating layer 40.
In one embodiment, before the step 110 of attaching the electrode and the at least one chip to be packaged on the carrier, the semiconductor packaging method further includes: and forming a protective layer on the front surface of the at least one chip to be packaged.
In the step 120 of forming the encapsulating layer 40, since the encapsulating layer 40 needs to be molded under high pressure during molding, the encapsulating material forming the encapsulating layer 40 easily penetrates between the carrier 10 and the chip 20 to be packaged. By forming a protective layer on the front surface of the chip 20 to be packaged, the protective layer can prevent the encapsulating material from penetrating into the surface of the chip 20 to be packaged, and even if the encapsulating material penetrates when the encapsulating layer 40 is formed, after the carrier plate 10 is peeled off from the chip 20, the surface of the protective layer can be directly treated by a chemical method or a grinding method without directly contacting the front surface of the chip 20 to be packaged, so that the welding pads on the front surface of the chip 20 to be packaged can be prevented from being damaged.
In step 130, the carrier is peeled off to expose the front surface of the chip and the first surface of the electrode.
A third intermediate structure as shown in fig. 6 may be obtained through step 130.
In one embodiment, the carrier plate 10 can be mechanically peeled off directly from the encapsulating layer 40, the chip 20 to be packaged and the electrodes 30. In another embodiment, the chip 20 and the electrode 30 to be packaged are bonded to the carrier 10 by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer may be heated to reduce its viscosity, so as to peel off the carrier 10. After the carrier 10 is peeled off, the front surface of each chip 20 to be packaged and the first surface of the electrode 30 are exposed.
In one embodiment, after the step 130 of peeling the carrier board when the protective layer is formed on the front surface of the at least one chip 20 to be packaged, the semiconductor packaging method further includes: and removing the protective layer. After the carrier 10 is peeled off, the passivation layer, the second surface of the electrode 30 and a portion of the surface of the encapsulating layer 40 are exposed, and after the passivation layer is removed, the front surface of each chip 20 to be packaged is exposed.
In step 140, a seed layer is formed on the front surface of the chip, and the seed layer covers the at least one chip to be packaged, the electrode, and the exposed encapsulating layer.
A fourth intermediate structure as shown in fig. 7 may be obtained via step 140.
Prior to step 140, the third intermediate structure may be flipped over with the front side of chip 20 facing upward to facilitate forming seed layer 50 on the front side of chip 20.
In one embodiment, seed layer 50 may be formed by a sputtering process.
In one embodiment, the material of seed layer 50 includes one or more of copper, nickel, molybdenum, aluminum, titanium, and the like. The resistivity of copper, nickel, molybdenum, aluminum and titanium is small, so that the seed layer 50 has good conductivity and small resistance, and is more favorable for improving the current in the subsequent electroplating process and the current density. In other embodiments, the material of the seed layer 50 may be other materials with better conductivity.
In step 150, the second surface is connected to a power source, and an electroplating process is performed to form a conductive layer on a side of the seed layer away from the chip, so as to form a conductive structure including the seed layer and the conductive layer.
In one embodiment, before the step 150 of connecting the second surface to a power source and performing an electroplating process, the semiconductor packaging method further comprises: a patterned photoresist layer 51 is formed on the side of the seed layer 50 facing away from the chip. After forming the photoresist layer 51, a fifth intermediate structure as shown in fig. 8 is obtained. The photoresist layer 51 is a patterned film layer, and the photoresist layer 51 covers the seed layer 50 except for a conductive layer to be formed subsequently. In forming the photoresist layer 51, a whole photoresist layer may be formed first, and then the photoresist layer is patterned to obtain the photoresist layer 51. The material of the photoresist layer 51 may be a positive photoresist or a negative photoresist.
Referring to fig. 9, in the electroplating process, the fifth intermediate structure is placed above the electroplating bath 54, the electrode 30 serves as a cathode, the second surface of the electrode 30 is connected to a negative electrode of a power supply 55, an anode 53 provided at the bottom of the electroplating bath 54 is connected to a positive electrode of the power supply 55, and the electroplating bath 54 contains an electrolyte. During the electroplating process, the metal atoms of the anode 53 lose electrons and become metal cations into the electrolyte, and the metal cations in the electrolyte are reduced into metal and deposited on the surface of the seed layer 50 not covered by the photoresist layer 51 to form a conductive layer.
In one embodiment, the electrolyte in the plating cell 54 may be a copper chloride solution or a copper sulfate solution, the material of the anode 53 may be copper metal, and the material of the conductive layer formed may be copper metal.
In one embodiment, when the electrode 30 comprises a plurality of electrode structures, said connecting said second surface to a power source comprises: the second surface of each electrode structure is connected to a power source.
In one embodiment, said connecting said second surface to a power source comprises: on the second surface a clamp 52 is arranged, by means of which clamp 52 the second surface is connected to a power source. The connection of the second surface of the electrode 30 to a power source is facilitated by the provision of the clamp 52.
In one embodiment, when the electrode 30 includes a strip-shaped electrode structure, a plurality of clamps 52 may be disposed on the second surface of the electrode 30. When the plurality of clamps 52 are arranged on the electrode structure, the contact area between the clamps 52 and the electrode structure is larger, so that current can uniformly flow to the electrode 30 from the clamps 52, uniform flow of the current on the whole seed layer is ensured, and the electroplating quality is improved.
A sixth intermediate structure as shown in fig. 10 may be obtained by an electroplating process. Referring to fig. 10, the conductive layer includes a plurality of conductive blocks 61, and the plurality of conductive blocks 61 are formed in the regions of the seed layer 50 not covered by the photoresist layer 51. Compared with the scheme that the photoresist layer 51 is not arranged, the whole metal layer is formed on the seed layer 50 through the electroplating process, and the conductive layer is formed through etching subsequently, the arrangement of the photoresist layer 51 is beneficial to shortening the time required by the electroplating process, and the process step of etching the metal layer can be saved.
In one embodiment, after the step 150 of connecting the second surface to a power source and performing an electroplating process, the semiconductor packaging method may further include: the photoresist layer 51 is removed. In this step, the photoresist layer may be removed by exposure and development. An eighth intermediate structure as shown in fig. 11 can be obtained by this step. Referring to fig. 11, a conductive structure 70 includes a seed layer 50 and a conductive layer 60. The shape and position of the plurality of conductive bumps 61 of the conductive layer 60 are the same as those of the rewiring structure formed in the subsequent step.
In step 160, the conductive structure is patterned to form a rewiring structure leading out the pad.
In one embodiment, the step 160 of patterning the conductive structure to form a rewiring structure leading out the pad may include the following steps:
and etching away the area of the seed layer 50 not shielded by the conductive layer 60, wherein the residual seed layer and the conductive layer are the rewiring structure 80. In this step, a wet etching process may be used to etch the regions of the seed layer not covered by the conductive layer. Through this step, a semiconductor package structure as shown in fig. 12 can be obtained. Referring to fig. 12, the re-wiring structure 80 includes the remaining seed layer 62 and the conductive bumps 61.
In one embodiment, after the step 160 of patterning the conductive structure to form a rewiring structure leading out the pad, the semiconductor packaging method further includes: and cutting the semiconductor packaging structure, and removing the electrode. In this step, the semiconductor package structure may be diced along the dotted line shown in fig. 12. And removing the conductive structure to obtain the packaged chip.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A semiconductor packaging method, comprising:
attaching an electrode and at least one chip to be packaged on a carrier plate, wherein the front surface of the chip is close to the carrier plate, and the front surface of the chip is provided with a welding pad; the electrode comprises a first surface close to the carrier plate and a second surface opposite to the first surface;
forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate, the encapsulating layer encapsulates the at least one chip to be encapsulated and the electrode, and the second surface of the electrode is exposed out of the encapsulating layer;
stripping the carrier plate to expose the front surface of the chip and the first surface of the electrode;
forming a seed layer on the front surface of the chip, wherein the seed layer covers the at least one chip to be packaged, the electrode and the exposed encapsulating layer;
connecting the second surface to a power supply, and carrying out an electroplating process to form a conductive layer on one side of the seed layer, which is far away from the chip, so as to form a conductive structure comprising the seed layer and the conductive layer;
and carrying out graphical processing on the conductive structure to form a rewiring structure leading out the welding pad.
2. The semiconductor packaging method according to claim 1, wherein the electrodes are disposed at an edge of the carrier board, and/or the electrodes are disposed between two adjacent chips.
3. The semiconductor packaging method according to claim 1, wherein the electrode comprises a plurality of strip-shaped electrode structures and/or a plurality of block-shaped electrode structures;
said connecting said second surface to a power source, comprising: connecting the second surface of each of the electrode structures to a power source.
4. The semiconductor packaging method of claim 1, wherein the forming an encapsulation layer comprises:
forming an encapsulation structure, wherein the encapsulation structure covers the carrier plate and encapsulates the at least one chip to be encapsulated and the electrode, and the distance from the surface of the encapsulation structure departing from the carrier plate to the carrier plate is greater than the distance from the second surface to the carrier plate;
and thinning one side of the encapsulation structure, which is far away from the carrier plate, to obtain the encapsulation layer so as to expose the second surface of the electrode.
5. The semiconductor packaging method according to claim 1, wherein a distance from the second surface of the electrode to the carrier board is greater than a distance from a side of the chip facing away from the carrier board to the carrier board; the side of the chip, which is far away from the carrier plate, does not expose the encapsulating layer.
6. The semiconductor packaging method according to claim 1, wherein the second surface is connected to a power supply, and an electroplating process is performed to form a conductive layer on a side of the seed layer facing away from the chip, and the semiconductor packaging method further comprises:
forming a patterned light resistance layer on one side of the seed layer, which is far away from the chip;
the conducting layer is formed in the area of the seed layer which is not shielded by the photoresist layer;
after the connecting the second surface to a power supply and performing an electroplating process to form a conductive layer on a side of the seed layer facing away from the chip, the semiconductor packaging method further includes:
and removing the photoresist layer.
7. The semiconductor packaging method according to claim 6, wherein the patterning the conductive structure comprises:
and etching the area of the seed layer which is not shielded by the conductive layer, wherein the residual seed layer and the residual conductive layer are the rewiring structure.
8. The semiconductor packaging method according to claim 1, wherein after the patterning process is performed on the conductive structure to form a rewiring structure leading out the bonding pads, the obtained structure is a semiconductor packaging structure, and the semiconductor packaging method further comprises:
and cutting the semiconductor packaging structure, and removing the electrode.
9. The semiconductor packaging method of claim 1, wherein the connecting the second surface to a power supply comprises:
a clamp is disposed on the second surface, through which the second surface is connected to a power source.
10. The semiconductor packaging method according to claim 1, wherein before the mounting the electrodes and the at least one chip to be packaged on the carrier, the semiconductor packaging method further comprises:
forming a protective layer on the front surface of the at least one chip to be packaged;
after the carrier plate is stripped, the semiconductor packaging method further comprises the following steps:
and removing the protective layer.
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CN113594052A (en) * 2021-07-29 2021-11-02 矽磐微电子(重庆)有限公司 Semiconductor packaging method

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CN110838452A (en) * 2019-03-26 2020-02-25 Pep创新私人有限公司 Packaging method, panel assembly, wafer package and chip package

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CN109494202A (en) * 2017-09-12 2019-03-19 Pep创新私人有限公司 A kind of semiconductor chip packaging method and encapsulating structure
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CN113436979A (en) * 2021-06-15 2021-09-24 矽磐微电子(重庆)有限公司 Semiconductor packaging method
CN113436979B (en) * 2021-06-15 2024-02-27 矽磐微电子(重庆)有限公司 Semiconductor packaging method
CN113594052A (en) * 2021-07-29 2021-11-02 矽磐微电子(重庆)有限公司 Semiconductor packaging method
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