CN114203558A - Semiconductor packaging method and carrier plate used for semiconductor packaging method - Google Patents

Semiconductor packaging method and carrier plate used for semiconductor packaging method Download PDF

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Publication number
CN114203558A
CN114203558A CN202010981270.0A CN202010981270A CN114203558A CN 114203558 A CN114203558 A CN 114203558A CN 202010981270 A CN202010981270 A CN 202010981270A CN 114203558 A CN114203558 A CN 114203558A
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CN
China
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sub
encapsulating layer
packaging method
semiconductor packaging
chip
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CN202010981270.0A
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Chinese (zh)
Inventor
谢雷
霍炎
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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Priority to CN202010981270.0A priority Critical patent/CN114203558A/en
Publication of CN114203558A publication Critical patent/CN114203558A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling

Abstract

The application provides a semiconductor packaging method and a carrier plate used for the semiconductor packaging method. The semiconductor packaging method comprises the following steps: providing a carrier plate, wherein the carrier plate comprises a body and a protrusion part arranged on the surface of the body, and the protrusion part divides the surface of the body into at least two sub-areas; mounting a plurality of chips to be packaged on the sub-area of the body; each subarea is attached with at least one chip; forming an encapsulating layer on the carrier plate, wherein the encapsulating layer encapsulates the plurality of chips to be encapsulated and the protruding structures, and a concave part is formed in the area of the encapsulating layer corresponding to the protruding part; stripping the carrier plate; carrying out fragment processing on the packaging structure to break the packaging structure at the concave part to obtain at least two sub-packaging structures; the packaging structure at least comprises the encapsulating layer and the plurality of chips to be packaged.

Description

Semiconductor packaging method and carrier plate used for semiconductor packaging method
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a carrier used in the semiconductor packaging method.
Background
In the process of a chip packaging process, firstly, the front side of a chip is attached to a carrier plate, hot-press plastic packaging is carried out, then the carrier plate is peeled off, then a rewiring structure is formed on the front side of the chip, and packaging is carried out to obtain a board-level structure; subsequently dividing the board-level structure into a plurality of sub-board-level structures, wherein each sub-board-level structure comprises a plurality of chips; and finally, cutting each sub-board level structure to obtain a plurality of independent chip products.
The existing scheme generally adopts laser to cut a board-level structure to obtain a plurality of sub-board-level structures, but in the laser cutting process, the laser can hurt operators, and laser cutting equipment is expensive, and the cutting cost is high. In addition, heat is generated during laser cutting, and the thermal stress caused by the heat affects the reliability of the product.
Disclosure of Invention
The embodiment of the application provides a semiconductor packaging method and a carrier plate used for the semiconductor packaging method.
According to a first aspect of embodiments herein, a semiconductor packaging method is provided. The semiconductor packaging method comprises the following steps:
providing a carrier plate, wherein the carrier plate comprises a body and a protrusion part arranged on the surface of the body, and the protrusion part divides the surface of the body into at least two sub-areas;
mounting a plurality of chips to be packaged on the sub-area of the body; each subarea is attached with at least one chip;
forming an encapsulating layer on the carrier plate, wherein the encapsulating layer encapsulates the plurality of chips to be encapsulated and the protruding structures, and a concave part is formed in the area of the encapsulating layer corresponding to the protruding part;
stripping the carrier plate;
and carrying out fragment processing on the packaging structure to break the packaging structure at the sunken part to obtain at least two sub-packaging structures, wherein the packaging structure at least comprises the encapsulating layer and the plurality of chips to be packaged.
In one embodiment, the height of the raised portion is greater than or equal to the thickness of the chip; the slicing processing of the packaging structure comprises:
and thinning one side of the encapsulating layer, which is far away from the depressed part, so that the thinned thickness of the encapsulating layer is equal to or less than the depth of the depressed part.
In an embodiment, the slicing processing on the package structure includes:
applying acting force to the packaging structure to enable the packaging structure to be broken off at the concave part;
before the applying the force to the package structure to break the package structure at the recess, the semiconductor packaging method further includes:
and fixing a clamp on the packaging structure, wherein the clamp comprises clamping plate parts which are at least partially positioned at two sides of the sunken part.
In one embodiment, the clamping plate portion comprises a body portion corresponding to the sub-packaging structures one to one, and the body portion is located at the side of the recessed portion; the body part is strip-shaped and covers the area of the packaging structure adjacent to the depressed part, or the body part covers the whole area of the packaging structure on the side part of the depressed part;
the clamping plate part further comprises extending parts which are formed by extending the body part and are positioned on the recessed parts, the extending parts are provided with protruding structures which are arranged at intervals, a gap part is formed between every two adjacent protruding structures, the protruding structures of the two adjacent extending parts are arranged in a staggered mode, and the protruding structure of one extending part is clamped into the gap part of the other extending part;
when the body part covers the whole area of the packaging structure, which is positioned on the side part of the depressed part, the body part is provided with a hollow part, and the two hollow parts positioned on the two opposite sides of the depressed part are symmetrically arranged.
In one embodiment, after the step of slicing the package structure to break the package structure at the recess to obtain at least two sub-package structures, the package structure at least includes the encapsulating layer and the plurality of chips to be packaged, the semiconductor packaging method further includes:
and removing the burr structure on the side part of the sub-packaging structure.
In one embodiment, the thickness of the packaging structure where the chip is located is greater than the thickness of the packaging structure where the recess is located;
the thickness range of the encapsulating layer in the area where the sunken part is located is 20-50 microns; and/or the presence of a gas in the gas,
the width of the protruding part is larger than half of the height of the protruding part, and/or the width of the protruding part is smaller than 5 mm.
In one embodiment, the boss is molded with the body; and/or the presence of a gas in the gas,
the shape and size of each sub-region are the same.
According to a second aspect of the embodiments of the present application, there is provided a carrier board for a semiconductor packaging method, the carrier board including a body and a protrusion disposed on a surface of the body, the protrusion dividing the surface of the body into at least two sub-regions; the sub-area is used for mounting a chip to be packaged.
In one embodiment, the width of the raised portion is greater than half the height of the raised portion, and/or the width of the raised portion is less than 5 mm.
In one embodiment, the boss is molded with the body; and/or the presence of a gas in the gas,
the shape and size of each sub-region are the same.
The embodiment of the application achieves the main technical effects that:
the carrier plate comprises a body and a protruding portion arranged on the surface of the body, and the protruding portion enables a position, corresponding to the protruding portion, of an encapsulating layer to form a concave portion, so that the thickness of a region, corresponding to the concave portion, of the packaging structure is thinner, the packaging structure is easier to break at the concave portion, the packaging structure does not need to be cut by laser, damage to operators by the laser can be avoided, and the operation safety of the packaging process is improved.
Drawings
FIG. 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;
FIG. 2 is a top view of a carrier provided by an exemplary embodiment of the present application;
FIG. 3 is a side view from one perspective of a carrier provided by an exemplary embodiment of the present application;
FIG. 4 is a side view from another perspective of a carrier provided by an exemplary embodiment of the present application;
FIG. 5 is a cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;
FIG. 6 is a cross-sectional view of a second intermediate structure provided in an exemplary embodiment of the present application;
FIG. 7 is a cross-sectional view of a third intermediate structure provided in an exemplary embodiment of the present application;
FIG. 8 is a cross-sectional view of a fourth intermediate structure provided in an exemplary embodiment of the present application;
fig. 9 is a cross-sectional view of a package structure mounted on a carrier according to an exemplary embodiment of the present application;
FIG. 10 is a cross-sectional view of a fifth intermediate structure provided in an exemplary embodiment of the present application;
FIG. 11 is a cross-sectional view of a sub-package structure provided by an exemplary embodiment of the present application;
FIG. 12 is a top view of a clip secured to a package structure as provided by an exemplary embodiment of the present application;
fig. 13 is a cross-sectional view of a clip secured to a package structure according to an exemplary embodiment of the present application.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The embodiment of the application provides a semiconductor packaging method. Referring to fig. 1, the semiconductor packaging method includes the following steps 110 to 150.
In step 110, a carrier plate is provided, where the carrier plate includes a body and a protrusion disposed on a surface of the body, and the protrusion divides the surface of the body into at least two sub-regions.
In step 120, a plurality of chips to be packaged are mounted in a sub-area of the body; each sub-area is attached with at least one chip.
In step 130, an encapsulation layer is formed on the carrier, the encapsulation layer encapsulates the plurality of chips to be packaged and the bump structures, and a concave portion is formed in a region of the encapsulation layer corresponding to the bump portion.
In step 140, the carrier is peeled off.
In step 150, the package structure is subjected to a slicing process to break the package structure at the recessed portion, so as to obtain at least two sub-package structures, wherein the package structure at least comprises the encapsulating layer and the plurality of chips to be packaged.
According to the semiconductor packaging method provided by the embodiment of the application, the carrier plate comprises the body and the protruding portion arranged on the surface of the body, the protruding portion enables the encapsulating layer to form the concave portion at the position corresponding to the protruding portion, so that the thickness of the area of the packaging structure corresponding to the concave portion is thinner, the packaging structure is easier to break at the concave portion, the packaging structure does not need to be cut by laser, the damage of the laser to an operator can be avoided, and the operation safety of the packaging process is improved.
The steps of the semiconductor packaging method provided by the embodiments of the present application will be described in detail below.
In step 110, a carrier plate is provided, where the carrier plate includes a body and a protrusion disposed on a surface of the body, and the protrusion divides the surface of the body into at least two sub-regions.
Referring to fig. 2 to 4, the carrier plate 10 includes a protrusion 11 and a body 12, and the protrusion 11 is disposed on a surface of the body 12. The surface of the body 12 may be provided with a plurality of protrusions 11, some of the protrusions 11 may extend in a first direction, and other protrusions 11 may extend in a second direction, the first direction intersecting the second direction, such that the plurality of protrusions 11 divide the surface of the body 12 into at least two sub-regions 101. In some embodiments, the first direction is perpendicular to the second direction, which may make the shape of the sub-region 101 more regular. In the illustrated embodiment, the surface of the body 12 is divided into four sub-areas 101 by the projections 11. In other embodiments, the number of sub-regions 101 of the surface of the body 12 may be different from four.
In one embodiment, the surface of the body 12 includes a plurality of sub-regions 101 having the same shape and size. The package structures are formed on the carrier 10, and the package structures are separated into a plurality of sub-package structures, where the shapes and sizes of the sub-package structures are the same as those of the corresponding sub-regions 101. By setting the shapes and sizes of the sub-regions 101 to be the same, the shapes and sizes of the obtained sub-package structures can be the same. When the sub-packaging structures are transported subsequently, the sub-packaging structures are required to be loaded into the boxes, the sub-packaging structures are identical in shape and size, the boxes with the same size can be loaded, the boxes with the corresponding size do not need to be selected according to the size of the sub-packaging structures, and the operation is simple.
In one embodiment, the sub-area 101 of the body 12 includes a mounting area 1011 and a blank area 1012. The areas of the sub-area 101 other than the mounting area 1011 are blank areas 1012. The shape of the mounting area 1011 is designed according to the layout of the chip 20 to be packaged on the surface of the body 12, and the shape of the mounting area 1011 may include a circle, a rectangle, or other shapes. The blank region 1012 includes an edge region of the sub-region 101 and a region located between adjacent mounting regions 1011. In the embodiment shown in fig. 2, each sub-area 101 includes a plurality of mounting areas 1011. In other embodiments, the body 12 may also include a mounting area 1011.
In the illustrated embodiment, the body 12 is rectangular in shape, and in other embodiments, the body 12 can be circular or have other shapes. The material of the carrier plate 10 may be iron-nickel alloy, or the material of the carrier plate 10 may also be stainless steel, polymer, etc.
In one embodiment, the body 12 is integrally formed with the boss 11. Thus, when the encapsulating layer and the chip are subsequently peeled off from the carrier 10, the bump 11 is not peeled off from the body 12 along with the encapsulating layer. In other embodiments, the protruding portion 11 may be separated from the body 12, for example, a bracket may be fixed on the surface of the body 12, and the bracket includes a plurality of protruding portions, so that the bracket does not detach from the carrier after the encapsulating layer and the chip are peeled off from the carrier.
In step 120, a plurality of chips to be packaged are mounted in a sub-area of the body; each sub-area is attached with at least one chip.
A first intermediate structure as shown in fig. 5 is obtained by step 120. Each mounting area 1011 of a sub-area may mount a chip 20 to be packaged.
In one embodiment, after the chip 20 to be packaged is mounted on the body 12, the front surface of the chip to be packaged can face the body 12. The front side of the chip to be packaged is provided with a welding pad which can lead out a circuit in the chip. The welding pad of the chip to be packaged is formed by a conductive electrode which is led out from the internal circuit of the chip to the surface of the chip. The front side of the chip to be packaged can be provided with a plurality of welding pads. In other embodiments, a process for processing the back surface of the chip is required, and after the chip 20 to be packaged is mounted on the body 12, the back surface of the chip to be packaged can face the body 12.
In one embodiment, the chip 20 to be packaged may be obtained by dicing a silicon wafer. The silicon chip is provided with an active surface, and the active surface of the silicon chip is provided with a welding pad. The silicon wafer can be cut by adopting a mechanical cutting mode or a laser cutting mode. Optionally, before the silicon wafer is cut, a grinding device may be used to grind the back surface of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness.
In one embodiment, the chip 20 to be packaged may be attached to the body 12 by an adhesive layer, and the adhesive layer may be made of a material that is easily peeled off so as to peel off the chip 20 to be packaged from the carrier 10 later, for example, the adhesive layer may be made of a thermal release material that can lose its adhesiveness by heating.
In step 130, an encapsulation layer is formed on the carrier, the encapsulation layer encapsulates the plurality of chips to be packaged and the bump structures, and a concave portion is formed in a region of the encapsulation layer corresponding to the bump portion.
A second intermediate structure as shown in fig. 6 may be obtained, via step 130.
Referring to fig. 6, an encapsulation layer 31 is formed on the chip 20 to be packaged and the exposed carrier 10, and encapsulates the chip 20 to be packaged and the bumps 11 to reconstruct a flat plate structure, so that after the carrier 10 is peeled off, re-wiring and packaging can be continued on the reconstructed flat plate structure. The encapsulating layer 31 encapsulates the protrusion 11, so that a position of the encapsulating layer 31 corresponding to the protrusion 11 forms a recess 311.
In one embodiment, before the formation of the encapsulating layer 31, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities from the surfaces of the chip 20 and the carrier 10, so that the bonding between the encapsulating layer 31 and the chip 20 to be packaged and the carrier 10 can be stronger without delamination or cracking.
In one embodiment, the encapsulating layer 31 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding an epoxy resin compound.
In step 140, the carrier is peeled off.
A third intermediate structure as shown in fig. 7 may be obtained, via step 140.
Referring to fig. 7, after the third intermediate structure 30 is peeled off from the carrier 10, the areas of the encapsulating layer 31 corresponding to the protrusions 11 form recesses 311, and the depth of the recesses 311 is the same as the height of the protrusions 11.
In one embodiment, the carrier plate 10 may be mechanically peeled off directly from the third intermediate structure 30. In another embodiment, the chip 20 to be packaged and the carrier 10 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer may be heated to reduce its viscosity, so as to peel off the carrier 10.
After the chips 20 to be packaged are attached to the body 12, when the front surfaces of the chips to be packaged face the body 12, the carrier 10 is peeled off to expose the front surfaces and the concave portions 311 of the chips 20 to be packaged. After the chips 20 to be packaged are attached to the body 12, when the back surfaces of the chips to be packaged can face the body 12, the carrier 10 is peeled off to expose the back surfaces and the concave portions 311 of the chips 20 to be packaged.
In one embodiment, after the carrier 10 is peeled off to expose the front surface of each chip 20 to be packaged and the recess 311, after step 140, the semiconductor packaging method further includes the following steps:
and forming a rewiring layer on the front surface of the chip, and leading out the welding pad on the front surface of the chip by the rewiring layer.
Through this step, a fourth intermediate structure as shown in fig. 8 can be obtained, where the fourth intermediate structure includes a carrier 10 and a package structure located on the carrier 10, and the package structure includes an encapsulating layer 31, a chip 20 to be packaged, and a redistribution layer. The rewiring layer includes a conductive structure 41 formed on the front side of the chip. The thickness of the packaging structure where the chip is located is larger than that of the packaging structure where the concave part is located;
in some embodiments, the step of forming the re-wiring layer on the front side of the chip may include the following processes:
firstly, a seed layer is formed on the front surface of the chip, and the seed layer covers the surface of the third intermediate structure.
Before forming the seed layer on the front side of the chip, the third intermediate structure may be attached to the carrier plate 51, so that the front side of the chip 20 is away from the carrier plate 10, and the carrier plate 10 supports the third intermediate structure, thereby facilitating the formation of the seed layer on the front side of the chip.
In one embodiment, the seed layer may be formed by a sputtering process.
In one embodiment, the material of the seed layer includes one or more of copper, nickel, molybdenum, aluminum, titanium, and the like. The resistivity of copper, nickel, molybdenum, aluminum and titanium is low, so that the seed layer has good conductivity and low resistance, and the current magnitude and the current density in the subsequent electroplating process are improved. In other embodiments, the material of the seed layer may also be other materials with better conductivity.
And then, forming a metal layer on one side of the seed layer, which is far away from the third intermediate structure, by adopting an electroplating process to obtain a conductive layer comprising the seed layer and the metal layer.
In one embodiment, the material of the metal layer may be the same as or different from the material of the seed layer. The metal layer may cover the seed layer, or the metal layer may be a patterned film layer.
And then, carrying out patterning treatment on the conductive layer to form a conductive structure for leading out the welding pad.
In the process of patterning the conductive layer, the conductive structure in the recess 311 is etched away, so as to smoothly perform the slicing process on the package structure.
In an embodiment, the width of the protrusions 11 on the carrier plate is larger than half the height of the protrusions 11, and/or the width of the protrusions is smaller than 5 mm. Wherein the width of the protruding part 11 refers to the dimension of the protruding part 11 in a direction perpendicular to the extension direction of the protruding part 11. By setting the width of the convex part 11 to be greater than half of the height of the convex part 11, the width of the formed concave part 311 is greater than half of the depth of the concave part 311, so that when a seed layer is formed, the seed layer can be prevented from being broken in the concave part 311, and further the seed layer is prevented from being broken in the concave part 311 to influence the formation of a metal layer; the width of the protruding part 11 is smaller than 5mm, so that the problem that the area of the surface of the body 12 is occupied by the protruding part 11 is large, and the effective utilization rate of the surface of the body 12 is low can be avoided.
In some embodiments, the thickness of the encapsulating layer 31 is greater than the height of the protrusions 11. Thus, after the encapsulating layer 31 is peeled off from the carrier 10, the recess 311 formed on the encapsulating layer 31 does not penetrate the encapsulating layer 31, thereby preventing the electroplating solution from leaking during the electroplating process.
In step 150, the package structure is subjected to a slicing process to break the package structure at the recessed portion, so as to obtain at least two sub-package structures, wherein the package structure at least comprises the encapsulating layer and the plurality of chips to be packaged.
In an embodiment, the step 150 of performing the slicing process on the package structure includes: and thinning one side of the encapsulating layer, which is far away from the depressed part, so that the thinned thickness of the encapsulating layer is equal to or less than the depth of the depressed part.
In some embodiments, referring to fig. 9, before thinning the side of the encapsulating layer away from the recess, the package structure may be attached to the carrier 52 with the conductive structure 41 close to the carrier 52. The carrier plate 52 supports the package structure for facilitating the thinning process of the package structure.
The package structure includes a plurality of sub-package structures, adjacent sub-package structures are connected together by the encapsulation layer 31 in a region corresponding to the recess 311 in the longitudinal direction. By thinning the side of the encapsulating layer 31 away from the recessed portion 311, the thickness of the package structure is thinned, and when the thinned thickness of the package structure is equal to the depth of the recessed portion 311, the portion of the encapsulating layer 31 corresponding to the recessed portion 311 in the longitudinal direction is removed, so that the adjacent sub-package structures are separated, and a fifth intermediate structure shown in fig. 10 is obtained. Then, the carrier 52 is peeled off, so as to obtain the sub-package structure 32 shown in fig. 11. The sub-package structures 32 are the same number as the sub-regions 101 of the body 12. In some embodiments, after the portions of the encapsulating layer 31 corresponding to the recesses 311 are removed, the thinning process may be continued on the encapsulating layer 31 to make the thickness of the sub-package structure 32 thinner.
In some embodiments, the encapsulation structure may be thinned by a grinding process.
In some embodiments, the thickness of the encapsulating layer 31 in the region of the recess 311 is in a range from 20 μm to 50 μm. With such an arrangement, it is avoided that the thickness of the encapsulating layer 31 in the region of the recess 311 is too large, which results in a long time spent in the thinning process, and is not beneficial to improving the semiconductor packaging efficiency, and it is also avoided that the thickness of the encapsulating layer 31 in the region of the recess 311 is too small, which results in the cracking of the encapsulating layer 31 in the recess 311 when the encapsulating layer 31 is peeled off from the carrier 10. In some embodiments, the thickness of the encapsulating layer 31 in the region corresponding to the recess 311 is 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, or the like.
In one embodiment, the height of the bump 11 is greater than or equal to the thickness of the chip 20 to be packaged. Here, the height of the protrusion 11 refers to a distance from a surface of the protrusion 11 facing away from the mounting area 1011 to the mounting area 1011, and the thickness of the chip 20 to be packaged refers to a distance from a surface of the chip 20 to be packaged facing away from the mounting area 1011 to the mounting area 1011. With such an arrangement, when the package structure is thinned, the package structure is thinned to a position where the back surface of the chip 20 is not exposed or is just exposed, and the package structure is separated from the recess 311, so that damage to the back surface of the chip 20 in the thinning process can be avoided.
In another embodiment, the step 150 of performing the slicing process on the package structure includes: and applying acting force to the packaging structure to break the packaging structure at the concave part.
The package is peeled from the carrier 52 before a force is applied to the package.
Since the thickness of the encapsulating layer 31 and the region corresponding to the recess 311 is smaller, the region corresponding to the recess 311 of the encapsulating layer 31 can be broken by applying an external force to the package structure, so that the package structure is broken at the recess 311. After the package structure is broken at the recess 311, the sub-package structure 32 shown in fig. 11 can be obtained.
In one embodiment, before the applying the force to the package structure to break the package structure at the recess, the semiconductor packaging method further includes:
and fixing a clamp on the packaging structure, wherein the clamp comprises clamping plate parts which are at least partially positioned at two sides of the sunken part. Referring to fig. 12 and 13, the clip portion 60 is located on the package structure. When a force is applied to the package structure, the clip portion 60 receives the force, so that the crack can be prevented from extending to the sub-package structure to damage the chip 20 to be packaged.
In one embodiment, the clip portion 60 includes body portions 61 corresponding to the sub-package structures one to one, and the body portions 61 are located at the side of the recess 311. In the embodiment shown in fig. 12 and 13, the body portion 61 is in a strip shape, and covers an area of the package structure adjacent to the recess 311. In other embodiments, the body portion 61 may cover the whole area of the package structure located at the side of the recess 311. When the body part 61 covers the whole area of the packaging structure at the side of the recess 311, acting force is applied to the packaging structure, the acting force is distributed on the packaging structure more uniformly, and the condition that the film layer is cracked due to the fact that the corner of the packaging structure close to the recess is stressed greatly can be avoided.
In some embodiments, the clamping plate portion 60 further includes an extending portion formed by extending the main body portion 61 and located on the recessed portion, the extending portion is provided with protruding structures arranged at intervals, a gap portion is formed between two adjacent protruding structures, the protruding structures of two adjacent extending portions are arranged in a staggered manner, and the protruding structure of one of the extending portions is snapped into the gap portion of the other extending portion. Thus, when an acting force is applied to the package structure, the acting force is concentrated at the end portions of the bump structures, and the generated cracks extend along the connecting line between the adjacent bump structures, which is more favorable for preventing the cracks from reaching the sub-package structure to damage the chip 20 to be packaged.
In some embodiments, when the main body covers the whole area of the package structure located at the side of the recessed portion, a hollow portion is disposed on the main body, and two hollow portions located at two opposite sides of the recessed portion are symmetrically disposed. Therefore, the applied acting force can be uniformly distributed in each area of the packaging structure, the weight of the clamping plate part is smaller, and the operation of operators is facilitated.
In some embodiments, the clamping plate portion 61 is located on a side of the encapsulation layer 31 facing away from the chip 20 to be packaged. Thus, the clip portion 61 does not contact the conductive structure 41 of the rewiring layer, and the conductive structure 41 is not damaged.
In some embodiments, after the package structure is broken at the recess, a burr structure is generated at the broken part; some burr structures may also be generated at the sides of the sub-package structure when thinning the package structure. The method for packaging the semiconductor comprises the following steps of carrying out slicing processing on the packaging structure to break the packaging structure at the sunken part to obtain at least two sub-packaging structures, wherein the packaging structure at least comprises the packaging layer and the plurality of chips to be packaged, and the method for packaging the semiconductor further comprises the following steps: and removing the burr structure on the side part of the sub-packaging structure.
By removing the burr structure on the side of the sub-packaging structure 32, the burr structure can be prevented from falling off and moving to the surface of the chip 20 in the transportation process, so that the reliability of the chip 20 is not affected; the operator can be prevented from being scratched by the burr structure; the burr structure can also be avoided so that the sub-package structure cannot be smoothly put into a box for storing the sub-package structure for transportation.
In some embodiments, a deburring apparatus may be employed to remove the burr structure of the sub-package structure 32. Alternatively, a sanding sheet may be used to sand the sides of sub-package 32 to remove the burr structure.
In one embodiment, the thickness of the region of the package structure corresponding to the recess 311 is in a range from 20 μm to 50 μm. With such an arrangement, it is avoided that the encapsulating layer 31 is too thick in the region corresponding to the recess 311, which may result in the package structure being unable to be smoothly broken at the recess 311, and it is also avoided that the encapsulating layer 31 is too thin in the region corresponding to the recess 311, which may result in the encapsulating layer 31 being broken at the recess 311 when the encapsulating layer is peeled off from the carrier 10.
In some embodiments, after step 150, the semiconductor packaging method further comprises: and cutting the sub-packaging structure to obtain a plurality of packaged chips.
The embodiment of the application also provides a carrier plate for the semiconductor packaging method. Referring to fig. 2 to 4, the carrier plate 10 includes a body 12 and a protrusion 11 disposed on a surface of the body 12, wherein the protrusion 11 divides the surface of the body 12 into at least two sub-regions 101. The sub-area 101 is used for mounting a chip to be packaged.
In one embodiment, the width of the boss 11 is greater than half the height of the boss 11, and/or the width of the boss 11 is less than 5 mm.
In one embodiment, the boss 11 is molded with the body 12.
In one embodiment, the shape and size of each of the sub-regions 101 are the same.
The carrier for the semiconductor packaging method provided by the embodiment of the present application and the embodiments of the semiconductor packaging method belong to the same inventive concept, and the description of the relevant details and the beneficial effects can be referred to each other, which is not repeated herein.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A semiconductor packaging method, comprising:
providing a carrier plate, wherein the carrier plate comprises a body and a protrusion part arranged on the surface of the body, and the protrusion part divides the surface of the body into at least two sub-areas;
mounting a plurality of chips to be packaged on the sub-area of the body; each subarea is attached with at least one chip;
forming an encapsulating layer on the carrier plate, wherein the encapsulating layer encapsulates the plurality of chips to be encapsulated and the protruding structures, and a concave part is formed in the area of the encapsulating layer corresponding to the protruding part;
stripping the carrier plate;
carrying out fragment processing on the packaging structure to break the packaging structure at the concave part to obtain at least two sub-packaging structures; the packaging structure at least comprises the encapsulating layer and the plurality of chips to be packaged.
2. The semiconductor packaging method according to claim 1, wherein a height of the bump is greater than or equal to a thickness of the chip; the slicing processing of the packaging structure comprises:
and thinning one side of the encapsulating layer, which is far away from the depressed part, so that the thinned thickness of the encapsulating layer is equal to or less than the depth of the depressed part.
3. The semiconductor packaging method according to claim 1, wherein the dicing process for the package structure comprises:
applying acting force to the packaging structure to enable the packaging structure to be broken off at the concave part;
before the applying the force to the package structure to break the package structure at the recess, the semiconductor packaging method further includes:
and fixing a clamp on the packaging structure, wherein the clamp comprises clamping plate parts which are at least partially positioned at two sides of the sunken part.
4. The semiconductor packaging method according to claim 3, wherein the clip portion comprises a body portion corresponding to the sub-package structures one to one, the body portion being located at a side of the recess portion; the body part is strip-shaped and covers the area of the packaging structure adjacent to the depressed part, or the body part covers the whole area of the packaging structure on the side part of the depressed part;
the clamping plate part further comprises extending parts which are formed by extending the body part and are positioned on the recessed parts, the extending parts are provided with protruding structures which are arranged at intervals, a gap part is formed between every two adjacent protruding structures, the protruding structures of the two adjacent extending parts are arranged in a staggered mode, and the protruding structure of one extending part is clamped into the gap part of the other extending part;
when the body part covers the whole area of the packaging structure, which is positioned on the side part of the depressed part, the body part is provided with a hollow part, and the two hollow parts positioned on the two opposite sides of the depressed part are symmetrically arranged.
5. The semiconductor packaging method according to claim 1, wherein the dicing process is performed on the package structures to break the package structures at the recessed portions, so as to obtain at least two package structures, and the package structures at least include the encapsulating layer and the plurality of chips to be packaged, and the semiconductor packaging method further comprises:
and removing the burr structure on the side part of the sub-packaging structure.
6. The semiconductor packaging method according to claim 1, wherein a thickness of the package structure where the chip is located is larger than a thickness of the package structure where the recess is located;
the thickness range of the encapsulating layer in the area where the sunken part is located is 20-50 microns; and/or the presence of a gas in the gas,
the width of the protruding part is larger than half of the height of the protruding part, and/or the width of the protruding part is smaller than 5 mm.
7. The semiconductor packaging method according to claim 1, wherein the bump is molded together with the body; and/or the presence of a gas in the gas,
the shape and size of each sub-region are the same.
8. The carrier plate for the semiconductor packaging method is characterized by comprising a body and a convex part arranged on the surface of the body, wherein the convex part divides the surface of the body into at least two sub-areas; the sub-area is used for mounting a chip to be packaged.
9. The carrier board for semiconductor packaging method according to claim 8, wherein the width of the bump is greater than half of the height of the bump, and/or the width of the bump is less than 5 mm.
10. The carrier board for semiconductor packaging methods of claim 8, wherein the bumps are molded with the body; and/or the presence of a gas in the gas,
the shape and size of each sub-region are the same.
CN202010981270.0A 2020-09-17 2020-09-17 Semiconductor packaging method and carrier plate used for semiconductor packaging method Pending CN114203558A (en)

Priority Applications (1)

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CN202010981270.0A CN114203558A (en) 2020-09-17 2020-09-17 Semiconductor packaging method and carrier plate used for semiconductor packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010981270.0A CN114203558A (en) 2020-09-17 2020-09-17 Semiconductor packaging method and carrier plate used for semiconductor packaging method

Publications (1)

Publication Number Publication Date
CN114203558A true CN114203558A (en) 2022-03-18

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Country Link
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