CN114171396A - Semiconductor packaging method and carrier plate used for semiconductor packaging method - Google Patents

Semiconductor packaging method and carrier plate used for semiconductor packaging method Download PDF

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Publication number
CN114171396A
CN114171396A CN202010955760.3A CN202010955760A CN114171396A CN 114171396 A CN114171396 A CN 114171396A CN 202010955760 A CN202010955760 A CN 202010955760A CN 114171396 A CN114171396 A CN 114171396A
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China
Prior art keywords
chip
auxiliary
auxiliary structure
packaged
layer
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CN202010955760.3A
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Chinese (zh)
Inventor
霍炎
谢雷
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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Priority to CN202010955760.3A priority Critical patent/CN114171396A/en
Publication of CN114171396A publication Critical patent/CN114171396A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Abstract

The application provides a semiconductor packaging method and a carrier plate used for the semiconductor packaging method. The semiconductor packaging method comprises the following steps: mounting at least one chip to be packaged on a carrier plate; the carrier plate comprises a body and an auxiliary structure arranged on the surface of the body, the surface of the body comprises a first area and a second area, at least one chip to be packaged is attached to the second area, the auxiliary structure is arranged in the first area, and the auxiliary structure and the carrier plate are integrally formed or the auxiliary structure is an integrated structure; forming an encapsulating layer on the carrier plate, wherein the encapsulating layer encapsulates the at least one chip to be encapsulated to obtain an encapsulating structure comprising the at least one chip to be encapsulated and the encapsulating layer; the auxiliary structure enables the packaging structure to form a positioning structure close to the surface of the body; when the auxiliary structure and the body are integrally formed, the carrier plate is peeled off to expose the positioning structure and the chip to be packaged; when the auxiliary structure is of an integrated structure, the body is peeled off, and the positioning structure and the chip to be packaged are exposed.

Description

Semiconductor packaging method and carrier plate used for semiconductor packaging method
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a carrier used in the semiconductor packaging method.
Background
The conventional semiconductor packaging technology, such as chip packaging technology, mainly includes the following processes: for the process of carrying out the process treatment on the front surface of the chip, firstly, the front surface of the chip is attached to a carrier plate, hot-press plastic package is carried out, the carrier plate is peeled off, then, a rewiring structure is formed on the front surface of the chip, and packaging is carried out. Exposure is required in the process of forming the rewiring layer, and the position to be exposed is required to be determined before exposure. For the process of processing the back surface of the chip, the back surface of the chip needs to be attached to the carrier board.
In the existing chip packaging technology, a plurality of target chips are mounted while a chip is mounted on a carrier plate, and the position to be exposed is positioned through the target chips. However, mounting errors exist in the process of mounting the target chips, and the target chips can generate certain offset due to the lateral impact force of the plastic packaging material in the hot-press plastic packaging process, so that the relative positions of the target chips are changed, the determined exposure position is inaccurate, and the exposure precision is reduced.
Disclosure of Invention
The embodiment of the application provides a semiconductor packaging method and a carrier plate used for the semiconductor packaging method.
According to a first aspect of embodiments of the present application, there is provided a semiconductor packaging method including:
mounting at least one chip to be packaged on a carrier plate; the carrier plate comprises a body and an auxiliary structure arranged on the surface of the body, the surface of the body comprises a first area and a second area, and the at least one chip to be packaged is attached to the second area of the body; the auxiliary structure is arranged in the first area of the body and is integrally formed with the body, or the auxiliary structure is an integrated structure;
forming an encapsulating layer on the carrier plate, wherein the encapsulating layer encapsulates the at least one chip to be encapsulated, so as to obtain an encapsulating structure comprising the at least one chip to be encapsulated and the encapsulating layer; the auxiliary structure enables the enclosing structure to form a positioning structure close to the surface of the body;
when the auxiliary structure and the body are integrally formed, the carrier plate is peeled off to expose the positioning structure and the chip to be packaged; when the auxiliary structure is of an integrated structure, the body is peeled off, and the positioning structure and the chip to be packaged are exposed.
In one embodiment, when the auxiliary structure is integrally formed with the body, the auxiliary structure includes a plurality of protruding structures formed on a surface of the body, and the positioning structure includes an encapsulating structure groove portion formed on a surface of the encapsulating structure and corresponding to each of the protruding structures; alternatively, the first and second electrodes may be,
when the auxiliary structure is integrally formed with the body, the auxiliary structure comprises a plurality of groove structures formed on the surface of the body, and the positioning structure comprises an encapsulating structure protruding part formed on the surface of the encapsulating structure and corresponding to each groove structure; alternatively, the first and second electrodes may be,
when the auxiliary structure is integrally formed with the body, the auxiliary structure comprises at least one protrusion structure and at least one groove structure formed on the surface of the body, and the positioning structure comprises an encapsulating structure groove part corresponding to the protrusion structure and formed on the surface of the encapsulating structure and an encapsulating structure protrusion part corresponding to the groove structure.
In one embodiment, when the auxiliary structure is a one-piece structure, the auxiliary structure comprises a frame body, and the frame body comprises a first surface and a second surface which are opposite;
before the mounting of the at least one chip to be packaged on the carrier, the semiconductor packaging method further includes: attaching the first surface of the frame body to the first region of the body;
the encapsulating layer also encapsulates the frame body, the encapsulating structure further comprising the frame body; the positioning structure comprises the frame body; the first surface of the frame body includes a plurality of positioning regions provided with frame body recesses.
In one embodiment, the number of the chips to be packaged is multiple, the auxiliary structure further includes multiple rod portions located in the frame body and connected to the frame body, the multiple rod portions divide an area enclosed by the frame body into multiple hollow-out areas, and the chips to be packaged are located in the hollow-out areas.
In one embodiment, the front surface of the chip is located on the same side as the positioning structure; when the auxiliary structure is an integrated structure, after the positioning structure and the chip to be packaged are exposed by peeling the body, or when the auxiliary structure and the body are integrally formed, after the positioning structure and the chip to be packaged are exposed by peeling the carrier plate, the semiconductor packaging method further includes:
forming a conductive layer on the front surface of the chip;
forming a light resistance film layer on the conducting layer, and determining the position of the light resistance film layer to be exposed according to the positioning structure;
exposing the light resistance film layer according to the position to be exposed so as to perform graphical processing on the light resistance film layer to obtain a light resistance layer;
and etching the area of the conducting layer which is not shielded by the photoresist layer to obtain a rewiring layer.
According to a second aspect of the embodiments of the present application, there is provided a carrier board for a semiconductor packaging method, the carrier board including a body and an auxiliary structure, a surface of the carrier board including a first region and a second region; the auxiliary structure is arranged in the first area, and the second area is used for mounting a chip to be packaged; the auxiliary structure and the body are integrally formed, or the auxiliary structure is of an integrated structure.
In one embodiment, when the auxiliary structure is integrally formed with the body, the auxiliary structure comprises at least one protruding structure and/or at least one groove structure formed on the surface of the body.
In one embodiment, the thickness of the raised structures is greater than or equal to 10 μm; the depth of the groove structure is greater than or equal to 10 μm.
In one embodiment, when the auxiliary structure is a one-piece structure, the auxiliary structure comprises a frame body; the frame body comprises a first surface and a second surface which are opposite, and the first surface faces the body;
the first surface of the frame body includes a plurality of positioning regions, which are provided with depressions.
In one embodiment, when the auxiliary structure is an integrated structure, the auxiliary structure further includes a plurality of rod portions located in the frame body and connected to the frame body, and the plurality of rod portions divide an area enclosed by the frame body into a plurality of hollow-out areas.
The embodiment of the application achieves the main technical effects that:
the carrier plate comprises a body and an auxiliary structure, wherein the auxiliary structure enables the encapsulation structure to form a positioning structure close to the surface of the carrier plate, and when the auxiliary structure is an integrated structure, the positioning structure is exposed after the body is peeled off; when the auxiliary structure and the body are integrally formed, the positioning structure is exposed after the carrier plate is stripped; subsequently, when a rewiring layer is formed, determining a position to be exposed according to the positioning structure; when auxiliary structure and body integrated into one piece, the location structure that the in-process that forms the encapsulated layer formed can not take place the skew for the body, and when auxiliary structure formula structure as an organic whole, the relative position of the different regions of the location structure that the in-process that forms the encapsulated layer formed can not change, and then the exposure position's that determines according to location structure precision is higher, helps promoting the exposure precision.
Drawings
FIG. 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;
FIG. 2 is a top view of a carrier provided by an exemplary embodiment of the present application;
FIG. 3 is a cross-sectional view of a carrier provided in an exemplary embodiment of the present application;
fig. 4 is a cross-sectional view of a first intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;
FIG. 5 is a cross-sectional view of a carrier provided in another exemplary embodiment of the present application;
fig. 6 is a cross-sectional view of a first intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;
FIG. 7 is a top view of a carrier provided in accordance with yet another exemplary embodiment of the present application;
FIG. 8 is a cross-sectional view of the carrier shown in FIG. 7;
fig. 9 is a top view of a first intermediate structure of a semiconductor package structure provided by yet another exemplary embodiment of the present application;
FIG. 10 is a cross-sectional view of the first intermediate structure shown in FIG. 9;
fig. 11 is a cross-sectional view of a second intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 12 is a cross-sectional view of a second intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;
fig. 13 is a cross-sectional view of a second intermediate structure of a semiconductor package structure provided in accordance with yet another exemplary embodiment of the present application;
fig. 14 is a cross-sectional view of a third intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 15 is a cross-sectional view of a third intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;
fig. 16 is a cross-sectional view of a third intermediate structure of a semiconductor package structure provided in accordance with yet another exemplary embodiment of the present application;
fig. 17 is a flow chart of a semiconductor packaging method provided by another exemplary embodiment of the present application;
fig. 18 is a cross-sectional view of a fourth intermediate structure of the semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 19 is a cross-sectional view of a fourth intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;
fig. 20 is a cross-sectional view of a fourth intermediate structure of a semiconductor package structure provided in accordance with yet another exemplary embodiment of the present application.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The embodiment of the application provides a semiconductor packaging method. Referring to fig. 1, the semiconductor packaging method includes the following steps 110 to 130.
In step 110, at least one chip to be packaged is mounted on a carrier; the carrier plate comprises a body and an auxiliary structure arranged on the surface of the body, the surface of the body comprises a first area and a second area, at least one chip to be packaged is attached to the second area of the body, the auxiliary structure is arranged on the first area of the body, and the auxiliary structure and the body are integrally formed or the auxiliary structure is of an integrated structure.
In step 120, an encapsulation layer is formed on the carrier, and the encapsulation layer encapsulates the at least one chip to be packaged, so as to obtain an encapsulation structure including the at least one chip to be packaged and the encapsulation layer; the auxiliary structure enables the enclosing structure to form a positioning structure close to the surface of the body.
In step 130, when the auxiliary structure and the body are integrally formed, the carrier plate is peeled off to expose the positioning structure and the chip to be packaged; when the auxiliary structure is of an integrated structure, the body is peeled off, and the positioning structure and the chip to be packaged are exposed.
According to the semiconductor packaging method provided by the embodiment of the application, the carrier plate comprises a body and an auxiliary structure, the auxiliary structure enables the packaging structure to be close to the surface of the carrier plate to form a positioning structure, and when the auxiliary structure is an integrated structure, after the body is stripped, a chip is exposed towards one surface of the body and the positioning structure; when the auxiliary structure and the body are integrally formed, one surface of the chip facing the body and the positioning structure are exposed after the carrier plate is stripped; subsequently, when a rewiring layer is formed, determining a position to be exposed according to the positioning structure; when auxiliary structure and body integrated into one piece, the location structure that the in-process that forms the encapsulated layer formed can not take place the skew for the body, and when auxiliary structure formula structure as an organic whole, the relative position of the different regions of the location structure that the in-process that forms the encapsulated layer formed can not change, and then the exposure position's that determines according to location structure precision is higher, helps promoting the exposure precision.
The steps of the semiconductor packaging method provided by the embodiments of the present application will be described in detail below.
In step 110, at least one chip to be packaged is mounted on a carrier; the carrier plate comprises a body and an auxiliary structure arranged on the surface of the body, the surface of the body comprises a first area and a second area, at least one chip to be packaged is attached to the second area of the body, the auxiliary structure is arranged in the first area of the body, and the auxiliary structure and the body plate are integrally formed or the auxiliary structure is of an integrated structure.
In one embodiment, referring to fig. 2, the carrier 10 includes a body 12 and an auxiliary structure 11, the body 12 includes a first area 101 and a second area 102 for mounting a chip to be packaged, and the auxiliary structure is disposed in the first area 101. The regions of the surface of the body 12 other than the second region 102 may be all the first regions 101. The shape of the second region 102 is designed according to the layout of the chip to be packaged on the whole carrier 10, and the shape of the second region 102 may include a circle, a rectangle, or other shapes. The first region 101 includes an edge region of the body 12 and a region between adjacent second regions 102.
In one embodiment, after the chip 20 to be packaged is mounted on the body 12, the front surface of the chip to be packaged can face the body 12. The front side of the chip to be packaged is provided with a welding pad which can lead out a circuit in the chip. In one embodiment, the cutting method can be used for cutting a silicon wafer. The silicon chip is provided with an active surface, and the active surface of the silicon chip is provided with a welding pad. The silicon wafer can be cut by adopting a mechanical cutting mode or a laser cutting mode. Optionally, before the silicon wafer is cut, a grinding device may be used to grind the back surface of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness.
The welding pad of the chip to be packaged is formed by a conductive electrode which is led out from the internal circuit of the chip to the surface of the chip. The front side of the chip to be packaged can be provided with a plurality of welding pads. The welding pad is arranged on the conductive electrode of the chip and leads out the conductive electrode of the chip.
In one embodiment, the shape of the body 12 may be circular, rectangular, or other shape. The material of the carrier plate 10 may be iron-nickel alloy, or the material of the body 12 may also be stainless steel, polymer, etc.
In one embodiment, the chip 20 to be packaged may be attached to the body 12 by an adhesive layer, and the adhesive layer may be made of a material that is easily peeled off so as to later peel the chip 20 to be packaged from the body 12, for example, the adhesive layer may be made of a thermal release material that can be heated to lose its adhesiveness.
In one embodiment, referring to fig. 3, the auxiliary structure 11 includes a plurality of protruding structures 111 formed on the surface of the body 12, and the first intermediate structure shown in fig. 4 is obtained through step 110. The protrusion 111 may be formed by protruding from the surface of the body 12 and integrally formed with the body 12.
In another embodiment, referring to fig. 5, the auxiliary structure 11 includes a plurality of recessed portions 112 formed on the surface of the body 12, resulting in the first intermediate structure shown in fig. 6, via step 110. The recessed portion 112 may be formed by a depression in the surface of the body 12, and may be integrally formed with the body 12.
In yet another embodiment, referring to fig. 7 and 8, the auxiliary structure 11 includes a frame body 113. The semiconductor packaging method further includes: and attaching the frame body to the first area of the body. In some embodiments, the frame 113 may be attached to the first region 101 of the body 12, and then at least one chip 20 to be packaged may be attached to the second region 102 of the body 12. The structure shown in fig. 7 and 8 can be obtained by attaching the frame body to the first region of the body 12. In other embodiments, the chip 20 to be packaged may be attached to the second region 102 of the body 12, and then the auxiliary structure 11 may be attached to the first region 101 of the body 12. Alternatively, the chip 20 to be packaged and the auxiliary structure 11 may be attached to the main body 12 at the same time.
The frame body 113 may be disposed at an edge region of the body 12, and the disposition of the frame body 113 does not affect the mounting of the chip 20 to be packaged. The first intermediate structure shown in fig. 9 and 10 can be obtained through step 110, and the chip 20 to be packaged is located in the area enclosed by the frame body 113.
In some embodiments, the frame body 113 may be attached to the body 12 by an adhesive layer, and the adhesive layer may be made of a material that is easily peeled off so that the frame body 113 is later peeled off from the body 12, for example, the adhesive layer may be made of a thermal release material that can be made to lose its adhesiveness by heating.
In the embodiment shown in fig. 4, 6 and 10, a plurality of chips 20 to be packaged are mounted on the body 12. In other embodiments, the number of chips 20 to be packaged mounted on the body 12 may be one.
In step 120, an encapsulation layer is formed on the carrier, and the encapsulation layer encapsulates the at least one chip to be packaged, so as to obtain an encapsulation structure including the at least one chip to be packaged and the encapsulation layer; the auxiliary structure enables the enclosing structure to form a positioning structure close to the surface of the body.
A second intermediate structure as shown in fig. 11, 12 or 13 may be obtained through step 120. An exposure process is required in the subsequent process of forming the rewiring layer, and the positioning structure is used for determining the position to be exposed before the exposure process is carried out. Specifically, before the exposure process is carried out, an image can be shot through the camera device, the controller can identify the positioning structure in the image and determine the position information of the positioning structure, and the position to be exposed is determined according to the position of the positioning structure and the relative position relation of the position to be exposed.
In some embodiments, the number of positioning structures is plural, and plural refers to two or more. In some embodiments, the number of the positioning structures is at least three, and the at least three positioning structures are arranged at intervals on the surface of the encapsulating structure. The distance between the position to be exposed and each positioning structure is a corresponding design distance, when the number of the positioning structures is three or more, the distance between the positioning structures and the position to be exposed is a corresponding set distance, and the position to be exposed is unique, so that the determined position to be exposed is more accurate. In the illustrated embodiment, the body 12 is substantially rectangular, the number of the positioning structures is four, and the four positioning structures are respectively located at four corners of the body 12. In other embodiments, the number of locating features may be three, five, six, etc.
In one embodiment, the step 120 of forming the encapsulation layer may include the steps of:
firstly, an encapsulating material layer is formed, the encapsulating material layer covers the carrier plate and coats the at least one chip to be packaged, and the distance from the surface of the encapsulating material layer, which is far away from the body 12, to the body 12 is greater than a preset distance. In this step, the thickness of the encapsulating material layer is greater than that of the chip 20 to be packaged, so that the encapsulating material layer completely encapsulates the chip 20 to be packaged, and the back surface of the chip 20 to be packaged does not expose the encapsulating material layer.
And then, thinning the side of the encapsulating material layer, which is far away from the carrier plate, to obtain the encapsulating layer, wherein the distance from the surface of the encapsulating layer, which is far away from the body 12, to the body 12 is equal to a preset distance. In this step, the encapsulating material layer may be thinned by a grinding process. When the distance from the surface of the encapsulating layer departing from the body 12 to the body 12 is equal to the preset distance, the surface of the chip to be packaged departing from the body 12 may or may not be exposed.
Referring to fig. 11, 12 or 13, an encapsulating layer 31 covers the body 12, encapsulates the chip 20 and the exposed surface of the body 12, and is used to encapsulate the chip 20 to be encapsulated to reconstruct a flat plate structure, i.e. the encapsulating structure 30 is flush with the surface of the body 12, so that after the carrier 10 is peeled off, the re-wiring and encapsulation can be continued on the reconstructed flat plate structure.
In one embodiment, before the formation of the encapsulating layer 31, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities from the surfaces of the chip 20 and the carrier 10, so that the connection between the encapsulating layer 31 and the surfaces of the chip 20 and the carrier 10 to be packaged is more intimate and no delamination or cracking occurs.
In one embodiment, the encapsulating layer 31 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding an epoxy resin compound.
In one embodiment, referring to fig. 11, the auxiliary structure 11 includes a plurality of protruding structures 111 formed on the surface of the body 12, and the positioning structure 21 includes an encapsulating structure recess portion 211 formed on the surface of the encapsulating structure 30 corresponding to each of the protruding structures 111. When the encapsulating layer 31 is formed, the encapsulating layer 31 encapsulates each chip 20 to be encapsulated and the bump structure 111, so that the encapsulating layer 31 forms an encapsulating structure recess portion 211 at a position corresponding to the bump structure 111.
In some embodiments, the thickness of the raised structures 111 is greater than or equal to 10 μm. The depth range of the encapsulation structure recess portion 211 is formed to be the same as the thickness range of the projection structure 111, that is, the depth of the encapsulation structure recess portion 211 is greater than or equal to 10 μm. Therefore, the depth of the packaging structure groove portion 211 can be prevented from being too small, so that the light-dark contrast of the packaging structure groove portion 211 and other regions in an image shot by the camera device is low, and the packaging structure groove portion 211 is not easy to identify.
Further, the thickness of the protruding structure 111 is less than or equal to 20 μm. This prevents the encapsulation structure recess 211 from being too deep, which may cause the encapsulation structure recess 211 to penetrate the encapsulation structure 30, and the electrolyte may leak through the encapsulation structure recess 211 when the redistribution layer is formed by the electroplating process. The thickness of the raised structure 111 may be, for example, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, or the like. In the embodiment shown in fig. 2, the cross section of the protruding structure 111 is only illustrated as a circle, and in other embodiments, the cross section of the protruding structure 111 may also be rectangular, circular, or the like.
In another embodiment, referring to fig. 12, the auxiliary structure 11 includes a plurality of groove structures 112 formed on the surface of the body 12, and the positioning structure 21 includes an encapsulating structure protrusion 212 formed on the surface of the encapsulating structure 30 corresponding to each of the groove structures 112. When the encapsulating layer 31 is formed, the encapsulating layer 31 encapsulates each chip 20 to be encapsulated and fills the groove structure 112, so that the encapsulating layer 31 forms an encapsulating structure protrusion 212 at a position corresponding to the groove structure 112.
In some embodiments, the depth of the groove structures 112 is greater than or equal to 10 μm. The depth range of the protrusion 212 of the encapsulation structure is formed to be the same as the thickness range of the groove structure 112, that is, the thickness of the protrusion 212 of the encapsulation structure is greater than or equal to 10 μm. With such a configuration, it can be avoided that the thickness of the projection portion 212 of the encapsulation structure is too small, so that the contrast between the projection portion 212 of the encapsulation structure and other regions in the image obtained by the image capturing device is low, and the projection portion 212 of the encapsulation structure is not easily recognized.
Further, the depth of the groove structure 112 is less than or equal to 20 μm. The surface of the dielectric layer to be formed in the subsequent step during the formation of the redistribution layer is required to be flat, so that the thickness of the dielectric layer to be formed in the subsequent step can be prevented from being too large due to the too large thickness of the protrusion 212 of the encapsulation structure, and the depth of the groove structure 112, which is not easily realized by the process, can be, for example, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, and the like. In the embodiment shown in fig. 2, the cross section of the groove structure 112 is only illustrated as a circle, and in other embodiments, the cross section of the groove structure 112 may also be rectangular, circular, or the like.
In a further embodiment, when the auxiliary structure 11 is integrally formed with the body 12, the auxiliary structure 11 includes at least one protrusion structure and at least one groove structure formed on the surface of the body 12, and the positioning structure 21 includes an envelope structure groove portion formed on the surface of the envelope structure 30 and corresponding to the protrusion structure, and an envelope structure protrusion portion formed on the surface of the envelope structure and corresponding to the groove structure. For example, the auxiliary structure 11 on the surface of the body 12 includes two convex structures and two concave structures, and the positioning structure includes two concave portions and two convex portions formed on the surface of the enclosing structure 30.
In the above three embodiments, the auxiliary structure 11 and the body 12 are integrally formed, so that the auxiliary structure 11 does not displace relative to the body 12 in the process of forming the encapsulation layer, and the position of the positioning structure 21 formed on the encapsulation structure does not shift; and the positioning structures 21 and the encapsulating layer 31 are integrally formed, after the encapsulating structure 30 is subsequently peeled off from the body 12, when the encapsulating layer 31 shrinks, the positioning structures 21 shrink together, the distances between different positioning structures 21 change, the deviation between the actual distance between different positioning structures 21 and the design distance (the distance between different positioning structures 21 before the encapsulating structure 30 is not peeled off from the body 12 is the design distance) can be calculated, the position to be exposed is determined according to the actual distance between different positioning structures 21 and the corresponding deviation, and the accuracy of the determined position to be exposed is ensured.
In another embodiment, the encapsulating layer 31 encapsulates the frame body 113, and the frame body 113 is a one-piece structure, that is, the frame body 113 is a one-piece structure independent from the body 12. The encapsulating structure 30 further comprises the frame body 113. Referring to fig. 7 and 13, the frame body 113 includes a first surface 1131 and a second surface 1132 which are opposite to each other, the first surface 1131 is located on the same side as the front surface of the chip 20 to be packaged, and the positioning structure 21 includes the frame body 113. With this arrangement, when the encapsulating layer 31 is formed, the encapsulating layer 31 encapsulates the frame body 113, and after the encapsulating structure 30 is subsequently peeled off from the body 12, the frame body 113 is separated from the body 12, the first surface 1131 of the frame body 113 is exposed, and a position to be exposed can be determined by the frame body 113. Since the frame body 113 is an independent component, the position of the positioning structure is not affected by the encapsulating material when the encapsulating layer 31 is formed, that is, the position of the positioning structure is not changed, and after the encapsulating structure 30 is peeled off from the body 12 in the subsequent step, the exposure position determined according to the position of the positioning structure has higher precision, which is helpful for improving the exposure precision.
In one embodiment, the first surface 1131 includes a positioning region 1133, the number of the positioning regions 1133 may be multiple, and the positioning region 1133 is provided with a frame body recess 1134. With the arrangement, the contrast between the light and the shade of the positioning region 1133 and other regions of the first surface 1131 in the image acquired by the camera device can be different, which is convenient for identifying the positioning region 1133. In some embodiments, the frame body recesses 1134 of the positioning region 1133 may be in a specific pattern.
In one embodiment, the number of the chips 20 to be packaged is multiple, the auxiliary structure 11 further includes a plurality of rods 114 located in the frame 113 and connected to the frame 113, the plurality of rods 114 divide an area enclosed by the frame 113 into a plurality of hollow areas, and the chips 20 to be packaged are located in the hollow areas. The number of the hollow areas and the number of the chips 20 to be packaged may be the same and may correspond one to one, and each chip 20 to be packaged is located in the corresponding hollow area. By arranging the rod part 114, the strength of the auxiliary structure 11 can be increased, and the change of the relative positions of different positioning regions 1133 caused by the deformation of the frame body 113 in the process of attaching the auxiliary structure 11 to the body 12 or in the process of forming the encapsulating layer 31 can be avoided, which is beneficial to improving the exposure precision; moreover, the frame body 113 is divided into a plurality of hollow areas by the rod portion 114, and each hollow area is provided with one chip 20 to be packaged, so that the rod portion 114 can perform an alignment function when the chip 20 to be packaged is mounted, and the accuracy of mounting the chip 20 to be packaged is improved. In some embodiments, the frame body 113 and the shaft portion 114 may be made of metal.
In step 130, when the auxiliary structure and the body are integrally formed, the carrier plate is peeled off to expose the positioning structure and the chip to be packaged; when the auxiliary structure is of an integrated structure, the body is peeled off, and the positioning structure and the chip to be packaged are exposed.
A third intermediate structure as shown in fig. 14, 15 or 16 may be obtained through step 130.
In one embodiment, the carrier plate 10 or the body 12 can be mechanically peeled off from the encapsulating structure 30 directly. In another embodiment, the chip 20 to be packaged and the body 12 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer may be heated to reduce its viscosity, so as to peel off the body 12 or the carrier 10. If the chips 20 to be packaged are attached to the body 12 with the front surfaces of the chips 20 facing the body 12, the front surfaces of the chips 20 to be packaged are exposed after the body 12 or the carrier 10 is peeled. When the auxiliary structure includes the frame body 113, the frame body 113 and the body 12 are bonded through the adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer can be heated to reduce the viscosity, so that the body 12 is peeled off to expose the first surface of the frame body.
In one embodiment, referring to fig. 17, the front surface of the chip is on the same side as the positioning structure, and the front surface of the chip is exposed after the body 12 is peeled off. After the step 130 of peeling the body, the semiconductor packaging method further includes the following steps 140 to 170.
In step 140, a conductive layer is formed on the front side of the chip.
Before this step, the third intermediate structure is first turned over so that the front side of the chip 20 faces upward, and is fixed to the support plate, facilitating the subsequent formation of a conductive layer on the front side of the chip.
When the conductive layer is formed, a seed layer may be formed first, and then a metal layer may be formed on the seed layer by using an electroplating process, where the conductive layer includes the seed layer and the metal layer. The seed layer and the metal layer can cover the front surface of the chip and the packaging layer.
In step 150, a photoresist layer is formed on the conductive layer, and the position of the photoresist layer to be exposed is determined according to the positioning structure.
In step 160, the photoresist layer is exposed according to the position to be exposed, so as to perform a patterning process on the photoresist layer, thereby obtaining a photoresist layer.
In this step, after the position to be exposed is exposed, the photoresist film layer may be patterned through a developing process.
In step 170, the area of the conductive layer not covered by the photoresist layer is etched to obtain a rewiring layer.
A fourth intermediate structure as shown in fig. 18, 19 and 20 may be obtained through step 170. The rewiring layer includes conductive structures 50 for routing out pads on the front side of the chip.
Because the position of the positioning structure in the third intermediate structure is accurate, the position of the photoresist film layer to be exposed, which is determined according to the positioning structure, is accurate, the pattern of the photoresist layer is accurate, and the reliability of the rewiring layer in the obtained fourth intermediate structure is high.
In an embodiment, after the etching is performed on the region of the conductive layer that is not covered by the photoresist layer, an obtained structure is a semiconductor packaging structure, and the semiconductor packaging method further includes: removing the photoresist layer; and cutting the semiconductor packaging structure, and removing the positioning structure.
When the semiconductor package structure is diced, dicing is performed along the dotted lines shown in fig. 18, 19, and 20, so that a packaged chip can be obtained. And, the positioning structure is removed in the process of cutting the semiconductor package structure, and when the positioning structure includes the frame body, the link is also removed.
In the embodiment of the application, the positioning structure can also be used for positioning a cutting position when the semiconductor packaging structure is cut, or can also be used for positioning a printing position when product information is printed on the surface of the chip.
The embodiment of the application also provides a carrier plate for the semiconductor packaging method. Referring to fig. 2, 3, 5, 7 and 8, the carrier 10 includes a body 12 and an auxiliary structure 11, and a surface of the body 12 includes a first region 101 and a second region 102. The auxiliary structure 12 is disposed in the first region 101, and the second region 102 is used for mounting a chip to be packaged; the auxiliary structure 11 and the body 12 are integrally formed, or the auxiliary structure 11 is an integrated structure.
In one embodiment, the auxiliary structure 11 is integrally formed with the body 12, and the auxiliary structure 11 includes a plurality of protruding structures 111 and/or at least one groove structure 112 formed on the surface of the body 12.
In some embodiments, the thickness of the raised structures 111 is greater than or equal to 10 μm and the depth of the recessed structures 112 is greater than or equal to 10 μm.
In the embodiment shown in fig. 3, the auxiliary structure 11 comprises a plurality of protruding structures 111. In the embodiment shown in fig. 5, the auxiliary structure 11 comprises a plurality of recessed portions 112.
In one embodiment, referring to fig. 7 and 8, when the auxiliary structure 11 is a one-piece structure, the auxiliary structure 11 includes a frame body 113; the frame body 113 includes a first surface 1131 and a second surface 1132 opposite to each other, and the first surface 1131 faces the body.
In some embodiments, the first surface 1131 includes a positioning region 1133, and the positioning region 1133 is provided with a frame body recess 1134.
In one embodiment, the auxiliary structure 11 further includes a plurality of rods 114 located in the frame 113 and connected to the frame 113, and the rods 114 divide an area enclosed by the frame 113 into a plurality of hollow areas.
The carrier for the semiconductor packaging method provided by the embodiment of the present application and the embodiments of the semiconductor packaging method belong to the same inventive concept, and the description of the relevant details and the beneficial effects can be referred to each other, which is not repeated herein.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A semiconductor packaging method, comprising:
mounting at least one chip to be packaged on a carrier plate; the carrier plate comprises a body and an auxiliary structure arranged on the surface of the body, the surface of the body comprises a first area and a second area, and the at least one chip to be packaged is attached to the second area of the body; the auxiliary structure is arranged in the first area of the body and is integrally formed with the body, or the auxiliary structure is an integrated structure;
forming an encapsulating layer on the carrier plate, wherein the encapsulating layer encapsulates the at least one chip to be encapsulated, so as to obtain an encapsulating structure comprising the at least one chip to be encapsulated and the encapsulating layer; the auxiliary structure enables the enclosing structure to form a positioning structure close to the surface of the body;
when the auxiliary structure and the body are integrally formed, the carrier plate is peeled off to expose the positioning structure and the chip to be packaged; when the auxiliary structure is of an integrated structure, the body is peeled off, and the positioning structure and the chip to be packaged are exposed.
2. The semiconductor packaging method according to claim 1, wherein the auxiliary structure comprises a plurality of protruding structures formed on the surface of the body when the auxiliary structure is integrally formed with the body, and the positioning structure comprises an encapsulating structure groove portion formed on the surface of the encapsulating structure and corresponding to each protruding structure; alternatively, the first and second electrodes may be,
when the auxiliary structure is integrally formed with the body, the auxiliary structure comprises a plurality of groove structures formed on the surface of the body, and the positioning structure comprises an encapsulating structure protruding part formed on the surface of the encapsulating structure and corresponding to each groove structure; alternatively, the first and second electrodes may be,
when the auxiliary structure is integrally formed with the body, the auxiliary structure comprises at least one protrusion structure and at least one groove structure formed on the surface of the body, and the positioning structure comprises an encapsulating structure groove part corresponding to the protrusion structure and formed on the surface of the encapsulating structure and an encapsulating structure protrusion part corresponding to the groove structure.
3. The semiconductor packaging method according to claim 1, wherein when the auxiliary structure is a one-piece structure, the auxiliary structure includes a frame body, and the frame body includes a first surface and a second surface opposite to each other;
before the mounting of the at least one chip to be packaged on the carrier, the semiconductor packaging method further includes: attaching the first surface of the frame body to the first region of the body;
the encapsulating layer also encapsulates the frame body, the encapsulating structure further comprising the frame body; the positioning structure comprises the frame body; the first surface of the frame body includes a plurality of positioning regions provided with frame body recesses.
4. The semiconductor packaging method according to claim 3, wherein the number of the chips to be packaged is plural, the auxiliary structure further comprises a plurality of rod portions located in the frame body and connected to the frame body, the plurality of rod portions partition a region enclosed by the frame body into a plurality of hollow-out regions, and the chips to be packaged are located in the hollow-out regions.
5. The semiconductor packaging method according to claim 1, wherein the front surface of the chip is located on the same side as the positioning structure; when the auxiliary structure is an integrated structure, after the positioning structure and the chip to be packaged are exposed by peeling the body, or when the auxiliary structure and the body are integrally formed, after the positioning structure and the chip to be packaged are exposed by peeling the carrier plate, the semiconductor packaging method further includes:
forming a conductive layer on the front surface of the chip;
forming a light resistance film layer on the conducting layer, and determining the position of the light resistance film layer to be exposed according to the positioning structure;
exposing the light resistance film layer according to the position to be exposed so as to perform graphical processing on the light resistance film layer to obtain a light resistance layer;
and etching the area of the conducting layer which is not shielded by the photoresist layer to obtain a rewiring layer.
6. The carrier plate for the semiconductor packaging method is characterized by comprising a body and an auxiliary structure, wherein the surface of the carrier plate comprises a first area and a second area; the auxiliary structure is arranged in the first area, and the second area is used for mounting a chip to be packaged; the auxiliary structure and the body are integrally formed, or the auxiliary structure is of an integrated structure.
7. The carrier board for semiconductor packaging method according to claim 6, wherein the auxiliary structure comprises at least one protrusion structure and/or at least one groove structure formed on the surface of the body when the auxiliary structure is integrally formed with the body.
8. The carrier board for semiconductor packaging method according to claim 7, wherein the thickness of the bump structure is greater than or equal to 10 μm; the depth of the groove structure is greater than or equal to 10 μm.
9. The carrier board for semiconductor packaging method according to claim 6, wherein the auxiliary structure comprises a frame body when the auxiliary structure is a one-piece structure; the frame body comprises a first surface and a second surface which are opposite, and the first surface faces the body;
the first surface of the frame body includes a plurality of positioning regions, which are provided with depressions.
10. The carrier board according to claim 9, wherein when the auxiliary structure is an integrated structure, the auxiliary structure further comprises a plurality of bars located in the frame and connected to the frame, and the bars divide an area enclosed by the frame into a plurality of hollow areas.
CN202010955760.3A 2020-09-11 2020-09-11 Semiconductor packaging method and carrier plate used for semiconductor packaging method Pending CN114171396A (en)

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Application Number Priority Date Filing Date Title
CN202010955760.3A CN114171396A (en) 2020-09-11 2020-09-11 Semiconductor packaging method and carrier plate used for semiconductor packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

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