Satellite-borne multi-source remote sensing load imaging processing unit
Technical Field
The invention relates to a satellite-borne multi-source remote sensing load imaging processing unit, and belongs to the field of space remote sensing.
Background
The miniature distributed reconfigurable remote sensing system needs to acquire image information of various types and different resolutions quickly, and needs to be assembled with image sensors of different types. The existing imaging processing circuit is customized and researched according to different requirements, various load interfaces are different, if various load interfaces, image data processing and transmission are integrated into a multi-source remote sensing load imaging processing unit module, the module is huge in size, difficult to realize miniaturization, not beneficial to system expansion and the like, and the requirements of quick assembly, test and emission of a miniature remote sensing constellation cannot be met.
Therefore, how to realize a multi-source remote sensing load imaging processing unit which can be compatible with input interfaces of different image sensors and can also provide a standardized electrical interface with a satellite is a main problem to be solved by the invention.
Disclosure of Invention
The invention aims to provide a satellite-borne multi-source remote sensing load imaging processing unit to solve the problems that an existing imaging processing circuit cannot be compatible with different image sensors and is not beneficial to miniaturization and system expansion.
The utility model provides a satellite-borne multisource remote sensing load imaging processing unit, processing unit includes heterogeneous load interface unit module and isomorphic imaging processing unit module, heterogeneous load interface unit module and isomorphic imaging processing unit module both way junction, heterogeneous load interface unit module includes heterogeneous image sensor input interface and isomorphic image sensor processing circuit, isomorphic imaging processing unit module includes isomorphic image data intelligence preprocessing circuit and isomorphic image data output interface, isomorphic image sensor input interface, heterogeneous image sensor processing circuit, isomorphic image data intelligence preprocessing circuit and isomorphic image data output interface connect gradually.
Further, the heterogeneous load interface unit module is configured to complete driving of the heterogeneous image sensor processing circuit, preprocess load data to form uniform format data, and exchange data with the homogeneous imaging processing unit module through a uniform standard interface;
the isomorphic imaging processing unit module is used for carrying out image intelligent preprocessing on the received uniform format data to form whole frame effective image data, storing and compressing the whole frame effective image data, and transmitting the whole frame effective image data to the data transmission subsystem through a standard bus interface for downlink transmission.
Furthermore, the heterogeneous image sensor processing circuit comprises a voltage conversion circuit, a synchronous dynamic random access memory, a first FPGA chip, a SerDes interface, a driving interface and an input interface, wherein the first FPGA chip comprises an image buffer interface, a heterogeneous data normalization processing module, an image preprocessing module, a normalization SerDes controller, a housekeeping bus control module and a PPS receiving processing module, the heterogeneous image sensor input interface is externally connected with a heterogeneous load, the heterogeneous image sensor input interface, the image buffer interface, the heterogeneous data normalization processing module, the image preprocessing module and the normalization SerDes controller are sequentially connected, the normalization SerDes controller is in data intercommunication with the SerDes interface, the SerDes interface is in data intercommunication with the homogeneous imaging processing unit module, the input interface is in data intercommunication with the housekeeping bus control module, and the housekeeping bus control module is in data intercommunication with the driving interface, the input interface, the PPS receiving processing module and the driving interface are sequentially connected, the voltage conversion circuit supplies power to the heterogeneous image sensor processing circuit, and the synchronous dynamic random access memory is in data intercommunication with the first FPGA chip.
Furthermore, the isomorphic imaging processing unit module comprises a voltage conversion circuit, a storage module, a compression module, a DDR memory and a second FPGA chip, wherein the second FPGA chip comprises an image preprocessing module, a bus transceiver module and a PPS receiving module, the isomorphic preprocessing module is externally connected with a unified interface and an isomorphic data transmission interface, the isomorphic preprocessing module is respectively in data intercommunication with the unified interface and the isomorphic data transmission interface, the bus transceiver module is respectively in data intercommunication with the unified interface and the isomorphic data transmission interface, the unified interface is connected with the PPS receiving module, the DDR memory and the storage module are respectively in data intercommunication with the second FPGA chip, and the voltage conversion circuit supplies power to the isomorphic imaging processing unit module.
Furthermore, the imaging processing unit of the satellite-borne multi-source remote sensing load further comprises an imaging unit and a processing unit, and interfaces between the imaging unit and the processing unit are divided into a power supply interface, a communication interface and an image data interface.
The main advantages of the invention are: the satellite-borne multi-source remote sensing load imaging processing unit can be compatible with different image sensors, has the advantages of miniaturization and convenience in expansion, is standardized in interface, and can be used in a plug-and-play mode.
Drawings
FIG. 1 is a schematic block diagram of a multi-source remote sensing load;
FIG. 2 is an internal block diagram of a heterogeneous load interface unit module;
FIG. 3 is an internal block diagram of a homogeneous imaging processing unit module;
FIG. 4 is a schematic diagram of a standardized interface of a satellite-borne multi-source remote sensing load imaging processing unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a satellite-borne multi-source remote sensing load imaging processing unit comprises a heterogeneous load interface unit module and a homogeneous imaging processing unit module, wherein the heterogeneous load interface unit module is bidirectionally connected with the homogeneous imaging processing unit module, the heterogeneous load interface unit module comprises a heterogeneous image sensor input interface and a heterogeneous image sensor processing circuit, the homogeneous imaging processing unit module comprises a homogeneous image data intelligent preprocessing circuit and a homogeneous image data output interface, and the heterogeneous image sensor input interface, the heterogeneous image sensor processing circuit, the homogeneous image data intelligent preprocessing circuit and the homogeneous image data output interface are sequentially connected.
In the preferred embodiment of this part, the heterogeneous load interface unit module is configured to complete driving of a heterogeneous image sensor processing circuit, preprocess load data to form uniform format data, and perform data exchange with the homogeneous imaging processing unit module through a uniform standard interface;
and the isomorphic imaging processing unit module is used for carrying out image intelligent preprocessing on the received uniform format data to form whole frame effective image data, storing and compressing the whole frame effective image data, and transmitting the whole frame effective image data to the data transmission subsystem through a standard bus interface for downlink transmission.
In a preferred embodiment of this part, the heterogeneous image sensor processing circuit comprises a voltage conversion circuit, a synchronous dynamic random access memory, a first FPGA chip, a SerDes interface, a driving interface and an input interface, wherein the first FPGA chip comprises an image buffer interface, a heterogeneous data normalization processing module, an image preprocessing module, a normalization SerDes controller, a housekeeping bus control module and a PPS receiving processing module, the heterogeneous image sensor input interface is externally connected with a heterogeneous load, the heterogeneous image sensor input interface, the image buffer interface, the heterogeneous data normalization processing module, the image preprocessing module and the normalization SerDes controller are sequentially connected, the normalization SerDes controller is in data intercommunication with the SerDes interface, the SerDes interface is in data intercommunication with the homogeneous imaging processing unit module, the input interface is in data intercommunication with the housekeeping bus control module, and the housekeeping bus control module is in data intercommunication with the driving interface, the input interface, the PPS receiving processing module and the driving interface are sequentially connected, the voltage conversion circuit supplies power to the heterogeneous image sensor processing circuit, and the synchronous dynamic random access memory is in data intercommunication with the first FPGA chip.
In this preferred embodiment, the isomorphic imaging processing unit module includes a voltage conversion circuit, a storage module, a compression module, a DDR memory and a second FPGA chip, the second FPGA chip includes an image preprocessing module, a bus transceiver module and a PPS receiving module, the isomorphic preprocessing module is externally connected with a unified interface and an isomorphic data transmission interface, the isomorphic preprocessing module is respectively in data intercommunication with the unified interface and the isomorphic data transmission interface, the bus transceiver module is respectively in data intercommunication with the unified interface and the isomorphic data transmission interface, the unified interface is connected with the PPS receiving module, the DDR memory, the storage module and the compression module are respectively in data intercommunication with the second FPGA chip, and the voltage conversion circuit supplies power to the isomorphic imaging processing unit module.
In the preferred embodiment of the part, the satellite-borne multi-source remote sensing load imaging processing unit further comprises an imaging unit and a processing unit, and interfaces between the imaging unit and the processing unit are divided into a power interface, a communication interface and an image data interface, so that the hardware interfaces are completely consistent, and plug and play are convenient to realize.
The implementation process is described below with a multisource remote sensing load integrated camera:
function division: divide whole multisource remote sensing load imaging processing unit into two standard modules: the heterogeneous load interface unit module and the homogeneous imaging processing unit module.
Heterogeneous load interface unit module: the heterogeneous load interface unit module comprises an image sensor and a peripheral driving circuit, carries out preprocessing on load data to form uniform format data, and carries out data exchange with the homogeneous imaging processing unit module through a uniform standard interface. The image sensors adopted by various loads are different, the normalized SerDes controller SerDes interface is responsible for processing image data needing interaction into the same format standard, and the imaging unit is adaptively modified, so that the design of the imaging system with novel loads can be realized.
Isomorphic imaging processing unit module: the isomorphic imaging processing unit adopts the design of miniaturized circuits such as SIP (session initiation protocol), and the like, has the functions of sensor drive control, image receiving, image storage compression, downlink transmission and the like, adopts the isomorphic hardware design, is compatible with the intelligent preprocessing of heterogeneous multisource image sensor data in hardware, provides a standardized electrical interface between the isomorphic hardware processing unit and a data transmission channel, and only needs to realize different software programs according to different sensor models.
Referring to fig. 4, interface standardization: the interface between the imaging unit and the processing unit is standardized and divided into a power interface, a communication interface and an image data interface, so that the hardware interfaces are completely consistent. The camera imaging system adopts a stacked structure, the electric connector between the high-speed boards completes signal transmission, and different imaging unit boards are replaced according to different load tasks, so that plug and play are conveniently realized.