CN214480992U

CN214480992U - Coding core board adaptable to various video formats

Info

Publication number: CN214480992U
Application number: CN202120559010.4U
Authority: CN
Inventors: 石园丁; 马小鹏; 马鹏飞
Original assignee: CETC 52 Research Institute
Current assignee: CETC 52 Research Institute
Priority date: 2021-03-18
Filing date: 2021-03-18
Publication date: 2021-10-22
Anticipated expiration: 2031-03-18

Abstract

The utility model discloses a core plate of coding of adaptable multiple video format, including the treater, network PHY chip, the video conversion module, an at least video format receiver and interface module, network PHY chip, video conversion module and interface module all are connected with the treater, network PHY chip still is connected with interface module, each video format receiver is connected with video conversion module or treater respectively, and each video format receiver still all is connected with interface module, the video format receiver corresponds the video signal of receiving interface module input and converts into same video format and sends to the treater and carry out the coding output. The core board meets the requirement of video processing with ultrahigh definition resolution, can meet the requirements of video processing with various video formats and connection and data storage of various external devices, and is wide in application range.

Description

Coding core board adaptable to various video formats

Technical Field

The utility model belongs to the technical field of the video monitoring, concretely relates to core plate of coding of adaptable multiple video format.

Background

In recent years, video monitoring technology has been rapidly developed, and various video monitoring devices are widely applied to security and protection in public places. The digital hard disk video recorder is used as a main device of a video monitoring system, and a video coding circuit is an indispensable circuit of the digital hard disk video recorder. In order to design conveniently, reduce development cycle and the like, some digital hard disk video recorder manufacturers design a video coding circuit into a core board independently. The core board is integrated with a central processing unit, an audio and video acquisition chip for acquiring audio and video signals, a memory, a network PHY chip, an interface module connected with an external interface and the like.

However, with the development of video technology, the resolution of video signals to be processed is higher and higher, and the video formats and interfaces are richer and more diverse. The video coding core board in the prior art cannot meet the processing requirements of ultra-high definition videos, and the input video format of the video coding core board in the prior art is relatively fixed and cannot meet the processing requirements of multiple video formats, so that the application is not flexible and the use is limited.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to the above-mentioned problem, provide a core plate of coding of adaptable multiple video format, satisfy the video processing demand of the clear resolution ratio of superelevation to the video processing of adaptable multiple video format and multiple external equipment are connected, the data storage demand, and application scope is wide.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the utility model provides a core plate of coding of adaptable multiple video format, which comprises a processor, still include network PHY chip, the video conversion module, an at least video format receiver and interface module, network PHY chip, video conversion module and interface module all are connected with the treater, each video format receiver is connected with video conversion module or treater respectively, and network PHY chip and each video format receiver still all are connected with interface module, the video format receiver corresponds the video signal who receives interface module input, and send the video signal of receipt to the treater through video conversion module conversion or direct conversion to same video format and carry out the code output.

Preferably, the processor is Hi 3531D.

Preferably, the network PHY chip is a 10M/100M/1000M adaptive chip.

Preferably, the coding core board capable of adapting to various video formats further comprises a synchronous dynamic memory for code running and data caching, an SPI NOR Flash memory for code storage and a clock chip, and the synchronous dynamic memory, the SPI NOR Flash memory and the clock chip are connected with the processor.

Preferably, the coding core board adaptable to a plurality of video formats further comprises a power supply module, wherein the power supply module is connected with the interface module and supplies power to the processor, the synchronous dynamic memory, the SPI NOR Flash memory, the network PHY chip, the clock chip, the video conversion module and each video format receiver.

Preferably, the at least one video format receiver includes at least one of an RGB a/D converter, a Camera Link receiver, a DVI receiver, and an SDI receiver.

Preferably, the video conversion module is an FPGA module, the RGB a/D converter, the Camera Link receiver and the DVI receiver are all connected to the FPGA module, and the SDI receiver is connected to the processor.

Preferably, the interface module includes a VGA interface, a Camera Link interface, a DVI interface, an SDI interface, a network interface, a SATA interface, an HDMI interface, a UART interface, an SPI interface, an I2C interface, and an I2S interface, respectively, for external connection.

Preferably, the size of the coding core plate that can accommodate multiple video formats is 100mm × 85 mm.

Compared with the prior art, the beneficial effects of the utility model are that:

1) the core board can simultaneously input a plurality of paths of video signals with different formats and convert the video signals with different formats into a uniform video format which can be processed by the processor, is suitable for video processing of various video formats and has wide application range;

2) the interface module of the core board is integrated with various interfaces, so that the core board is suitable for the requirements of connection of various external devices, data storage and the like under different application scenes, and has wide application scenes and good universality;

3) this nuclear core plate satisfies small-size lightweight demand to adopt high performance treater, satisfy the video processing demand of the clear resolution ratio of superelevation.

Drawings

Fig. 1 is a schematic view of the overall structure of the coding core board of the present invention;

fig. 2 is a flow chart of the video signal encoding of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

As shown in fig. 1-2, an encoding core board adaptable to multiple video formats includes a processor, a network PHY chip, a video conversion module, at least one video format receiver, and an interface module, where the network PHY chip, the video conversion module, and the interface module are all connected to the processor, each video format receiver is respectively connected to the video conversion module or the processor, and the network PHY chip and each video format receiver are also connected to the interface module, and the video format receiver receives a video signal input by the interface module correspondingly, and converts the received video signal into the same video format through the video conversion module or directly converts the same video format, and sends the video signal to the processor for encoding and outputting.

The processor is used for encoding and processing video signals, the network PHY chip can transmit data encoded by the processor to a network, the receiver adopting at least one video format can simultaneously input a plurality of paths of video signals with different formats, and the video conversion module can convert the video signals with different formats into a unified video format for processing by the processor. The core board converts video signals with different formats into a unified video format which can be processed by the processor through the video conversion module or directly converts the video signals into the unified video format which can be processed by the processor, is suitable for video processing of various video formats, and has good universality.

In one embodiment, the processor is Hi 3531D.

The processor can adopt a Haisi Hi3531D high-performance processor, meets the video processing requirement of ultra-high definition resolution, and can perform model selection according to the actual requirement.

In one embodiment, the network PHY chip is a 10M/100M/1000M adaptive chip.

The network PHY chip is configured to transmit data encoded by the processor to a network, and may be a 10M/100M/1000M adaptive chip (the model is 88E 1512).

In one embodiment, the coding core board capable of adapting to various video formats further comprises a synchronous dynamic memory for code running and data caching, an SPI NOR Flash memory for code storage and a clock chip, and the synchronous dynamic memory, the SPI NOR Flash memory and the clock chip are connected with the processor.

The SPI NOR Flash memory is used for code storage (for example, the model is MX25L25635F), the synchronous dynamic memory is used for code operation and data caching, and can be composed of a plurality of DDR3 (for example, the model is MT41K256M16HA-125), the synchronous dynamic memory in the embodiment is preferably composed of four DDR3, and a clock chip (for example, the model is 24MHZ crystal) can provide a clock reference for the core board. It should be noted that, in practical application, the SPI NOR Flash memory, the synchronous dynamic memory, and the clock chip may be selected according to actual requirements.

In an embodiment, the coding core board adaptable to a plurality of video formats further includes a power supply module, and the power supply module is connected to the interface module and supplies power to the processor, the synchronous dynamic memory, the SPI NOR Flash memory, the network PHY chip, the clock chip, the video conversion module, and each video format receiver.

The core board is connected with direct-current voltage, such as voltage 5V, through the interface module, and is converted and output to supply power for the processor, the synchronous dynamic memory, the SPI NOR Flash memory, the network PHY chip, the clock chip, the video conversion module and the voltage required by each video format receiver on the core board through the power module.

In an embodiment, the at least one video format receiver comprises at least one of an RGB a/D converter, a Camera Link receiver, a DVI receiver, and an SDI receiver.

The RGB a/D converter (for example, model AD9888), the Camera Link receiver (for example, model DS90CR286), the DVI receiver (for example, model TFP401), and the SDI receiver (for example, model GS2971) are all used for video interface format conversion, and the core board of this embodiment includes four video format receivers, namely, an RGB a/D converter, a Camera Link receiver, a DVI receiver, and an SDI receiver, and can be respectively used for VGA, Camera Link, DVI, and SDI video format conversion. It should be noted that the type or number of the video format receivers can also be set according to actual requirements.

In one embodiment, the video conversion module is an FPGA module, the RGB a/D converter, the Camera Link receiver, and the DVI receiver are all connected to the FPGA module, and the SDI receiver is connected to the processor.

The FPGA module (for example, XC7A100T-2CSG324 is selected as a model) is used for color space conversion, and sends video data to the processor for encoding processing according to a specified format and a time sequence requirement. It should be noted that the video conversion module may also be another chip used for implementing color space conversion in the prior art, such as a video decoding chip corresponding to each video format respectively.

In one embodiment, the interface module includes a VGA interface, a Camera Link interface, a DVI interface, an SDI interface, a network interface, a SATA interface, an HDMI interface, a UART interface, an SPI interface, an I2C interface, and an I2S interface, respectively, for external connection.

The VGA interface, the Camera Link interface, the DVI interface and the SDI interface are respectively used for receiving video signals in different formats, the SATA interface is used for being externally connected with a storage medium such as a solid state disk, the HDMI interface is used for video display output, the UART interface can be used as a debugging interface, the SPI interface and the I2C interface can be used for configuring an external audio Codec chip, and the I2S interface can be used for carrying out data transmission with the external audio Codec chip. The interface module of the core board is integrated with various interfaces, is suitable for connecting different external equipment, storage media and other requirements, and has wide application scenes and good universality.

In one embodiment, the size of the encoding core plate that can accommodate multiple video formats is 100mm × 85 mm.

The core plate has the size of 100mm multiplied by 85mm, meets the requirement of small and light weight, and contributes to reducing the size and weight of equipment.

The operating principle of the core board is as follows:

the core board comprises four video format receivers including an RGB A/D converter, a Camera Link receiver, a DVI receiver and an SDI receiver, and is used for VGA, Camera Link, DVI and SDI video format conversion respectively. The RGB A/D converter receives RGB analog video signals and carries out A/D conversion on the RGB analog video signals, the 24-bit digital RGB video data, a line synchronizing signal, a field synchronizing signal and a pixel clock signal which are converted and output are all input into the FPGA module, RGB to YCbCr color space conversion is carried out through the FPGA module, and the video data are sent to the processor according to format and time sequence requirements specified by BT.1120 standards. The Camera Link receiver receives the serial differential LVDS video signal and converts the LVDS video signal, the 24bits digital RGB video data, a line synchronizing signal, a field synchronizing signal, a pixel clock signal and a data enabling signal which are converted and output are all input into the FPGA module, RGB to YCbCr color space conversion is carried out through the FPGA module, and the video data are sent to the processor according to the format and time sequence requirements specified by the BT.1120 specification. The DVI receiver receives and converts the serial differential TMDS video signals, the 24bits digital RGB video data, a line synchronizing signal, a field synchronizing signal, a pixel clock signal and a data enable signal which are converted and output are all input into the FPGA module, RGB to YCbCr color space conversion is carried out through the FPGA module, and the video data are sent to the processor according to the format and time sequence requirements specified by the BT.1120 specification. The SDI receiver receives the single-ended serial digital video signal and converts the single-ended serial digital video signal, and the output video data is sent to the processor according to the format and timing requirements specified by the bt.1120 specification. The four paths of input video data with different formats (VGA, Camera Link, DVI and SDI video grids) are uniformly converted into a digital video interface BT.1120 to be accessed into a processor, and the processor simultaneously carries out H.264/H.265 coding on the four paths of video. The code stream output by the coding can be transmitted to a network interface of the interface module through a network PHY chip, and is transmitted to an upper computer or other equipment by the network interface of the interface module for further processing or storage, and can also be directly stored to an external solid state disk through an SATA interface.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express the more specific and detailed embodiments described in the present application, but not should be interpreted as limiting the scope of the claims of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. An encoding core board adaptable to a plurality of video formats, comprising a processor, characterized in that: the coding core board adaptable to various video formats further comprises a network PHY chip, a video conversion module, at least one video format receiver and an interface module, wherein the network PHY chip, the video conversion module and the interface module are all connected with the processor, each video format receiver is respectively connected with the video conversion module or the processor, the network PHY chip and each video format receiver are also connected with the interface module, the video format receivers correspondingly receive video signals input by the interface module and convert the received video signals into the same video format through the video conversion module or directly convert the video signals into the same video format and send the same video format to the processor for coding output.

2. The coding core board of claim 1, adapted to accommodate a plurality of video formats, wherein: the processor is Hi 3531D.

3. The coding core board of claim 1, adapted to accommodate a plurality of video formats, wherein: the network PHY chip is a 10M/100M/1000M self-adaptive chip.

4. The coding core board of claim 1, adapted to accommodate a plurality of video formats, wherein: the coding core board capable of adapting to various video formats further comprises a synchronous dynamic memory for code operation and data caching, an SPI NOR Flash memory for code storage and a clock chip, and the SPI NOR Flash memory and the clock chip are connected with the processor.

5. The coding core board of claim 4, adapted to accommodate a plurality of video formats, wherein: the coding core board capable of adapting to various video formats further comprises a power supply module, wherein the power supply module is connected with the interface module and supplies power to the processor, the synchronous dynamic memory, the SPI NOR Flash memory, the network PHY chip, the clock chip, the video conversion module and each video format receiver.

6. The coding core board of claim 1, adapted to accommodate a plurality of video formats, wherein: the at least one video format receiver includes at least one of an RGB a/D converter, a Camera Link receiver, a DVI receiver, and an SDI receiver.

7. The coding core board of claim 6, adapted to accommodate a plurality of video formats, wherein: the video conversion module is an FPGA module, the RGB A/D converter, the Camera Link receiver and the DVI receiver are all connected with the FPGA module, and the SDI receiver is connected with the processor.

8. The coding core board of claim 1, adapted to accommodate a plurality of video formats, wherein: the interface module comprises a VGA interface, a Camera Link interface, a DVI interface, an SDI interface, a network interface, a SATA interface, an HDMI interface, a UART interface, an SPI interface, an I2C interface and an I2S interface which are respectively used for being connected with the outside.

9. The coding core board of claim 1, adapted to accommodate a plurality of video formats, wherein: the size of the encoding core plate capable of adapting to various video formats is 100mm multiplied by 85 mm.