CN221101383U - Camellink signal simulator with USB interface - Google Patents
Camellink signal simulator with USB interface Download PDFInfo
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- CN221101383U CN221101383U CN202323248775.4U CN202323248775U CN221101383U CN 221101383 U CN221101383 U CN 221101383U CN 202323248775 U CN202323248775 U CN 202323248775U CN 221101383 U CN221101383 U CN 221101383U
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- 238000004891 communication Methods 0.000 claims abstract description 58
- 238000007726 management method Methods 0.000 claims description 72
- 241000209507 Camellia Species 0.000 claims description 28
- 235000018597 common camellia Nutrition 0.000 claims description 28
- 230000005540 biological transmission Effects 0.000 claims description 23
- LRFDUPNLCDXZOE-UHFFFAOYSA-N camellianin b Chemical compound OC1C(O)C(O)C(C)OC1OC1C(O)C(O)C(OC=2C=3C(=O)C=C(OC=3C=C(O)C=2)C=2C=CC(O)=CC=2)OC1CO LRFDUPNLCDXZOE-UHFFFAOYSA-N 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000013500 data storage Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000036039 immunity Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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Abstract
The Camellink signal simulator of the USB interface comprises: SD card interface, SD card communication chip, ethernet interface, ethernet communication chip, USB interface, USB communication chip, +12V input interface, nonvolatile flash memory, field programmable logic device, power management module, high-speed dynamic random access memory, TTL IO chip, differential IO chip, camellia_Base driver, camellia_Medium driver, camellia_full driver, base high-precision clock management, full high-precision clock management, and connector.
Description
Technical Field
The utility model relates to the fields of industrial control, high-end manufacturing and the like, in particular to a Camellia signal simulator with a USB interface.
Background
The Camelline standard is a communication interface developed based on video application, the standard itself is developed from CHANNELLINK technology, and a matched standard industrial interface device is defined, so that the signal transmission of a camera and an image acquisition card is simplified. The Camellia link has the characteristics of high transmission rate, good noise immunity, reliable transmission capacity and the like, and has high communication efficiency and unified communication protocol standard. Has been applied to the fields of industrial control, high-end manufacturing and the like.
With the development of image acquisition card technology, different modes are input into the acquisition card, and part of cameras can only support one mode output. Therefore, it is necessary to develop a Cameralink signal emulator that supports multiple mode outputs simultaneously. However, at present, no chip capable of supporting multiple mode output is available, and few products of the Camellia link signal simulator capable of supporting multiple mode output are available at home. Therefore, the research and development of the Camelline signal simulator product supporting the output of multiple modes simultaneously has great significance.
Disclosure of Invention
In order to solve the requirements of the current industrial control and high-end manufacturing equipment on a Camellia signal simulator and meet the development requirements of an industrial manufacturing system, the utility model provides the Camellia signal simulator with a USB interface, which adopts a discrete circuit to realize the communication electrical standard of the Camellia, is designed as the USB interface, and can be applied to all industrial computers based on the USB protocol for use.
The Camellink signal simulator of the USB interface comprises: SD card interface, SD card communication chip, ethernet interface, ethernet communication chip, USB interface, USB communication chip, +12V input interface, nonvolatile flash memory, field programmable logic device, power management module, high-speed dynamic random access memory, TTL IO chip, differential IO chip, camellia_Base driver, camellia_Medium driver, camellia_full driver, base high-precision clock management, full high-precision clock management, and connector.
The SD card interface is connected with the SD card communication chip to realize information reading of the SD card.
The SD card communication chip is connected with the SD card interface, the field programmable logic device and the power management module, so that information transmission between the SD card and the field programmable logic device is realized.
And the Ethernet interface is connected with the Ethernet communication chip to realize information reading and conversion of the Ethernet.
And the Ethernet communication chip is connected with the Ethernet interface, the field programmable logic device and the power management module and is used for realizing information transmission between the Ethernet and the field programmable logic device.
The USB interface is connected with the USB communication chip and is used for reading and converting USB information.
And the USB communication chip is connected with the USB interface, the field programmable logic device and the power management module and is used for realizing information transmission between the USB and the field programmable logic device.
And the +12V input interface is connected with the power management module to realize the external power input of the Camellia signal simulator of the USB interface.
And the nonvolatile flash memory is connected with the field programmable logic device and the power management module and is used for data storage.
The field programmable logic device is connected with the SD card communication chip, the Ethernet communication chip, the USB communication chip, the nonvolatile flash memory, the power management module, the high-speed dynamic random access memory, the TTL IO chip, the differential IO chip, the Camellia_Base driver, the Camellia_Medium driver, the Camellia_full driver, the Base high-precision clock management and the Full high-precision clock management, and achieves overall control.
The power management module is connected with the SD card communication chip, the Ethernet communication chip, the USB communication chip, +12V input interface, the nonvolatile flash memory, the field programmable logic device, the high-speed dynamic random access memory, the TTL IO chip, the differential IO chip, the Camellia link_Base driver, the Camellia link_Medium driver, the Camellia link_full driver, the Base high-precision clock management and the Full high-precision clock management and is used for providing required voltage for the Camellia link signal simulator of the USB interface.
The high-speed dynamic random access memory is connected with the field programmable logic device and the power management module and is used for realizing the cache of the output information of the Cameralink signal simulator.
And the TTL IO chip is connected with the field programmable logic device, the power management module and the connector to realize the input and output of TTL level.
The differential IO chip is connected with the field programmable logic device, the power management module and the connector, and realizes the input and output of differential signals.
And the Camelline_Base driver is connected with the field programmable logic device, the power management module and the connector to realize the signal output of the Camelline protocol.
And the Camellin_Medium driver is connected with the field programmable logic device, the power management module and the connector to realize the signal output of the Camellin protocol.
And the Camellin_full driver is connected with the field programmable logic device, the power management module and the connector to realize the signal output of the Camellin protocol.
And the Base high-precision clock management is connected with the field programmable logic device and the power management module to realize high-precision clock signal output.
And Full high-precision clock management is connected with the field programmable logic device and the power management module to realize high-precision clock signal output.
And the connector is connected with the TTL IO chip, the differential IO chip, the Camellia link_Base driver, the Camellia link_Medium driver and the Camellia link_full driver and is used for outputting the Camellia link signals, the TTL levels and the differential signals to the outside by the Camellia link signal simulator of the USB interface.
The beneficial effects of the utility model are as follows: the camera link signal simulator of the USB interface is designed as the USB interface, and the simulator supports the camera link surface scanning and line scanning camera image output simulating two Base, one Medium, one Full mode or one 80bit mode. The simulator adopts a discrete circuit to realize the communication electrical standard of the Cameralink. The simulator adopts FPGA as a core processing device, and runs an independently developed image simulation IP core. The USB interface is connected with the FPGA through the USB communication chip, and data transmission with large data volume is performed in a FIFO mode, so that the processing capacity of the message and the data transmission bandwidth of the host interface are improved. On-board two 4GB DDR3 SDRAM is used for caching image information. Meanwhile, the product also provides continuous single-frame transmission, sequence transmission, cyclic sequence transmission, and transmission frame interval settable functions, supports output image resolution settable, supports 7 paths of TTL/differential input and output functions, supports SD card storage and output functions, and supports Ethernet interface communication. The performance and function of the product can meet the requirements of the current industrial manufacturing system.
The technical scheme of the utility model is further described in detail through the drawings and the embodiments.
Drawings
Fig. 1 is a block diagram of a camera link signal simulator of a USB interface according to the present utility model.
Description of the embodiments
As shown in FIG. 1, the structural block diagram of the Camelline signal emulator of the USB interface is provided by the utility model. The Camellink signal simulator of the USB interface comprises: the SD card interface 1, the SD card communication chip 2, the Ethernet interface 3, the Ethernet communication chip 4, the USB interface 5, the USB communication chip 6, +12V input interface 7, the nonvolatile flash memory 8, the field programmable logic device 9, the power management module 10, the high-speed dynamic random access memory 11, the TTL IO chip 12, the differential IO chip 13, the camera link_Base driver 14, the camera link_Medium driver 15, the camera link_full driver 16, the Base high-precision clock management 17, the Full high-precision clock management 18 and the connector 19.
The SD card interface 1 is connected with the SD card communication chip 2 to realize information reading of the SD card.
The SD card communication chip 2 is connected with the SD card interface 1, the field programmable logic device 9 and the power management module 10, so that information transmission between the SD card and the field programmable logic device 9 is realized.
The Ethernet interface 3 is connected with the Ethernet communication chip 4 to realize information reading and conversion of the Ethernet.
The Ethernet communication chip 4 is connected with the Ethernet interface 3, the field programmable logic device 9 and the power management module 10, and realizes information transmission between the Ethernet and the field programmable logic device 9.
And the USB interface 5 is connected with the USB communication chip 6 to realize information reading and conversion of the USB.
The USB communication chip 6 is connected with the USB interface 5, the field programmable logic device 9 and the power management module 10, and realizes information transmission between the USB and the field programmable logic device 9.
The +12V input interface 7 is connected with the power management module 10 to realize the external power input of the Camelline signal simulator of the USB interface.
A nonvolatile flash memory 8, which is connected with a field programmable logic device 9 and a power management module 10 for data storage.
The field programmable logic device 9 is connected with the SD card communication chip 2, the Ethernet communication chip 4, the USB communication chip 6, the nonvolatile flash memory 8, the power management module 10, the high-speed dynamic random access memory 11, the TTL IO chip 12, the differential IO chip 13, the Cameralink_Base driver 14, the Cameralink_Medium driver 15, the Cameralink_Full driver 16, the Base high-precision clock management 17 and the Full high-precision clock management 18, and achieves overall control.
The power management module 10 is connected with the SD card communication chip 2, the Ethernet communication chip 4, the USB communication chip 6, +12V input interface 7, the nonvolatile flash memory 8, the field programmable logic device 9, the high-speed dynamic random access memory 11, the TTL IO chip 12, the differential IO chip 13, the Camellink_Base driver 14, the Camellin_Medium driver 15, the Camellin_full driver 16, the Base high-precision clock management 17 and the Full high-precision clock management 18, and is used for providing required voltages for a Camellin signal simulator of the USB interface.
The high-speed dynamic random access memory 11 is connected with the field programmable logic device 9 and the power management module 10 and is used for realizing the cache of the output information of the Cameralink signal simulator.
The TTL IO chip 12 is connected with the field programmable logic device 9, the power management module 10 and the connector 19, and realizes the input and output of TTL level.
The differential IO chip 13 is connected with the field programmable logic device 9, the power management module 10 and the connector 19, and realizes the input and output of differential signals.
The camera link_base driver 14 is connected with the field programmable logic device 9, the power management module 10 and the connector 19, and realizes the output of a camera link protocol signal.
The camera link_medium driver 15 is connected with the field programmable logic device 9, the power management module 10 and the connector 19, and realizes the signal output of the camera link protocol.
And the Camellink_full driver 16 is connected with the field programmable logic device 9, the power management module 10 and the connector 19 to realize the Camellink protocol signal output.
And the Base high-precision clock management 17 is connected with the field programmable logic device 9 and the power management module 10 to realize high-precision clock signal output.
And the Full high-precision clock management 18 is connected with the field programmable logic device 9 and the power management module 10 to realize high-precision clock signal output.
And a connector 19 for connecting the TTL IO chip 12, the differential IO chip 13, the Camellia_Base driver 14, the Camellia_Medium driver 15 and the Camellia_Full driver 16, and outputting the Camellia signal, the TTL level and the differential signal to the outside by the Camellia signal simulator of the USB interface.
The beneficial effects of the utility model are as follows: the camera link signal simulator of the USB interface is designed as the USB interface, and the simulator supports the camera link surface scanning and line scanning camera image output simulating two Base, one Medium, one Full mode or one 80bit mode. The simulator adopts a discrete circuit to realize the communication electrical standard of the Cameralink. The simulator adopts FPGA as a core processing device, and runs an independently developed image simulation IP core. The USB interface is connected with the FPGA through the USB communication chip, and data transmission with large data volume is performed in a FIFO mode, so that the processing capacity of the message and the data transmission bandwidth of the host interface are improved. On-board two 4GB DDR3 SDRAM is used for caching image information. Meanwhile, the product also provides continuous single-frame transmission, sequence transmission, cyclic sequence transmission, and transmission frame interval settable functions, supports output image resolution settable, supports 7 paths of TTL/differential input and output functions, supports SD card storage and output functions, and supports Ethernet interface communication. The performance and function of the simulator can meet the requirements of the current industrial manufacturing system.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model and not for limiting it, and although the present utility model has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that: the technical scheme of the utility model can be modified or replaced by the same, and the modified technical scheme cannot deviate from the spirit and scope of the technical scheme of the utility model.
Claims (1)
1. A Camellink signal simulator of a USB interface is characterized in that:
The Camellink signal simulator of the USB interface comprises: SD card interface, SD card communication chip, ethernet interface, ethernet communication chip, USB interface, USB communication chip, +12V input interface, nonvolatile flash memory, field programmable logic device, power management module, high-speed dynamic random access memory, TTL IO chip, differential IO chip, camellia_Base driver, camellia_Medium driver, camellia_full driver, base high-precision clock management, full high-precision clock management, and connector;
the SD card interface is connected with the SD card communication chip to realize information reading of the SD card;
The SD card communication chip is connected with the SD card interface, the field programmable logic device and the power management module, so that information transmission between the SD card and the field programmable logic device is realized;
the Ethernet interface is connected with the Ethernet communication chip to realize information reading and conversion of the Ethernet;
the Ethernet communication chip is connected with the Ethernet interface, the field programmable logic device and the power management module, and realizes information transmission between the Ethernet and the field programmable logic device;
The USB interface is connected with the USB communication chip and is used for reading and converting USB information;
The USB communication chip is connected with the USB interface, the field programmable logic device and the power management module, and information transmission between the USB and the field programmable logic device is realized;
The +12V input interface is connected with the power management module to realize the external power input of the Camellia signal simulator of the USB interface;
the nonvolatile flash memory is connected with the field programmable logic device and the power management module and is used for data storage;
The field programmable logic device is connected with the SD card communication chip, the Ethernet communication chip, the USB communication chip, the nonvolatile flash memory, the power management module, the high-speed dynamic random access memory, the TTL IO chip, the differential IO chip, the Camellia_Base driver, the Camellia_Medium driver, the Camellia_full driver, the Base high-precision clock management and the Full high-precision clock management to realize overall control;
The power management module is connected with the SD card communication chip, the Ethernet communication chip, the USB communication chip, +12V input interface, the nonvolatile flash memory, the field programmable logic device, the high-speed dynamic random access memory, the TTL IO chip, the differential IO chip, the Camellia link_Base driver, the Camellia link_Medium driver, the Camellia link_full driver, the Base high-precision clock management and the Full high-precision clock management and is used for providing required voltage for a Camellia link signal simulator of the USB interface;
The high-speed dynamic random access memory is connected with the field programmable logic device and the power management module and is used for realizing the cache of the output information of the Cameralink signal simulator;
the TTL IO chip is connected with the field programmable logic device, the power management module and the connector, and is used for realizing the input and output of TTL level;
The differential IO chip is connected with the field programmable logic device, the power management module and the connector, and realizes the input and output of differential signals;
The Camelline_Base driver is connected with the field programmable logic device, the power management module and the connector to realize the signal output of a Camelline protocol;
The Camellin_Medium driver is connected with the field programmable logic device, the power management module and the connector to realize the signal output of the Camellin protocol;
The Camellin_full driver is connected with the field programmable logic device, the power management module and the connector to realize the signal output of a Camellin protocol;
base high-precision clock management is connected with the field programmable logic device and the power management module to realize high-precision clock signal output;
The Full high-precision clock management is connected with the field programmable logic device and the power management module to realize high-precision clock signal output;
And the connector is connected with the TTL IO chip, the differential IO chip, the Camellia link_Base driver, the Camellia link_Medium driver and the Camellia link_full driver and is used for outputting the Camellia link signals, the TTL levels and the differential signals to the outside by the Camellia link signal simulator of the USB interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323248775.4U CN221101383U (en) | 2023-11-30 | 2023-11-30 | Camellink signal simulator with USB interface |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323248775.4U CN221101383U (en) | 2023-11-30 | 2023-11-30 | Camellink signal simulator with USB interface |
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| Publication Number | Publication Date |
|---|---|
| CN221101383U true CN221101383U (en) | 2024-06-07 |
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| CN202323248775.4U Active CN221101383U (en) | 2023-11-30 | 2023-11-30 | Camellink signal simulator with USB interface |
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- 2023-11-30 CN CN202323248775.4U patent/CN221101383U/en active Active
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