CN111640787A - LDMOS device with multiple grooves - Google Patents
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- CN111640787A CN111640787A CN202010535896.9A CN202010535896A CN111640787A CN 111640787 A CN111640787 A CN 111640787A CN 202010535896 A CN202010535896 A CN 202010535896A CN 111640787 A CN111640787 A CN 111640787A
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- 238000004519 manufacturing process Methods 0.000 claims 1
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
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Abstract
The invention relates to an LDMOS device with multiple grooves, and belongs to the technical field of power semiconductors. According to the LDMOS device with the multiple grooves, the appearance of the second conduction type diffusion region is changed through groove etching, uniformly distributed doping is achieved, so that the electric field distribution of the surface is optimized, the area of the drift region is reduced, in addition, the appearance of junctions on two sides is improved, the reverse blocking voltage of the device is improved, and meanwhile, the on-resistance can be improved.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to an LDMOS device with multiple grooves.
Background
LDMOS transistors are one of the most widely used devices in smart power integrated circuits. In many power devices, LDMOS is used as a core device of a power integrated circuit, and has many advantages such as simple design, easy integration, and excellent frequency and switching characteristics, which have become research objects of many scholars at home and abroad. However, the severe contradiction between the breakdown voltage and the specific on-resistance in the lateral high-voltage power device has been limiting the application of LDMOS at high voltage and large current. Therefore, designing the LDMOS capable of meeting certain voltage withstanding requirements and having a low on-resistance is an important development direction of the current power semiconductor technology.
The traditional LDMOS device is a multi-sub-type device, so that the silicon limit problem of mutual restriction between breakdown voltage and on-resistance also exists. To solve this problem, new technologies such as RESURF technology, super junction LDMOS, and the like are proposed. Taking RESURF technology as an example, as shown in fig. 1: the essence of the RESURF technology is that the surface electric field after the drift region is fully depleted is reduced and optimized through the interaction of electric fields in the N-type depletion layer and the P-type depletion layer, namely through charge sharing, the breakdown point is moved from the surface to the inside of the device, and the withstand voltage of the device is improved. Meanwhile, the RESURF structure enables the concentration of an active region to be increased under the same breakdown voltage, and the on-resistance to be reduced, so that good compromise between the breakdown voltage and the on-resistance is achieved. However, although the RESURF structure can ensure that the device has higher withstand voltage and improve the compromise relationship between the withstand voltage and the on-resistance of the device, the area occupied by the RESURF structure is too large, so that the whole device area is larger, the original RESURF region is relatively unevenly doped, and the distribution of the transverse electric field lines of the original drift region is difficult to approach the ideal trapezoidal distribution, thereby reducing the breakdown voltage of the device and influencing the performance of the device.
Disclosure of Invention
The invention provides an LDMOS device with multiple trenches, aiming at solving the problems in the prior art.
In order to solve the above technical problem, an embodiment of the present invention provides an LDMOS device with multiple trenches, which includes a second conductive type substrate, a first conductive type drift region, a second conductive type body region, a highly doped second conductive type body contact region, a first conductive type source region, a first conductive type drain region, a dielectric layer, a source, a planar gate structure and a drain;
the first conductive type drift region is located on the second conductive type substrate; the second conductive type body region is located in the first conductive type drift region and on the second conductive type substrate; the side surfaces of the highly doped second conductive type body contact region and the first conductive type source region are mutually contacted and are positioned on one side, away from the first conductive type drift region, of the top layer of the second conductive type body region; the first conduction type drain region is positioned on one side, far away from the second conduction type body region, of the top layer of the first conduction type drift region;
the source electrode is positioned on the highly doped second conductivity type body contact region and the first portion of the first conductivity type source region; the planar gate structure is located on a second part of the first conductive type source region, the second conductive type body region and a part of the first conductive type drift region; the drain electrode is positioned on the first conduction type drain region;
the dielectric layer is positioned on the first conduction type drift region among the source electrode, the planar gate structure and the drain electrode;
the semiconductor device further comprises a second conductive type polycrystalline silicon groove region and a second conductive type diffusion region, wherein the second conductive type diffusion region is located in the first conductive type drift region and located between the second conductive type body region and the first conductive type drain region, the second conductive type polycrystalline silicon groove regions are located on the top layer of the second conductive type diffusion region at intervals, and the second conductive type diffusion region is formed by diffusion of the second conductive type polycrystalline silicon groove regions.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the planar gate structure comprises the gate oxide layer and a polysilicon gate electrode positioned on the gate oxide layer.
Further, the dielectric layer is silicon dioxide.
Further, the second conductive-type diffusion region is located inside or at a top layer of the first conductive-type drift region.
Furthermore, in the preparation process, the transverse width, the longitudinal length, the interval or the number of the grooves of the second conductive type polycrystalline silicon groove regions are adjusted by changing a photolithography mask.
Further, the first conductive type is an N type, and the second conductive type is a P type.
Further, the first conductive type is a P type, and the second conductive type is an N type.
The invention has the beneficial effects that: according to the LDMOS device with the multiple grooves, the appearance of the second conduction type diffusion region is changed through groove etching, uniformly distributed doping is achieved, so that the electric field distribution of the surface is optimized, the area of the drift region is reduced, in addition, the appearance of junctions on two sides is improved, the reverse blocking voltage of the device is improved, and meanwhile, the on-resistance can be improved.
Drawings
FIG. 1 is a schematic diagram of a conventional LDMOS structure;
FIG. 2 is a schematic diagram of a first structure of an LDMOS device having multiple trenches according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a second structure of an LDMOS device having multiple trenches according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a third structure of an LDMOS device with multiple trenches according to an embodiment of the invention.
In the drawings, the components represented by the respective reference numerals are listed below:
201. a second conductive type substrate, 202, a first conductive type drift region, 203, a second conductive type body region, 204, a highly doped second conductive type body contact region, 205, a first conductive type source region, 206, a first conductive type drain region, 207, a gate oxide layer, 208, a dielectric layer, 209, a source, 210, a polysilicon gate electrode, 211, a drain, 212, a second conductive type polysilicon trench region, 213, a second conductive type diffusion region, 301-1 to 301-N are the transverse width of each trench of the plurality of second conductive type polysilicon trench regions, 302-1 to 302-N-1 are the spacing between adjacent trenches in the plurality of second conductive type polysilicon trench regions, 401-1 to 401-N are the longitudinal length of each trench of the plurality of second conductive type polysilicon trench regions, wherein N is a positive integer.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 2, a first embodiment of the present invention provides an LDMOS device with multiple trenches, which includes a second conductive type substrate 201, a first conductive type drift region 202, a second conductive type body region 203, a highly doped second conductive type body contact region 204, a first conductive type source region 205, a first conductive type drain region 206, a dielectric layer 208, a source 209, a planar gate structure and a drain 211;
the first conductive-type drift region 202 is located on the second conductive-type substrate 201; the second conductive-type body region 203 is located in the first conductive-type drift region 202 and on the second conductive-type substrate 201; the top layer of the second conductive type body region 203, which is laterally contacted with the highly doped second conductive type body contact region 204 and the first conductive type source region 205, is located at a side far away from the first conductive type drift region 202; the first conductive-type drain region 206 is located on a side of the top layer of the first conductive-type drift region 202 away from the second conductive-type body region 203;
the source 209 is located on a first portion of the highly doped second conductivity type body contact region 204 and first conductivity type source region 205; the planar gate structure is located on a second portion of the first conductive-type source region 205, the second conductive-type body region 203, and a portion of the first conductive-type drift region 202; the drain electrode 211 is positioned on the first conductive type drain region 206;
the dielectric layer 208 is positioned on the first conductive type drift region 202 between the source electrode 209, the planar gate structure and the drain electrode 211;
the semiconductor device further comprises a second conductive type polysilicon trench region 212 and a second conductive type diffusion region 213, wherein the second conductive type diffusion region 213 is located in the first conductive type drift region 202 and between the second conductive type body region 203 and the first conductive type drain region 206, a plurality of the second conductive type polysilicon trench regions 212 are spaced from each other and located on the top layer of the second conductive type diffusion region 213, and the second conductive type diffusion region 213 is formed by diffusing the second conductive type polysilicon trench regions 212.
In the above embodiments, the first conductive type may be an N type, and the second conductive type may be a P type. The second conductive type polysilicon trench region 212 is formed by etching a trench, and the trench is filled with second conductive type polysilicon, preferably, the longitudinal lengths of the plurality of second conductive type polysilicon trench regions 212 are the same, and the distances between adjacent trenches in the plurality of second conductive type polysilicon trench regions 212 are the same;
the second conductive-type diffusion region 213 is preferably formed by high-temperature annealing diffusion of the second conductive-type polysilicon trench region 212.
Taking an N-type LDMOS as an example, the working principle of the invention is illustrated:
the invention provides an LDMOS device with multiple grooves, wherein a plurality of grooves are formed on the surface of an N-type drift region 202 through etching, P-type polycrystalline silicon is filled in the grooves to form a P-type polycrystalline silicon groove region 212, then a P-type diffusion region 213 is formed through annealing, a PN junction is respectively formed between the left end and the right end of the P-type diffusion region 213 and the N-type drift region 202, and thus the PN junctions at the two ends are respectively formed, the P-type body region 203 and the N-type drift region 202 are depleted, and the lateral electric potential distribution and the lateral electric field distribution of the device are changed under the combined action of the P-type diffusion region 213 and the N-type drift region 202.
The electrode connection mode when the reverse blocking is carried out is as follows: the drain 211 is connected to a high potential and the source 209 and polysilicon gate electrode 210 are connected to a low potential. When the device is subjected to reverse voltage withstanding, the mutual depletion region of the PN junction can enable the surface electric field of the device to be rapidly reduced, so that the surface electric field distribution is more uniform. Because the P-type polycrystalline silicon is deposited in the groove, the doping effect is uniformly distributed, the appearance of the junctions on two sides is improved, the breakdown voltage is improved, the whole area of the device can be reduced, and the on-resistance of the whole device is improved.
Optionally, as shown in fig. 2, the planar gate structure includes the gate oxide layer 207 and a polysilicon gate electrode 210 thereon.
Optionally, the dielectric layer 208 is silicon dioxide.
Alternatively, the second conductive-type diffusion region 213 is located at an inner portion or a top layer of the first conductive-type drift region 202.
Alternatively, as shown in fig. 3 to 4, during the preparation process, the lateral width, the longitudinal length, the pitch, or the number of trenches of the second conductivity type polysilicon trench regions 212 may be adjusted by changing photolithography.
In the above embodiments, a person skilled in the art can adjust the lateral width, the longitudinal length, the pitch, or the number of trenches of the plurality of second conductivity type polysilicon trench regions 212 according to actual needs.
Optionally, the first conductivity type is an N-type, and the second conductivity type is a P-type.
Optionally, the first conductivity type is a P type, and the second conductivity type is an N type.
According to the LDMOS device with the multiple grooves, the appearance of the second conduction type diffusion region is changed through groove etching, uniformly distributed doping is achieved, so that the electric field distribution of the surface is optimized, the area of the drift region is reduced, in addition, the appearance of junctions on two sides is improved, the reverse blocking voltage of the device is improved, and meanwhile, the on-resistance can be improved.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (7)
1. An LDMOS device with multiple grooves comprises a second conduction type substrate (201), a first conduction type drift region (202), a second conduction type body region (203), a highly-doped second conduction type body contact region (204), a first conduction type source region (205), a first conduction type drain region (206), a dielectric layer (208), a source electrode (209), a planar gate structure and a drain electrode (211);
the first conductivity type drift region (202) is located on the second conductivity type substrate (201); the second conductivity type body region (203) is located in the first conductivity type drift region (202) and on the second conductivity type substrate (201); the top layer of the second conduction type body region (203), which is in mutual contact with the side surface of the first conduction type source region (205), is positioned on the side, away from the first conduction type drift region (202), of the highly doped second conduction type body contact region (204); the first conductivity type drain region (206) is located on a side of the top layer of the first conductivity type drift region (202) away from the second conductivity type body region (203);
the source (209) is located on a first portion of the highly doped second conductivity type body contact region (204) and first conductivity type source region (205); the planar gate structure is located on a second portion of the first conductivity type source region (205), the second conductivity type body region (203), and a portion of the first conductivity type drift region (202); the drain electrode (211) is positioned on the first conductive type drain region (206);
the dielectric layer (208) is positioned on the first conduction type drift region (202) among the source electrode (209), the planar gate structure and the drain electrode (211);
the transistor is characterized by further comprising a second conductive type polycrystalline silicon trench region (212) and a second conductive type diffusion region (213), wherein the second conductive type diffusion region (213) is located in the first conductive type drift region (202) and located between the second conductive type body region (203) and the first conductive type drain region (206), a plurality of second conductive type polycrystalline silicon trench regions (212) are located at the top layer of the second conductive type diffusion region (213) in an interval mode, and the second conductive type diffusion region (213) is formed by diffusion of the second conductive type polycrystalline silicon trench regions (212).
2. An LDMOS device having multiple trenches as claimed in claim 1 wherein said planar gate structure comprises said gate oxide layer (207) and a polysilicon gate electrode (210) located thereon.
3. The LDMOS device having the multiple trenches of claim 1, wherein the dielectric layer (208) is silicon dioxide.
4. An LDMOS device having a multi-trench as claimed in any of claims 1-3, characterized in that the second conductivity type diffusion region (213) is located inside or on top of the first conductivity type drift region (202).
5. An LDMOS device having multiple trenches as claimed in any of claims 1-3 wherein the lateral width, longitudinal length, pitch or number of trenches of the multiple second conductivity type polysilicon trench regions (212) is adjusted by changing photolithography during the fabrication process.
6. An LDMOS device having multiple trenches as claimed in any of claims 1-3 wherein the first conductivity type is N-type and the second conductivity type is P-type.
7. An LDMOS device having multiple trenches as claimed in any of claims 1-3 wherein the first conductivity type is P-type and the second conductivity type is N-type.
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| CN202010535896.9A CN111640787B (en) | 2020-06-12 | 2020-06-12 | LDMOS device with multiple grooves |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023284481A1 (en) * | 2021-07-16 | 2023-01-19 | 无锡华润上华科技有限公司 | Body gate laterally double-diffused metal-oxide semiconductor field effect transistor and method for preparing same |
| CN117711939A (en) * | 2024-02-05 | 2024-03-15 | 深圳腾睿微电子科技有限公司 | Groove type terminal IGBT device and manufacturing method thereof |
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|---|---|---|---|---|
| WO2023284481A1 (en) * | 2021-07-16 | 2023-01-19 | 无锡华润上华科技有限公司 | Body gate laterally double-diffused metal-oxide semiconductor field effect transistor and method for preparing same |
| CN117711939A (en) * | 2024-02-05 | 2024-03-15 | 深圳腾睿微电子科技有限公司 | Groove type terminal IGBT device and manufacturing method thereof |
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