CN117133799A - Insulated bipolar transistor with multiple potentials and manufacturing method thereof - Google Patents
Insulated bipolar transistor with multiple potentials and manufacturing method thereof Download PDFInfo
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- CN117133799A CN117133799A CN202311382398.5A CN202311382398A CN117133799A CN 117133799 A CN117133799 A CN 117133799A CN 202311382398 A CN202311382398 A CN 202311382398A CN 117133799 A CN117133799 A CN 117133799A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The application relates to the technical field of semiconductor devices, in particular to an insulated bipolar transistor with multiple potential and a manufacturing method thereof. The insulated bipolar transistor with multiple potentials comprises the following components in each cell: a cell region located on the first main surface of the first conductivity type drift region and a terminal region located on the outer periphery of the cell region and surrounding the cell region; the cellular region comprises: a cell adjacent to the poly potential in the trench being a gate potential and a cell adjacent to the poly potential in the trench being an arbitrary potential. The insulated bipolar transistor can reduce and adjust the input capacitance and the current density.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to an insulated bipolar transistor with multiple potential and a manufacturing method thereof.
Background
The IGBT device is a composite fully controlled voltage driven power semiconductor device composed of a BJT (Bipolar Junction Transistor, bipolar transistor) and a MOS (Metal Oxide Semiconductor, insulated gate field effect transistor). In practical application, the IGBT device has the advantages of both high input impedance of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and low on-voltage drop of GTR (Giant Transistor), and is widely used in chopper or inverter circuits, such as rail transit, electric vehicles, wind power and photovoltaic power generation, and household appliances. With the continuous improvement and development of the IGBT device, the structure of the IGBT is not limited to the classical trench type, but structures such as the trench bottom P-type injection with the CS layer and the IEGT type are generated successively, but the cell structure inside the IGBT device is designed to be smaller and smaller with the development of the IGBT device. However, the existing cell structure can cause the increase of the input capacitance and the increase of the on-state current density of the IGBT device due to the overlarge cell density, thereby causing the mismatch with a driving circuit and even causing the heat concentration failure of the device.
Disclosure of Invention
In order to solve at least one of the problems in the prior art, an object of the present application is to provide an insulated bipolar transistor with a poly potential and a method for manufacturing the same, which adjusts the structure of a cell, so that the input capacitance and current density of the device are reduced and adjustable.
In order to achieve the above object, the present application provides an insulated bipolar transistor of a poly potential, comprising a cell region located on a first main surface of a drift region of a first conductivity type and a terminal region located on an outer periphery of the cell region and surrounding the cell region; the cellular region comprises: a cell adjacent to the poly potential in the trench being a gate potential and a cell adjacent to the poly potential in the trench being an arbitrary potential.
Further, the cell adjacent to the gate potential in the trench comprises a second conductive type base region, a first conductive type carrier storage layer and a second conductive type ohmic contact region are arranged in the second conductive type base region, the first conductive type carrier storage layer is connected with the trench, the second conductive type ohmic contact region and the first conductive type carrier storage layer are connected with source metal through a metal hole, and the second conductive type ohmic contact region is located at the lower end of the metal hole or coats the metal hole.
Further, the cell adjacent to the poly potential in the trench to be any potential comprises a base region of the second conductivity type.
Further, the cell with the random potential of the poly potential in the adjacent groove comprises a second type base region and a second conduction type ohmic contact region, the second conduction type ohmic contact region is connected with the source electrode metal through a metal hole, and the second conduction type ohmic contact region is positioned at the lower end of the metal hole or is coated on the metal hole.
Further, floating regions of the first conductivity type covering the trenches are arranged below the trenches.
Further, an oxide layer grows on the inner wall of the groove, and conductive polysilicon is deposited in the groove.
Further, the second main surface of the first conductivity type drift region is stacked with the first conductivity type cut-off layer, the second conductivity type collector and the collector metal in this order.
Further, the terminal area includes:
and the transition region is positioned outside the cell region and comprises a second conductive type well, a poly field plate and a gate metal, and the poly field plate is connected with the second conductive type well and the gate metal.
Further, the terminal area further includes:
the field limiting ring field plate structure surrounds the transition region, and comprises a second conductive type field limiting ring, a poly field plate and a metal field plate, wherein the metal field plate is connected with the second conductive type field limiting ring and the poly field plate.
Further, the terminal area further includes:
and the cut-off ring region is positioned on the outer side of the field limiting ring field plate structure and comprises a first conductive type carrier storage layer and drain metal connected with the first conductive type carrier storage layer.
To achieve the above object, the present application also provides a method for manufacturing an insulated bipolar transistor having a poly potential, the method comprising:
providing a first conductive type drift layer, depositing a hard mask and photoresist on a first main surface of the first conductive type drift layer, and etching the hard mask;
growing a field oxide layer with a mask layer, removing the hard mask layer, photoetching a second conductivity type impurity injection region, injecting second conductivity type impurities, annealing to diffuse the impurities, and forming a second conductivity type field limiting ring and a second conductivity type well of the transition region;
depositing a hard mask, etching the hard mask to form a pattern required by etching the groove, and etching the groove under the shielding of the hard mask;
injecting first conductivity type impurities into the bottom of the groove by using a hard mask, pushing the groove to form a first conductivity type floating region coating the bottom of the groove, and removing the hard mask;
growing an oxide layer in the groove, and then depositing and etching polysilicon among the grooves, the transition region and the second conductivity type field limiting ring to form a groove and a poly field plate, wherein the groove comprises conductive polysilicon and has a flat surface;
injecting second conductivity type impurities into the positions corresponding to the cells, and forming a second conductivity type base region by a push well;
injecting first conductivity type impurities into the second conductivity type base region and the cut-off ring region at the first preset position, and pushing the well to form a first conductivity type carrier storage layer;
depositing an insulating layer on the first main surface, photoetching the insulating layer to form a pattern required by a metal hole, etching the metal hole to a depth required by the metal hole under the shielding of the insulating layer, injecting second conductivity type impurities into a second conductivity type base region at a second preset position, and forming a second conductivity type ohmic contact region after well pushing;
depositing a metal layer on the first main surface and photoetching to form a gate metal, a source metal, a metal field plate and a drain metal;
and injecting a first conductive type impurity push well on the second main surface of the first conductive type drift layer to form a first conductive type cut-off region, injecting a second conductive type impurity push well to form a second conductive type collector, and depositing metal to form a collector metal.
Regarding the "first conductivity type" and the "second conductivity type", for an N-type power IGBT device, the first conductivity type refers to an N-type, and the second conductivity type is a P-type; for a P-type power IGBT device, the first conductivity type and the second conductivity type refer to the type that is the opposite of an N-type semiconductor device.
The application provides an insulated bipolar transistor with multiple potentials, which is characterized in that three different cell structures are designed: the proportion and the size of the device Cge, cgc, cce are regulated and controlled by adjusting the position and the proportion of the poly potential, so that the problem that the input capacitance of the device is overlarge or is not matched with a driving circuit is solved.
The power density of the bipolar transistor is adjusted by adjusting the proportion of different cell structures, so that the internal heat distribution of the device can be adjusted, and the occurrence of a heat concentration area and a power density shortage area is avoided.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the embodiments of the application, and do not limit the application. In the drawings:
FIG. 1 is a schematic diagram of a conventional IGBT;
FIG. 2 is a schematic diagram of an insulated bipolar transistor with multiple potentials according to an embodiment of the present application;
FIGS. 3-10 are schematic views illustrating the steps of a method for fabricating a bipolar transistor with multiple potential isolation according to an embodiment of the present application;
description of the drawings: 100-N-drift region, 200-cell region, 300-terminal region, 101-P-well, 102-field oxide layer, 103-P-field stop ring, 104-trench, 105-N+ floating region, 106-poly field plate, 107-conductive polysilicon, 108-oxide layer, 109-P-base region, 110-insulating layer, 111-N+ carrier storage layer, 112-P+ ohmic contact region, 113-drain metal, 114-source metal, 115-gate metal, 116-metal field plate, 117-N+ stop layer, 118-P+ collector, 119-collector metal, 210-first type cell, 220-second type cell, 230-third type cell, 310-transition region, 320-field stop ring field plate structure, 330-stop ring region.
Detailed Description
For a better understanding and explanation of the present application, reference will be made to the following detailed description of the application taken in conjunction with the accompanying drawings. The application is not limited to these specific embodiments only. On the contrary, the application is intended to cover modifications and equivalent arrangements included within the scope of the appended claims.
It should be noted that in the following detailed description, numerous specific details are set forth. It will be understood by those skilled in the art that the present application may be practiced without these specific details. In the following description of various embodiments, well-known principles, structures and components are not described in detail in order to facilitate a salient point of the application.
Example 1
Fig. 1 is a schematic diagram of a prior art IGBT structure, including an initial classical trench structure, and new modified and designed CS layer, trench bottom P-type implanted, IEGT type, etc. structures for reducing Vcesat and improving switching characteristics.
However, with the continuous development of the IGBT device, the cell structure inside the IGBT device is designed to be smaller and smaller, but the input capacitance and on-state current density of the IGBT device are also increased due to the excessive cell density, so that the device is mismatched with the driving circuit, and the power is increased.
Based on the above, the application provides an insulated bipolar transistor with multiple potentials, which adjusts the structure of a cell, so that the input capacitance and current density of the device are reduced and adjustable. The insulated bipolar transistor of the present application with a poly potential will be described in detail with reference to fig. 2, taking an N-type IGBT device as an example:
the N-drift region 100 includes a first main surface and a second main surface which are oppositely disposed, wherein the first main surface is provided with a cell region 200 and a terminal region 300 which is positioned at the outer ring of the cell region 200 and surrounds the cell region 200, the cell region 200 includes a plurality of trenches 104 and each cell disposed between the trenches 104, and each cell includes:
the first type cell 210, the first type cell 210 includes a P-type base region 109, an n+ type carrier storage layer 111 and a p+ type ohmic contact region 112 are disposed in the P-type base region 109, the n+ type carrier storage layer 111 is connected with the trench 104, the p+ type ohmic contact region 112 and the n+ type carrier storage layer 111 are connected with the source metal 114 through a metal hole, the p+ type ohmic contact region 112 is located at the lower end of the metal hole or covers the metal hole, and poly in at least one adjacent trench 104 of the first type cell 210 is at a gate potential;
a second type of cell 220, also referred to as a carrier memory cell, includes a P-type base region 109, where the poly potential in the trench 104 adjacent to the carrier memory cell 220 is any potential;
the third type of cell 230, also called a current density controlling cell, includes a P-type base region 109 and a p+ -type ohmic contact region 112, the p+ -type ohmic contact region 112 is connected to the source metal 114 through a metal hole, the p+ -type ohmic contact region 112 is located at the lower end of the metal hole or covers the metal hole, and the poly potential in the trench 104 adjacent to the current density controlling cell 230 is any potential.
It should be noted that the positions and the number of the three types of cells can be adaptively set according to the input capacitance and the current density of the actual device.
Any potential may be a gate potential, a source potential, or other potentials connected to the source potential.
The material of the semiconductor substrate, i.e. the N-drift region 100, may be, for example, silicon carbide, gallium nitride-based material or diamond.
It will be appreciated that the first major surface is the upper surface of the N-drift region 100 and the second major surface is the lower surface of the N-drift region 100.
In this embodiment, an n+ type floating region covering the trench 104 is disposed below the trench 104, an oxide layer 108 is grown on the inner wall of the trench 104, and conductive polysilicon 107 is deposited in the trench.
In the present embodiment, the n+ -type cut layer 117, the p+ -type collector 118, and the collector metal 119 are stacked in this order on the second main surface.
For the IGBT device, the cell region 200 corresponds to a power device region inside the device, and the terminal region 300 corresponds to a guard ring and an isolation structure inside the device. Because the electric field intensity of the edge cylindrical region or the corner spherical region of the main junction is larger than that of the plane junction in the IGBT device, the problem of breakdown voltage reduction is easily caused, and therefore, a protection ring and an isolation structure are added in the IGBT device to improve the breakdown voltage.
In the present embodiment, the terminal area 300 includes:
the transition region 310 is located outside the cell region 200 and comprises a P-type well 101, a poly field plate 106 and a gate metal 115, wherein the poly field plate 106 is connected with the P-type well 101 and the gate metal 115;
a field limiting ring field plate structure 320 disposed around the transition region 310, including a P-type field limiting ring 103, a poly field plate 106, and a metal field plate 116, the metal field plate 116 being connected to the P-type field limiting ring 103 and the poly field plate 106;
the stop-ring region 330 is located outside the field limiting ring field plate structure 320 and includes an n+ type carrier storage layer 111 and a drain metal 113 connected to the n+ type carrier storage layer 111.
It should be noted that, the field oxide layer 102 and the insulating layer 110 are further provided, and the field oxide layer 102 and the insulating layer 110 may be adaptively provided according to actual requirements, which is not described herein again.
Example 2
Embodiment 2 of the present application also provides a method for manufacturing an insulated bipolar transistor with a poly potential, in which the method for manufacturing an insulated bipolar transistor with a poly potential of the present application is described below by taking an example of manufacturing an N-type insulated bipolar transistor, and the method for manufacturing the insulated bipolar transistor with a poly potential includes:
providing an N-type drift layer, depositing a hard mask and photoresist on a first main surface of the N-type drift layer, and etching the hard mask;
referring to fig. 3, the n-type drift layer 100 is a semiconductor substrate with two main surfaces, wherein the upper surface is a first main surface, the lower surface is a second main surface, and the material is silicon, silicon carbide, gallium nitride material or diamond.
In this embodiment, the material of the hard mask is silicon nitride.
Growing a field oxide layer 102 with a mask layer, removing the hard mask layer, photoetching a P-type impurity injection region, injecting P-type impurities, annealing to diffuse the impurities, and forming a P-type field limiting ring 103 and a P-type well 101 of a transition region, as shown in FIG. 4;
depositing a hard mask, etching the hard mask to form a pattern required for etching the groove, and etching the groove 104 under the shielding of the hard mask, see FIG. 5;
injecting an N+ type impurity into the bottom of the trench 104 by using a hard mask and performing well pushing to form an N+ type floating region 105 covering the bottom of the trench 104, and removing the hard mask, see FIG. 6;
growing an oxide layer 108 in the trenches 104, and then depositing and etching polysilicon between the trenches 104, at the transition region and at the position of the P-type field stop ring 103 to form trenches 104 and poly field plates 106 which comprise conductive polysilicon 107 and have flat surfaces, see fig. 7;
injecting P-type impurities into the positions corresponding to the cells, and forming a P-type base region 109 by a push well, see fig. 7;
injecting N+ type impurities into the P type base region 109 and the cut-off ring region at preset positions, and pushing a well to form an N+ type carrier storage layer 111, as shown in FIG. 8;
it should be noted that, the "first preset position" in this embodiment corresponds to the position of the first type of cell in embodiment 1.
Depositing an insulating layer 110 on the first main surface, photoetching the insulating layer 110 to form a pattern required by a metal hole, etching the metal hole to a required depth under the shielding of the insulating layer 110, injecting P-type impurities into the P-type base region 109 at a preset position, and forming a P-type ohmic contact region 112 after well pushing, as shown in fig. 8;
it should be noted that, the "second preset position" herein corresponds to the positions of the first type of cells and the third type of cells in embodiment 1.
Depositing a metal layer on the first main surface and performing photoetching to form a gate metal 115, a source metal 114, a metal field plate 116 and a drain metal 113, see fig. 9;
an n+ type impurity push well is implanted on the second main surface of the N-type drift layer 100 to form an n+ type cut-off region 117, a p+ type impurity push well is implanted to form a p+ type collector 118, and a metal is deposited to form a collector metal 119, see fig. 10.
It is noted that the specific values mentioned above are only for the purpose of illustrating the implementation of the present application in detail and should not be construed as limiting the present application. In other examples or embodiments or examples, other values may be selected according to the present application, without specific limitation.
Those of ordinary skill in the art will appreciate that: the above is only a preferred embodiment of the present application, and the present application is not limited thereto, but it is to be understood that the present application is described in detail with reference to the foregoing embodiments, and modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (11)
1. An insulated bipolar transistor of a poly potential comprising: a cell region and a termination region located on a first major surface of the drift region of the first conductivity type, characterized in that,
the terminal area is positioned on the outer ring of the cell area and surrounds the cell area;
the cellular region comprises: a cell adjacent to the poly potential in the trench being a gate potential and a cell adjacent to the poly potential in the trench being an arbitrary potential.
2. The bipolar transistor of claim 1, wherein the cells adjacent to the trench and having a gate potential include a second conductivity type base region, wherein a first conductivity type carrier storage layer and a second conductivity type ohmic contact region are disposed in the second conductivity type base region, wherein the first conductivity type carrier storage layer is connected to the trench, wherein the second conductivity type ohmic contact region and the first conductivity type carrier storage layer are connected to a source metal through a metal hole, and wherein the second conductivity type ohmic contact region is located at a lower end of the metal hole or covers the metal hole.
3. The bipolar transistor of claim 1, wherein the cells adjacent to the trench having any poly potential comprise a base region of the second conductivity type.
4. The bipolar transistor of claim 1, wherein the cells adjacent to the trench and having any poly potential comprise a second type base region and a second conductivity type ohmic contact region, the second conductivity type ohmic contact region being in metal contact with the source electrode through a metal hole, the second conductivity type ohmic contact region being at a lower end of the metal hole or surrounding the metal hole.
5. The bipolar transistor of claim 1, wherein the first conductivity type floating regions are disposed below the trenches.
6. The bipolar transistor of claim 1, wherein an oxide layer is grown on the inner walls of the trench and conductive polysilicon is deposited in the trench.
7. The bipolar transistor of claim 1, wherein the second major surface of the first conductivity type drift region is stacked with a first conductivity type blocking layer, a second conductivity type collector and a collector metal in that order.
8. The bipolar transistor of claim 1, wherein the termination region comprises:
and the transition region is positioned outside the cell region and comprises a second conductive type well, a poly field plate and a gate metal, and the poly field plate is connected with the second conductive type well and the gate metal.
9. The bipolar transistor of claim 8, wherein the termination region further comprises:
the field limiting ring field plate structure surrounds the transition region, and comprises a second conductive type field limiting ring, a poly field plate and a metal field plate, wherein the metal field plate is connected with the second conductive type field limiting ring and the poly field plate.
10. The bipolar transistor of claim 9, wherein the termination region further comprises:
and the cut-off ring region is positioned on the outer side of the field limiting ring field plate structure and comprises a first conductive type carrier storage layer and drain metal connected with the first conductive type carrier storage layer.
11. A method for manufacturing the bipolar transistor of a multipolymer potential, for manufacturing the bipolar transistor of a multipolymer potential according to any one of claims 1 to 10, comprising:
providing a first conductive type drift layer, depositing a hard mask and photoresist on a first main surface of the first conductive type drift layer, and etching the hard mask;
growing a field oxide layer with a mask layer, removing the hard mask layer, photoetching a second conductivity type impurity injection region, injecting second conductivity type impurities, annealing to diffuse the impurities, and forming a second conductivity type field limiting ring and a second conductivity type well of the transition region;
depositing a hard mask, etching the hard mask to form a pattern required by etching the groove, and etching the groove under the shielding of the hard mask;
injecting first conductivity type impurities into the bottom of the groove by using a hard mask, pushing the groove to form a first conductivity type floating region coating the bottom of the groove, and removing the hard mask;
growing an oxide layer in the groove, and then depositing and etching polysilicon among the grooves, the transition region and the second conductivity type field limiting ring to form a groove and a poly field plate, wherein the groove comprises conductive polysilicon and has a flat surface;
injecting second conductivity type impurities into the positions corresponding to the cells, and forming a second conductivity type base region by a push well;
injecting first conductivity type impurities into the second conductivity type base region and the cut-off ring region at the first preset position, and pushing the well to form a first conductivity type carrier storage layer;
depositing an insulating layer on the first main surface, photoetching the insulating layer to form a pattern required by a metal hole, etching the metal hole to a depth required by the metal hole under the shielding of the insulating layer, injecting second conductivity type impurities into a second conductivity type base region at a second preset position, and forming a second conductivity type ohmic contact region after well pushing;
depositing a metal layer on the first main surface and photoetching to form a gate metal, a source metal, a metal field plate and a drain metal;
and injecting a first conductive type impurity push well on the second main surface of the first conductive type drift layer to form a first conductive type cut-off region, injecting a second conductive type impurity push well to form a second conductive type collector, and depositing metal to form a collector metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311382398.5A CN117133799A (en) | 2023-10-24 | 2023-10-24 | Insulated bipolar transistor with multiple potentials and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311382398.5A CN117133799A (en) | 2023-10-24 | 2023-10-24 | Insulated bipolar transistor with multiple potentials and manufacturing method thereof |
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