CN111640679A - Graphene enhanced heat dissipation semiconductor packaging process, semiconductor product and electronic product - Google Patents

Graphene enhanced heat dissipation semiconductor packaging process, semiconductor product and electronic product Download PDF

Info

Publication number
CN111640679A
CN111640679A CN202010432877.3A CN202010432877A CN111640679A CN 111640679 A CN111640679 A CN 111640679A CN 202010432877 A CN202010432877 A CN 202010432877A CN 111640679 A CN111640679 A CN 111640679A
Authority
CN
China
Prior art keywords
heat dissipation
packaging process
chip
substrate
product
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN202010432877.3A
Other languages
Chinese (zh)
Inventor
王琇如
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Great Team Backend Foundry Dongguan Co Ltd
Original Assignee
Great Team Backend Foundry Dongguan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Great Team Backend Foundry Dongguan Co Ltd filed Critical Great Team Backend Foundry Dongguan Co Ltd
Priority to CN202010432877.3A priority Critical patent/CN111640679A/en
Publication of CN111640679A publication Critical patent/CN111640679A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention discloses a graphene enhanced heat dissipation semiconductor packaging process, a semiconductor product and an electronic product, wherein the packaging process comprises the following steps: s1, feeding a core, providing a substrate, arranging a chip on the substrate, and electrically connecting the chip and the substrate; s2, coating an insulating adhesive on the substrate provided with the chip for the first time to form an insulating adhesive layer; and S3, coating the heat dissipation layer on the surface of the insulating glue layer for the second time. Make the product encapsulation can adopt the material that has high heat dissipating ability through twice coating insulating glue layer and heat dissipation layer respectively in this scheme, rely on its good heat dispersion can improve the radiating effect of semiconductor product, set up the insulating glue and can effectually avoid graphite alkene heat dissipation layer to extend to and cause the short circuit between chip and the base plate.

Description

Graphene enhanced heat dissipation semiconductor packaging process, semiconductor product and electronic product
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a graphene enhanced heat dissipation semiconductor packaging process.
Background
The semiconductor is a material with a conductive capability between a conductor and a non-conductor, and the semiconductor element belongs to a solid-state element according to the characteristics of the semiconductor material, and the volume of the semiconductor element can be reduced to a small size, so that the power consumption is low, the integration level is high, and the semiconductor element is widely introduced in the field of electronic technology.
Disclosure of Invention
The embodiment of the invention aims to: the graphene enhanced heat dissipation semiconductor packaging process is provided, and the problems in the prior art can be solved.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a graphene enhanced heat dissipation semiconductor packaging process is provided, which includes the following steps:
s1, feeding a core, providing a substrate, arranging a chip on the substrate, and electrically connecting the chip and the substrate;
s2, coating an insulating adhesive on the substrate provided with the chip for the first time to form an insulating adhesive layer;
and S3, coating the heat dissipation layer on the surface of the insulating glue layer for the second time.
As a preferred technical solution of the graphene enhanced heat dissipation semiconductor packaging process, the heat dissipation layer is a graphene heat dissipation layer or a high heat dissipation carbonized material.
As a preferable technical scheme of the graphene enhanced heat dissipation semiconductor packaging process, the insulating glue is low-viscosity insulating glue so as to ensure that the insulating glue can enter a gap between the chip and the substrate.
As a preferred technical solution of the graphene enhanced heat dissipation semiconductor packaging process, the material viscosity of the heat dissipation layer is greater than the viscosity of the insulating glue.
As a preferable technical solution of the graphene enhanced heat dissipation semiconductor packaging process, the step of curing is further included after the second coating is completed, the curing temperature is between 100 ℃ and 190 ℃, and the curing time is greater than or equal to 30 minutes.
As an optimal technical scheme of the graphene enhanced heat dissipation semiconductor packaging process, the substrate is a PCB, the chip is arranged on the substrate in an inverted manner, and the chip is electrically connected with a circuit on the PCB through a solder ball.
As an optimal technical scheme of the graphene enhanced heat dissipation semiconductor packaging process, the insulating glue extends into a space between the chip and the PCB after one-time coating and covers the solder ball.
As a preferred technical solution of the graphene enhanced heat dissipation semiconductor packaging process, the packaging process is performed on a wafer-level product, and a single semiconductor product is formed by cutting after secondary coating and curing.
In another aspect, a semiconductor product is provided, which is packaged by using the graphene enhanced heat dissipation semiconductor packaging process as described above.
In another aspect, an electronic product having a semiconductor product processed by the graphene enhanced heat dissipation semiconductor packaging process is provided.
The invention has the beneficial effects that: make the product encapsulation can adopt the material that has high heat dissipating ability through twice coating insulating glue layer and heat dissipation layer respectively in this scheme, rely on its good heat dispersion can improve the radiating effect of semiconductor product, set up the insulating glue and can effectually avoid graphite alkene heat dissipation layer to extend to and cause the short circuit between chip and the base plate.
Drawings
The invention is explained in more detail below with reference to the figures and examples.
Fig. 1 is a flowchart of a graphene enhanced heat dissipation semiconductor packaging process according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a primary coating process according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a secondary coating process according to an embodiment of the invention.
In the figure:
100. a PCB; 200. a chip; 300. an insulating glue layer; 400. a heat dissipation layer; 500. solder balls.
Detailed Description
In order to make the technical problems solved, technical solutions adopted, and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention are described in further detail below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, unless otherwise expressly specified or limited, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
As shown in fig. 1 to 3, the present embodiment provides a graphene enhanced heat dissipation semiconductor packaging process, which includes the following steps:
s1, mounting a core, providing a substrate, arranging a chip 200 on the substrate, and electrically connecting the chip 200 and the substrate;
s2, coating insulating glue on the substrate provided with the chip 200 for the first time to form an insulating glue layer 300;
and S3, coating the heat dissipation layer 400 on the surface of the insulating adhesive layer 300 for the second time.
In this scheme, the insulating adhesive layer 300 and the heat dissipation layer 400 are coated twice respectively, so that the product package can adopt a material with high heat dissipation performance, the heat dissipation effect of the semiconductor product can be improved by virtue of the excellent heat dissipation performance of the product, and the insulating adhesive is arranged to effectively prevent the graphene heat dissipation layer 400 from extending to a position between the chip 200 and the substrate to cause short circuit.
In this scheme, the heat dissipation layer 400 can be graphene heat dissipation layer 400 or a high heat dissipation carbonized material.
Specifically, the graphene heat dissipation layer 400 is adopted in this embodiment.
Graphene has very good thermal conductivity. The pure defect-free single-layer graphene has the thermal conductivity coefficient as high as 5300W/mK, is the carbon material with the highest thermal conductivity coefficient so far, and is higher than that of a single-wall carbon nanotube (3500W/mK) and a multi-wall carbon nanotube (3000W/mK). When it is used as the carrier 100, the thermal conductivity can also reach 600W/mK.
Specifically, in this embodiment, the insulating paste is a low-viscosity insulating paste, so as to ensure that the insulating paste can enter a gap between the chip 200 and the substrate. The material viscosity of the heat dissipation layer 400 is greater than the viscosity of the insulating paste.
As a preferable technical solution of the graphene enhanced heat dissipation semiconductor packaging process of this embodiment, the step of curing is further included after the second coating is completed, the curing temperature is between 100 ℃ and 190 ℃, and the curing time is greater than or equal to 30 minutes.
Specifically, in this example, the curing temperature is 100 ℃, and the curing time is 50 minutes.
In another embodiment of the present invention, the curing temperature is 300 ℃ and the curing time is 30 minutes.
In yet another embodiment of the present invention, the curing temperature is 200 ℃ and the curing time is 45 minutes.
In this embodiment, the substrate is a PCB100, the chip 200 is disposed on the substrate in a flip-chip manner, and the chip 200 is electrically connected to a circuit on the PCB100 through a solder ball 500.
After the first coating, the insulating paste extends into the space between the chip 200 and the PCB100 and covers the solder ball 500. By extending the insulating adhesive between the chip 200 and the PCB100 and coating the insulating adhesive with tin, the solder ball 500 can block the insulating adhesive to a certain extent, so that the insulating adhesive can be prevented from flowing into the space, which causes the height of the insulating adhesive on the PCB100 to decrease, and the insulating adhesive can not completely seal the gap between the chip 200 and the PCB100, which may cause the graphene heat dissipation layer 400 to enter the gap between the chip 200 and the PCB100 to cause short circuit.
Specifically, the packaging process is performed on the wafer-level product in this embodiment, and the wafer-level product is cut into individual semiconductor products after the secondary coating and curing are completed.
Meanwhile, the embodiment also provides a semiconductor product which is packaged by adopting the graphene enhanced heat dissipation semiconductor packaging process.
The embodiment also provides an electronic product, which has a semiconductor product processed by the graphene enhanced heat dissipation semiconductor packaging process.
In the description herein, it is to be understood that the terms "upper," "lower," "left," "right," and the like are used in an orientation or positional relationship merely for convenience in description and simplicity of operation, and do not indicate or imply that the referenced device or element must have a particular orientation, configuration, and operation in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.

Claims (10)

1. A graphene enhanced heat dissipation semiconductor packaging process is characterized by comprising the following steps:
s1, mounting a core, providing a substrate, arranging a chip (200) on the substrate, and electrically connecting the chip (200) and the substrate;
s2, coating insulating glue on the substrate provided with the chip (200) for the first time to form an insulating glue layer (300);
and S3, coating the heat dissipation layer (400) on the surface of the insulating glue layer (300) for the second time.
2. The graphene enhanced heat dissipation semiconductor packaging process according to claim 1, wherein the heat dissipation layer (400) is a graphene heat dissipation layer (400) or a high heat dissipation carbonized material.
3. The graphene-enhanced heat dissipation semiconductor packaging process according to claim 2, wherein a low-viscosity insulating glue is adopted as the insulating glue to ensure that the insulating glue can enter a gap between the chip (200) and the substrate.
4. The graphene enhanced heat dissipation semiconductor packaging process according to claim 3, wherein the material viscosity of the heat dissipation layer (400) is greater than the viscosity of the insulating glue.
5. The graphene-based heat dissipation enhancing semiconductor packaging process of claim 4, further comprising a step of curing after the second coating is completed, wherein the curing temperature is between 100 ℃ and 190 ℃, and the curing time is greater than or equal to 30 minutes.
6. The graphene enhanced heat dissipation semiconductor packaging process of claim 5, wherein the substrate is a PCB (100), the chip (200) is disposed on the substrate in a flip-chip manner, and the chip (200) is electrically connected to a circuit on the PCB (100) through a solder ball (500).
7. The graphene enhanced heat dissipation semiconductor packaging process of claim 6, wherein the insulating paste extends into a space between the chip (200) and the PCB (100) after one coating and covers the solder ball (500).
8. The graphene enhanced heat dissipation semiconductor packaging process of claim 7, wherein the packaging process is performed on a wafer-level product, and the secondary coating and curing are performed and then the wafer-level product is cut to form a single semiconductor product.
9. A semiconductor product, wherein the graphene enhanced heat dissipation semiconductor packaging process of any one of claims 1-8 is adopted for packaging.
10. An electronic product, characterized in that, the electronic product is a semiconductor product processed by the graphene enhanced heat dissipation semiconductor packaging process according to any one of claims 1 to 8.
CN202010432877.3A 2020-05-21 2020-05-21 Graphene enhanced heat dissipation semiconductor packaging process, semiconductor product and electronic product Withdrawn CN111640679A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010432877.3A CN111640679A (en) 2020-05-21 2020-05-21 Graphene enhanced heat dissipation semiconductor packaging process, semiconductor product and electronic product

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010432877.3A CN111640679A (en) 2020-05-21 2020-05-21 Graphene enhanced heat dissipation semiconductor packaging process, semiconductor product and electronic product

Publications (1)

Publication Number Publication Date
CN111640679A true CN111640679A (en) 2020-09-08

Family

ID=72329383

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010432877.3A Withdrawn CN111640679A (en) 2020-05-21 2020-05-21 Graphene enhanced heat dissipation semiconductor packaging process, semiconductor product and electronic product

Country Status (1)

Country Link
CN (1) CN111640679A (en)

Similar Documents

Publication Publication Date Title
CN205194687U (en) A heat conduction silica gel sheet for cell -phone
CN102244066B (en) Power semiconductor module
CN104637910B (en) Semiconductor module and its manufacture method
CN112018049B (en) Chip packaging structure and electronic equipment
WO2015064231A1 (en) Semiconductor module
JP2004006603A (en) Semiconductor power device
CN106783753A (en) Semiconductor devices
JP2010199367A (en) Heat radiating material and method for manufacturing the same, and electronic device and method for manufacturing the same
CN111640679A (en) Graphene enhanced heat dissipation semiconductor packaging process, semiconductor product and electronic product
CN108281406B (en) Power device packaging structure and manufacturing method thereof
CN111640680A (en) Semiconductor packaging process, semiconductor product and electronic product
CN209785918U (en) SMD triode
CN111725161B (en) Semiconductor heat dissipation device, packaging method and electronic product
CN203983160U (en) A kind of solid-state relay with Rapid Thermal dissipation
CN111640681A (en) High-heat-dissipation semiconductor packaging process
CN110951199B (en) Insulating heat conduction material for semiconductor and preparation method thereof
CN111725159A (en) High-heat-dissipation semiconductor product, packaging method and electronic product
CN212587482U (en) Semiconductor product with top heat dissipation function and electronic product
CN210925990U (en) Semiconductor device with a plurality of transistors
CN212587484U (en) Dual-heat-dissipation semiconductor product and electronic product
CN211980603U (en) Semiconductor product and electronic product with bottom surface heat dissipation plate
CN218243947U (en) Heat radiation structure for flat surface-mounted packaged power device and electronic circuit thereof
CN212587495U (en) Semiconductor product electric connection structure and electronic product
TW201145474A (en) Heat dissipation device of electronic/photoelectric element
CN215496781U (en) Refrigeration chip and nanometer water ion generator

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication

Application publication date: 20200908

WW01 Invention patent application withdrawn after publication