CN111640681A - High-heat-dissipation semiconductor packaging process - Google Patents
High-heat-dissipation semiconductor packaging process Download PDFInfo
- Publication number
- CN111640681A CN111640681A CN202010432881.XA CN202010432881A CN111640681A CN 111640681 A CN111640681 A CN 111640681A CN 202010432881 A CN202010432881 A CN 202010432881A CN 111640681 A CN111640681 A CN 111640681A
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- Prior art keywords
- heat dissipation
- insulating
- chip
- substrate
- packaging
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000012858 packaging process Methods 0.000 title claims abstract description 29
- 230000017525 heat dissipation Effects 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 16
- 239000005022 packaging material Substances 0.000 claims abstract description 15
- 238000004806 packaging method and process Methods 0.000 claims abstract description 15
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 11
- 229910021389 graphene Inorganic materials 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 239000003292 glue Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 30
- 238000010586 diagram Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- RKUAZJIXKHPFRK-UHFFFAOYSA-N 1,3,5-trichloro-2-(2,4-dichlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC=C1C1=C(Cl)C=C(Cl)C=C1Cl RKUAZJIXKHPFRK-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000002048 multi walled nanotube Substances 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002109 single walled nanotube Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a high heat dissipation semiconductor packaging process, a product and an electronic product, wherein the high heat dissipation semiconductor packaging process comprises the following steps: s1, feeding a core, providing a substrate, arranging a chip on the substrate, and electrically connecting the chip and the substrate; s2, providing a packaging material, and providing an insulating heat dissipation packaging material comprising an insulating layer and a heat dissipation layer; and S3, packaging the chip arranged on the substrate by adopting the insulating heat dissipation material. According to the scheme, the semiconductor is packaged by adopting the insulating heat dissipation packaging material with the insulating layer and the heat dissipation layer, the heat dissipation effect of the semiconductor product can be improved by relying on the excellent heat dissipation performance of the heat dissipation layer, and the heat dissipation layer can be prevented from entering the space between the chip and the substrate to cause short circuit by arranging the insulating layer.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a high-heat-dissipation semiconductor packaging process.
Background
The semiconductor is a material with a conductive capability between a conductor and a non-conductor, and the semiconductor element belongs to a solid-state element according to the characteristics of the semiconductor material, and the volume of the semiconductor element can be reduced to a small size, so that the power consumption is low, the integration level is high, and the semiconductor element is widely introduced in the field of electronic technology.
Disclosure of Invention
The embodiment of the invention aims to: a high heat dissipation semiconductor packaging process is provided, which can solve the above problems in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, a high heat dissipation semiconductor packaging process is provided, which includes the following steps:
s1, feeding a core, providing a substrate, arranging a chip on the substrate, and electrically connecting the chip and the substrate;
s2, providing a packaging material, and providing an insulating heat dissipation packaging material comprising an insulating layer and a heat dissipation layer;
and S3, packaging the chip arranged on the substrate by adopting the insulating heat dissipation material.
As a preferable technical scheme of the high heat dissipation semiconductor packaging process, the insulating layer is an insulating glue material or an insulating heat dissipation material, and the heat dissipation layer is a graphene heat dissipation layer.
As a preferable technical solution of the high heat dissipation semiconductor packaging process, the insulating heat dissipation packaging material is formed by laminating the heat dissipation layer and the insulating layer.
As a preferable technical scheme of the high heat dissipation semiconductor packaging process, the substrate is a PCB, the chip is arranged on the substrate in an inverted manner, and the chip is electrically connected with a circuit on the PCB through a solder ball.
As a preferable technical solution of the high heat dissipation semiconductor packaging process, the packaging is performed in a lamination manner.
As a preferable technical solution of the high heat dissipation semiconductor packaging process, the insulating paste extends into a space between the chip and the PCB and covers the solder ball.
As a preferred technical solution of the high heat dissipation semiconductor packaging process, a step of plasma cleaning is further included before the packaging.
As a preferable technical solution of the high heat dissipation semiconductor packaging process, curing is further included after the packaging, and the curing time is 1 to 3 hours.
In another aspect, a semiconductor product is provided, which is packaged by using the high heat dissipation semiconductor packaging process as described above.
In still another aspect, an electronic product having a semiconductor product processed by the high heat dissipation semiconductor packaging process is provided.
The invention has the beneficial effects that: according to the scheme, the semiconductor is packaged by adopting the insulating heat dissipation packaging material with the insulating layer and the heat dissipation layer, the heat dissipation effect of the semiconductor product can be improved by relying on the excellent heat dissipation performance of the heat dissipation layer, and the heat dissipation layer can be prevented from entering the space between the chip and the substrate to cause short circuit by arranging the insulating layer.
Drawings
The invention is explained in more detail below with reference to the figures and examples.
Fig. 1 is a flow chart of a high heat dissipation semiconductor packaging process according to an embodiment of the invention.
Fig. 2 is a schematic structural diagram of a high heat dissipation semiconductor product according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of an insulating and heat dissipating package material according to an embodiment of the invention.
In the figure:
100. a PCB; 200. a chip; 300. an insulating heat-dissipating packaging material; 310. an insulating layer; 320. a graphene heat dissipation layer; 400. solder balls.
Detailed Description
In order to make the technical problems solved, technical solutions adopted, and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention are described in further detail below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, unless otherwise expressly specified or limited, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
As shown in fig. 1-3, the present embodiment provides a high heat dissipation semiconductor packaging process, which includes the following steps:
s1, mounting a core, providing a substrate, arranging a chip 200 on the substrate, and electrically connecting the chip 200 and the substrate;
s2, providing a packaging material, and providing an insulating heat dissipation packaging material 300 comprising an insulating layer 310 and a heat dissipation layer;
and S3, packaging the chip 200 arranged on the substrate by adopting the insulating heat dissipation material.
According to the scheme, the semiconductor is packaged by the insulating heat dissipation packaging material 300 with the insulating layer 310 and the heat dissipation layer, the heat dissipation effect of a semiconductor product can be improved by means of excellent heat dissipation performance of the heat dissipation layer, and the heat dissipation layer can be prevented from entering a space between the chip 200 and the substrate to cause short circuit by the aid of the insulating layer 310.
In this embodiment, the insulating layer 310 may be an insulating glue material or an insulating heat sink material.
Specifically, in the present embodiment, an insulating adhesive material is used as the insulating layer 310.
The heat dissipation layer is preferably a graphene heat dissipation layer 320. Graphene has very good thermal conductivity. The pure defect-free single-layer graphene has the thermal conductivity coefficient as high as 5300W/mK, is the carbon material with the highest thermal conductivity coefficient so far, and is higher than that of a single-wall carbon nanotube (3500W/mK) and a multi-wall carbon nanotube (3000W/mK). When it is used as the carrier 100, the thermal conductivity can also reach 600W/mK.
The insulating and heat dissipating package material 300 is formed by laminating the graphene heat dissipating layer 320 and the insulating layer 310.
In a specific use process, the insulating layer 310 is disposed toward one side of the chip 200 and the PCB100, and the graphene heat dissipation layer 320 is disposed away from the chip 200 and the PCB 100.
The substrate is a PCB100, the chip 200 is arranged on the substrate in a flip-chip manner, and the chip 200 is electrically connected with a circuit on the PCB100 through a solder ball 400.
In the scheme, the insulating glue of the insulating and heat-dissipating packaging material 300 melts in the hot-pressing process, extends into the space between the chip 200 and the PCB100, fills the gap, coats the solder ball 400, and ensures that the graphene heat dissipation layer 320 cannot enter, so that the graphene is insulated from the chip 200 and the PCB100, and short circuit of the product is avoided.
As a preferable technical solution of the high heat dissipation semiconductor packaging process, the packaging is performed in a lamination manner.
A plasma clean step is also included prior to the encapsulation.
Preferably, the packaging method further comprises curing after the packaging, wherein the curing time is 1-3 hours.
Meanwhile, the embodiment also provides a semiconductor product which is packaged by adopting the high heat dissipation semiconductor packaging process.
Meanwhile, the embodiment also discloses an electronic product which is provided with the semiconductor product processed by the high-heat-dissipation semiconductor packaging process.
In the description herein, it is to be understood that the terms "upper," "lower," "left," "right," and the like are used in an orientation or positional relationship merely for convenience in description and simplicity of operation, and do not indicate or imply that the referenced device or element must have a particular orientation, configuration, and operation in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.
Claims (10)
1. A high heat dissipation semiconductor packaging process is characterized by comprising the following steps:
s1, mounting a core, providing a substrate, arranging a chip (200) on the substrate, and electrically connecting the chip (200) and the substrate;
s2, providing a packaging material, and providing an insulating heat dissipation packaging material (300) comprising an insulating layer (310) and a heat dissipation layer;
and S3, packaging the chip (200) arranged on the substrate by adopting the insulating heat dissipation material.
2. The high heat dissipation semiconductor packaging process of claim 1, wherein the insulating layer (310) is an insulating glue material or an insulating heat dissipation material, and the heat dissipation layer is a graphene heat dissipation layer (320).
3. The high heat dissipation semiconductor packaging process of claim 1 or 2, wherein the insulating and heat dissipation packaging material (300) is formed by laminating the heat dissipation layer and the insulating layer (310).
4. The high heat dissipation semiconductor packaging process of claim 3, wherein the substrate is a PCB (100), the chip (200) is disposed on the substrate in a flip-chip manner, and the chip (200) is electrically connected to the circuit on the PCB (100) through a solder ball (400).
5. The high heat dissipation semiconductor packaging process of claim 1, 2, 3 or 4, wherein the packaging is performed in a laminating manner.
6. The high heat dissipation semiconductor packaging process of claim 4, wherein the insulating glue extends into a space between the chip (200) and the PCB (100) and covers the solder ball (400).
7. The process of claim 6, further comprising a step of plasma cleaning before said packaging.
8. The process for packaging a high heat dissipation semiconductor according to claim 7, further comprising curing after the packaging, wherein the curing is performed for 1-3 hours.
9. A semiconductor product, which is packaged by the high heat dissipation semiconductor packaging process of any one of claims 1-8.
10. An electronic product, characterized in that, the electronic product is a semiconductor product processed by the high heat dissipation semiconductor packaging process of any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010432881.XA CN111640681A (en) | 2020-05-21 | 2020-05-21 | High-heat-dissipation semiconductor packaging process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010432881.XA CN111640681A (en) | 2020-05-21 | 2020-05-21 | High-heat-dissipation semiconductor packaging process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111640681A true CN111640681A (en) | 2020-09-08 |
Family
ID=72332736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010432881.XA Withdrawn CN111640681A (en) | 2020-05-21 | 2020-05-21 | High-heat-dissipation semiconductor packaging process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111640681A (en) |
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2020
- 2020-05-21 CN CN202010432881.XA patent/CN111640681A/en not_active Withdrawn
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Application publication date: 20200908 |
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| WW01 | Invention patent application withdrawn after publication |