CN111563012B - Software testing method for detecting NORFLASH memory global bit line short-circuit fault - Google Patents

Software testing method for detecting NORFLASH memory global bit line short-circuit fault Download PDF

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Publication number
CN111563012B
CN111563012B CN201911378529.6A CN201911378529A CN111563012B CN 111563012 B CN111563012 B CN 111563012B CN 201911378529 A CN201911378529 A CN 201911378529A CN 111563012 B CN111563012 B CN 111563012B
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flash
space
data
test
programming
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CN111563012A (en
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边维
张永华
李红军
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Tianjin Jinhang Computing Technology Research Institute
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Tianjin Jinhang Computing Technology Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1448—Management of the data involved in backup or backup restore
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention relates to a software testing method for detecting a global bit line short-circuit fault of a NORFLASH memory, which comprises the following steps: after receiving the NORFLASH backup command and the test parameters, the test software backs up the appointed space data into a cache space and calculates the checksum of the FLASH read data, calculates the checksum of the cache space after the backup is completed, compares whether the checksums are consistent, if not, sets the command execution state as a check error, and terminates the test; a FLASH erasing programming test, and erasing the FLASH whole space; performing programming test on the FLASH designated area according to the programming type; performing read-back verification on the programmed area; performing FLASH erasing programming test operation circularly according to different programming types; erasing the FLASH whole space; recovering FLASH data, and resetting the FLASH; programming data of the cache space to a designated FLASH space; and calculating the FLASH and cache data checksums, and comparing whether the FLASH and cache data checksums are consistent.

Description

Software testing method for detecting NORFLASH memory global bit line short-circuit fault
Technical Field
The invention belongs to the technical field of electronic information, and particularly relates to a software testing method for detecting a global bit line short-circuit fault of a NORFLASH memory.
Background
A certain comprehensive control machine is provided with a JFM LV641-E type NORFLASH memory chip, after production, a FLASH erasing programming test is carried out, but after delivery, the situation that application software cannot be solidified still occurs, after investigation, the fault is found to be a global bit line short circuit fault caused by defects in the manufacturing process, the traditional FLASH testing mode is that the idle FLASH space is erased and programmed, programming data are mostly regular step 0 and step 1 data, so that testing of data lines, address lines and FLASH erasing programming functions is realized, and the fault is difficult to detect. This failure requires the chip manufacturer to write special test patterns using the ATE equipment to screen out, however, for the finished product, the chip needs to be disassembled for factory return testing.
Disclosure of Invention
The present invention is directed to an embodiment of a software testing method for detecting a global bitline short fault of a NORFLASH memory in accordance with the present invention, which is used to solve the above-mentioned problems of the prior art.
An embodiment of a software testing method for detecting a global bit line short-circuit fault of a NORFLASH memory according to the present invention includes: FLASH data backup, including: after receiving the NORFLASH backup command and the test parameters, the test software backs up the specified space data into the cache space, calculates the checksum of the FLASH read data, calculates the checksum of the cache space after the backup is completed, compares whether the checksums are consistent, if not, sets the command execution state as a check error, and terminates the test; a FLASH erase programming test comprising: erasing the FLASH whole space; performing programming test on the FLASH designated area according to the programming type; performing read-back verification on the programmed area; performing FLASH erasing programming test operation circularly according to different programming types; erasing the FLASH whole space; FLASH data recovery includes: resetting FLASH; programming data of the cache space to a designated FLASH space; and calculating the FLASH and cache data checksums, and comparing whether the FLASH and cache data checksums are consistent.
An embodiment of a software testing method for detecting a global bit line short-circuit fault of a NORFLASH memory according to the present invention further includes: and caching the software in the FLASH into an external memory SDRAM, performing erasure operation on the whole space of the FLASH, and identifying the short circuit fault of the bit line of the sector through programming of a specific sequence and data verification after programming.
According to one embodiment of the software testing method for detecting the global bit line short-circuit fault of the NORFLASH memory, FLASH data backup, FLASH erasing programming test and FLASH data recovery are sequentially carried out according to a flow.
According to one embodiment of the software testing method for detecting the global bit line short-circuit fault of the NORFLASH memory, after the testing software receives the NORFLASH backup command and the testing parameters, specified space data are backed up into a cache space, and meanwhile, the FLASH read data checksum is calculated to be 8-bit accumulated sum.
According to one embodiment of the software testing method for detecting the global bit line short circuit fault of the NORFLASH memory, the buffer space checksum is calculated as an 8-bit accumulated sum after the backup is completed.
According to one embodiment of the software testing method for detecting a global bit line short circuit fault of a NORFLASH memory, a FLASH and cache data checksum is calculated as an 8-bit accumulated sum.
The invention designs a software test method for detecting the global bit line short-circuit fault of the NORFLASH memory, which is used for detecting the possible sector bit line short-circuit fault of a product FLASH chip, and avoids a large amount of factory return maintenance work.
Drawings
Fig. 1 is a NOR FLASH test flow diagram.
Detailed Description
For the purposes of clarity, content, and advantages of the present invention, a detailed description of the embodiments of the present invention will be described in detail below with reference to the drawings and examples.
FIG. 1 is a flow chart of NOR FLASH test, as shown in FIG. 1, a software test method for detecting a NORFLASH memory global bit line short circuit fault according to the present invention includes: and the DSP test software is adopted, firstly, the FLASH internal software is cached in an external memory SDRAM, the FLASH whole space is erased, and the sector meta-line short circuit fault is identified through the programming of a specific sequence and the data verification after the programming.
The testing flow designed by the invention is divided into three parts, namely FLASH data backup, FLASH erasing programming test and FLASH data recovery, the testing flow is shown in figure 1,
the test method is described below:
FLASH data backup
After receiving the NORFLASH backup command and the test parameters, the test software backs up the specified space data into the cache space, calculates the FLASH read data checksum (8-bit accumulation sum), calculates the cache space checksum (8-bit accumulation sum) after the backup is finished, compares whether the checksums are consistent, if not, sets the command execution state as a check error, and terminates the test.
FLASH erase programming test
Erasing the FLASH whole space;
performing programming test on the FLASH designated area according to the programming type 1 (shown in table 1);
read-back verification of programmed regions
Performing 2.1) -2.4) operations according to program types 2, 3, 4 loops
Erasing FLASH full space
FLASH data recovery
Resetting FLASH
Programming data of the cache space to the designated FLASH space
Calculating FLASH and cache data checksum (8-bit accumulation sum) and comparing whether the FLASH and cache data checksum are consistent; table 1 is a FLASH programming data specification table.
TABLE 1
The test scheme is designed aiming at the fault mode of rare global bit line short circuit of the NORFLASH chip, and the NORFLASH chip on the finished product is subjected to troubleshooting and identification in a CPU software read-write mode.
The invention has the advantages that:
the identification capability of the original data line and address line short circuit fault modes is covered, and the original full-space programming verification process is simplified.
The fault identification capability of the sector meta-line short circuit can be effectively screened, and the uncovering maintenance operation is not required.
Aiming at the products which are produced and filled with software, the depth detection of FLASH is finished under the condition that the state of software and hardware is not influenced.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.

Claims (6)

1. A test method for reading and writing FLASH memory space by using DSP software is characterized by comprising the following steps:
FLASH data backup, including:
after receiving the NORFLASH backup command and the test parameters, the test software backs up the specified space data into the cache space, calculates the checksum of the FLASH read data, calculates the checksum of the cache space after the backup is completed, compares whether the checksums are consistent, if not, sets the command execution state as a check error, and terminates the test;
a FLASH erase programming test comprising:
erasing the FLASH whole space;
performing programming test on the FLASH designated area according to the programming type;
performing read-back verification on the programmed area;
performing FLASH erasing programming test operation circularly according to different programming types;
erasing the FLASH whole space;
FLASH data recovery includes:
resetting FLASH;
programming data of the cache space to a designated FLASH space;
and calculating the data checksum of the FLASH space and the cache space, and comparing whether the data checksum is consistent.
2. The method for testing the FLASH memory space by using the DSP software according to claim 1, further comprising: and caching the software in the FLASH into an external memory SDRAM, performing erasure operation on the whole space of the FLASH, and identifying the short circuit fault of the meta-line of the sector through programming and data verification after programming.
3. The method for testing the FLASH memory space by using the DSP software according to claim 1, wherein the FLASH data backup, the FLASH erase programming test and the FLASH data recovery are performed sequentially according to a flow.
4. The method for testing the FLASH memory space by using the DSP software according to claim 1, wherein after the test software receives the NORFLASH backup command and the test parameters, the specified space data is backed up into the cache space and the checksum of the FLASH read data is calculated as an 8-bit accumulated sum.
5. The method for testing the FLASH memory space by using the DSP software according to claim 1, wherein the checksum of the buffer memory space is calculated as an 8-bit accumulated sum after the backup is completed.
6. The method for testing FLASH memory space using DSP software as set forth in claim 1, wherein the FLASH and cache data checksum is calculated as an 8-bit accumulation sum.
CN201911378529.6A 2019-12-27 2019-12-27 Software testing method for detecting NORFLASH memory global bit line short-circuit fault Active CN111563012B (en)

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CN115775588A (en) * 2021-09-08 2023-03-10 长鑫存储技术有限公司 Data path detection method, device, equipment and storage medium

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