CN111563012A - Software testing method for detecting NORFLASH memory global bit line short-circuit fault - Google Patents

Software testing method for detecting NORFLASH memory global bit line short-circuit fault Download PDF

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CN111563012A
CN111563012A CN201911378529.6A CN201911378529A CN111563012A CN 111563012 A CN111563012 A CN 111563012A CN 201911378529 A CN201911378529 A CN 201911378529A CN 111563012 A CN111563012 A CN 111563012A
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flash
data
space
programming
test
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CN111563012B (en
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边维
张永华
李红军
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Tianjin Jinhang Computing Technology Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1448—Management of the data involved in backup or backup restore
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 

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  • Physics & Mathematics (AREA)
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Abstract

The invention relates to a software testing method for detecting NORFLASH memory global bit line short circuit fault, which comprises the following steps: backing up FLASH data, wherein after receiving NORFLASH backup commands and test parameters, test software backs up specified space data into a cache space and calculates FLASH read data check sums at the same time, after the backup is finished, the cache space check sums are calculated, whether the check sums are consistent or not is compared, if not, the command execution state is set to be a check error, and the test is terminated; erasing programming test of FLASH, erasing FLASH whole space; carrying out programming test on the designated FLASH area according to the programming type; carrying out read-back verification on the programmed area; circularly executing FLASH erasing programming test operation according to different programming types; erasing the FLASH full space; recovering FLASH data, and resetting FLASH; programming the data of the cache space to a designated FLASH space; and calculating the checksum of the FLASH and the cache data, and comparing whether the checksum is consistent or not.

Description

Software testing method for detecting NORFLASH memory global bit line short-circuit fault
Technical Field
The invention belongs to the technical field of electronic information, and particularly relates to a software testing method for detecting NORFLASH memory global bit line short circuit fault.
Background
A certain integrated control machine is provided with JFM29LV641-E NORFLASH memory chips, although a FLASH erasing programming test is carried out after production, the situation that application software cannot be solidified still occurs after delivery, after troubleshooting, the fault is found to be a global bit line short circuit fault caused by defects in the manufacturing and processing process, the traditional FLASH testing mode is to erase and program an idle FLASH space, programming data are mostly regular step 0 and step 1 data, the fault is used for testing a data line, an address line and a FLASH erasing programming function, and the fault is difficult to detect. The failure needs to be screened out by the chip manufacturer by writing some special test patterns using ATE equipment, but for the finished product, the chip needs to be disassembled and then tested back to the factory.
Disclosure of Invention
The invention relates to a testing method for reading and writing FLASH storage space by using DSP software, which is used for solving the problems in the prior art.
The invention relates to a testing method for reading and writing FLASH storage space by using DSP software, which comprises the following steps: FLASH data backup, including: after receiving NORFLASH backup command and test parameters, the test software backups the specified space data to the cache space and calculates FLASH read data check sum, calculates the cache space check sum after the backup is finished, compares whether the check sum is consistent, if not, sets the command execution state as check error, and terminates the test; a FLASH erase programming test comprising: erasing the FLASH full space; carrying out programming test on the designated FLASH area according to the programming type; carrying out read-back verification on the programmed area; circularly executing FLASH erasing programming test operation according to different programming types; erasing the FLASH full space; FLASH data recovery, including: resetting the FLASH; programming the data of the cache space to a designated FLASH space; and calculating the checksum of the FLASH and the cache data, and comparing whether the checksum is consistent or not.
According to an embodiment of the testing method for reading and writing the FLASH memory space by using the DSP software, the testing method further comprises the following steps: caching the software in the FLASH into an external memory SDRAM, carrying out erasing operation on the whole space of the FLASH, and identifying the bit line short circuit fault in the sector by programming of a specific sequence and data verification after programming.
According to an embodiment of the testing method for reading and writing the FLASH storage space by using the DSP software, FLASH data backup, FLASH erasing programming test and FLASH data recovery are sequentially carried out according to the flow.
According to an embodiment of the testing method for reading and writing the FLASH storage space by using the DSP software, after receiving the NORFLASH backup command and the testing parameters, the testing software backups the specified space data into the cache space and calculates the FLASH read data checksum as 8-bit accumulated sum.
According to an embodiment of the testing method for reading and writing the FLASH storage space by using the DSP software, the check sum of the cache space is calculated to be 8-bit accumulated sum after the backup is finished.
According to an embodiment of the testing method for reading and writing the FLASH storage space by using the DSP software, the checksum of the FLASH and the cache data is calculated as 8-bit accumulated sum.
The invention designs a testing method for reading and writing FLASH storage space by using DSP software, which is used for detecting the possible short circuit fault of a bit line between sectors of a FLASH chip of a product and avoiding a large amount of repair work for returning to a factory.
Drawings
Figure 1 is a NOR FLASH test flow diagram.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
Fig. 1 is a flow chart of NOR FLASH test, and as shown in fig. 1, the testing method for reading and writing FLASH memory space by using DSP software of the present invention includes: the method comprises the steps of firstly caching the FLASH internal software into an external memory SDRAM by adopting DSP test software, carrying out erasing operation on the FLASH whole space, and identifying the line short fault in the position of a sector through programming of a specific sequence and data verification after the programming.
The testing process designed by the invention is divided into three parts to be carried out, namely FLASH data backup, FLASH erasing programming test and FLASH data recovery are carried out in sequence, the testing process is shown as figure 1,
the test methods are described below:
FLASH data backup
After receiving NORFLASH backup command and test parameters, the test software backups the appointed space data to the cache space and calculates FLASH read data check sum (8-bit accumulation sum), calculates the cache space check sum (8-bit accumulation sum) after the backup is finished, compares whether the check sum is consistent, if not, sets the command execution state as error check, and terminates the test.
FLASH Erase Programming test
Erasing the FLASH full space;
carrying out programming test on the designated area of the FLASH according to the programming type 1 (shown in Table 1);
read-back verification of programmed regions
Performing 2.1) -2.4) operations according to the programming type 2, 3 and 4 in a loop
Erase FLASH full space
FLASH data recovery
Resetting FLASH
Programming the data of the cache space to the appointed FLASH space
Calculating FLASH and cache data check sums (8-bit accumulated sums) and comparing whether the FLASH and the cache data check sums are consistent; table 1 is a FLASH programming data description table.
TABLE 1
Figure BDA0002341661260000041
The method is characterized in that a test scheme is designed aiming at a fault mode that NORFLASH chips are rarely short-circuited on the global bit lines, and the faults are checked and identified by the NORFLASH chips on the finished products in a CPU software reading and writing mode.
The invention has the advantages that:
the method covers the identification capability of the short-circuit fault mode of the original data line and address line, and simplifies the original full-space programming and verifying process.
The fault identification capability of the sector inter-bit line short circuit can be effectively screened, and the cover opening maintenance operation is not required.
Aiming at the products which are finished with production and software filling, the deep detection of the FLASH is finished under the condition that the states of software and hardware are not influenced.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims (6)

1. A software testing method for detecting NORFLASH memory global bit line short circuit fault is characterized by comprising the following steps:
FLASH data backup, including:
after receiving NORFLASH backup command and test parameters, the test software backups the specified space data to the cache space and calculates FLASH read data check sum, calculates the cache space check sum after the backup is finished, compares whether the check sum is consistent, if not, sets the command execution state as check error, and terminates the test;
a FLASH erase programming test comprising:
erasing the FLASH full space;
carrying out programming test on the designated FLASH area according to the programming type;
carrying out read-back verification on the programmed area;
circularly executing FLASH erasing programming test operation according to different programming types;
erasing the FLASH full space;
FLASH data recovery, including:
resetting the FLASH;
programming the data of the cache space to a designated FLASH space;
and calculating the checksum of the FLASH and the cache data, and comparing whether the checksum is consistent or not.
2. The software test method for detecting norfall memory global bit line short faults as claimed in claim 1, further comprising: caching the software in the FLASH into an external memory SDRAM, carrying out erasing operation on the whole space of the FLASH, and identifying the bit line short circuit fault in the sector by programming of a specific sequence and data verification after programming.
3. The software testing method for detecting the NORFLASH memory global bit line short circuit fault as claimed in claim 1 wherein the FLASH data backup, FLASH erase programming test and FLASH data recovery are performed in sequence according to the flow.
4. The software testing method for detecting NORFLASH memory global bit line short circuit fault as claimed in claim 1 wherein testing software receives NORFLASH backup command and test parameters, backups designated space data to cache space and calculates FLASH read data checksum as 8 bit cumulative sum.
5. The software test method for detecting NORFLASH memory global bit line short faults as claimed in claim 1 wherein after the backup is completed the cache space checksum is calculated as an 8 bit cumulative sum.
6. The software test method of detecting NORFLASH memory global bit line short faults of claim 1, wherein the FLASH and cache data checksums are calculated as 8 bit cumulative sums.
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