CN1577784A - Writing buffer-supporting FLASH internal unit testing metod - Google Patents
Writing buffer-supporting FLASH internal unit testing metod Download PDFInfo
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- CN1577784A CN1577784A CN 03150016 CN03150016A CN1577784A CN 1577784 A CN1577784 A CN 1577784A CN 03150016 CN03150016 CN 03150016 CN 03150016 A CN03150016 A CN 03150016A CN 1577784 A CN1577784 A CN 1577784A
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Abstract
The test method includes the following steps: first erasing the whole chip, then writing in loop walk 0 data block based on address order in buffering area writing mode until all the inner units are written, and finally reading back the data for checking. The method of the present invention can ensure test efficiency and perform complete test covering to FLASH faults, and is suitable for the test of FLASH unit supporting writing buffering in various fields.
Description
Technical field
The present invention relates to the FLASH memory, refer to a kind of method that the FLASH internal element of supporting to write buffering is tested especially.
Background technology
The fault of FLASH device mainly shows as following form:
(1) open circuit of lead or short circuit;
(2) address decoder can not correct addressing;
(3) multiple writing;
The data of (4) unit are subjected to the influence of the data of other unit or read-write operation and change;
(5) fail after writing to recover, can not get correct information when reading immediately;
(6) and then sense amplifier is read x ' time after reading a series of information x, does not have correctly response;
(7) FLASH can not keep the information that writes.
The basic structure and the fault form of expression in conjunction with FLASH can draw following fault model:
(1) fault in the memory cell array:
1. fixed logic fault (Stuck-at fault): the logical value of a unit does not change with any behavior of unit, is not subjected to the influence of remaining element yet, claims stuck-at fault again, and it comprises and is fixed as 1 or be fixed as 0 two kinds of situations (S-A-1 or S-A-0);
2. stuck-open fault (Stuck-open fault): the fault that open circuit causes;
3. state exchange fault (Transition fault): 0-〉1 or 1-0 state exchange has at least one not to be executed correctly;
4. data keep fault (Data-maintaining fault): memory cell can't keep a logical value to continue the regular hour;
5. state coupling fault (Coupling fault): and if only if unit j is in some particular state y (y ∈ 0, in the time of 1}), unit i be always some determined value x (x ∈ 0,1}), then claim unit i to be coupled in unit j.Coupled relation not necessarily has symmetry, also just says that unit i is coupled in unit j, might not also be coupled in unit I by unit j.
6. multiple Write fault (multiple access fault): to unit i write x (x ∈ 0,1}) cause unit j also to write x, 6. then claim unit i that multiple Write fault is arranged.Multiple Write fault not necessarily has symmetry.
(2) fault in the address decoding circuitry:
1. do not choose arbitrary memory cell;
2. choose selected cell, and chosen other unit.
Fault in the decoder can equivalence be the fault in the memory cell array.1. fault is equivalent to stuck-open fault, and 2. fault is equivalent to multiple Write fault.
(3) fault in the read-write logic:
1. input, one or more fixed logic faults in the output lead;
2. one or more stuck-open faults in buffer or the latch;
3. the state coupling fault between any two in buffer or the latch.
The fault of read-write in the logical circuit also can equivalence be the fault in the memory cell array.1. fault is equivalent to the fixed logic fault, and 2. fault is equivalent to stuck-open fault, and 3. fault is equivalent to the state coupling fault.
Can know by above analysis, the test of FLASH is equal to internal element test to FLASH, and the internal element of FLASH has mainly comprised following fault type: fixed logic fault, stuck-open fault, state exchange fault, data keep fault, state coupling fault and multiple Write fault.
Method of testing now commonly used is is all read and write one by one by word, does not consider the characteristics of this class FLASH that supports the compose buffer operation and adopts effective method of testing to improve testing efficiency.Method of testing according to routine is read and write the method for testing one by one by word, and its efficient is low-down, and a FLASH chip is carried out complete test may need tens of minutes, even more than one hour.And utilize the characteristic of compose buffer, and the testing time can be controlled in several minutes, can satisfy the requirement of testing efficiency better.
And utilize the compose buffer of FLASH to test, and need consider the particular form of this batch processing, simultaneously in conjunction with the characteristics of FLASH self, design effective test data.
Summary of the invention
In view of the shortcoming of above-mentioned prior art, the invention provides a kind of method of testing of supporting to write the FLASH internal element of buffering, guaranteeing that test imitates under the prerequisite of efficient, the fault of FLASH is compared complete test cover.
The FLASH internal element method of testing of buffering is write in support provided by the invention, comprise the following steps: that first full wafer wipes, write the data block of circulation walking 0 then by sequence of addresses, described write operation is to carry out according to the mode of compose buffer, after all internal elements had been write, readback data carried out verification again.
The described buffer operation of writing is once to write full buffering area.
Described is to begin to finish to location superlatively or begin to finish to lowest address from location superlatively from lowest address by sequence of addresses.
The data block of described circulation walking 0, the data of its each row are 0 except one, and it does everybody is 1 entirely, and wherein 0 position is that order moves, the circulation walking.
Described 0 position is that the next line data move to left one or more than lastrow data or move to right one or more.
The present invention can improve the fault coverage of test by the above-mentioned specific test data of structure, has particularly improved the detectability to multiple Write fault and basic coupling fault.
Embodiment
Part FLASH device is (as 28F160S5 and 28F320S5,28F128J3A, 28F320J3A and 28F640J3A, 28F320J5 and 28F640J5 etc.) support the read-write mode of compose buffer (Write Buffer), utilize Write Buffer technology to write the test speed that FLASH can improve FLASH significantly, but because the WriteMode of Write Buffer and common WriteMode have very big difference, so also difference to some extent of method of testing.
Because once write a buffering area, thus the speed of writing significantly improve, so, can adopt following method to supporting the FLASH write buffering to test:
Elder generation's full wafer is wiped, and begins to write the data of walking 0 successively to the highest (or minimum) end of address (EOA) from minimum (or the highest) address then, after all having write, and then reads back and carries out verification.Wherein write operation is undertaken by Write Buffer.Because the data that write are the mobile process of digital " 0 " circulation just, so here with this method of testing called after " circulation walking 0 algorithm ".
Illustrate now, suppose address space from 0000 to 1111, data wire is 3, and it is as follows then to write tables of data:
| The test address | Write data |
| ?????0000 | ??????110 |
| ?????0001 | ??????101 |
| ?????0010 | ??????011 |
| ?????0011 | ??????110 |
| ?????0100 | ??????101 |
| ?????0101 | ??????011 |
| ?????0110 | ??????110 |
| ?????0111 | ??????101 |
| ?????1000 | ??????011 |
| ?????1001 | ??????110 |
| ?????1010 | ??????101 |
| ?????1011 | ??????011 |
| ?????1100 | ??????110 |
| ?????1101 | ??????101 |
| ?????1110 | ??????011 |
| ?????1111 | ??????110 |
The characteristics of this method of testing are to carry out when writing the FLASH operation to carry out according to the mode of compose buffer, the data block that writes is the data block of circulation walking 0, just each line data is 0 except one, all the other everybody be 1 entirely, wherein 0 position is not fixed, but order moves, the form of circulation walking.
In the above-mentioned example, 0 position is that the next line data move to left one than lastrow data at every turn, in the practical operation, is not limited thereto, and can move to left also can move to right, and the figure place that moves is also unrestricted, can once only move one, also can once move two or multidigit more.
The present invention is because adopt walking 0 algorithm, so can effectively detect the short trouble of adjacent cells.Because the characteristics of FLASH device itself are: can only write digital " 0 ", can not write numeral " 1 ", could be " 1 " after wiping, so in structure test data process, more " 1 " and a spot of " 0 " appears, and the position of " 0 " changes, and can detect so more to cause " 1 " to be write as the fault of " 0 " by mistake because of short circuit.
Claims (7)
1, a kind of FLASH internal element method of testing of supporting to write buffering, comprise the following steps: that first full wafer wipes, write the data block of circulation walking 0 then by sequence of addresses, described write operation is to carry out according to the mode of compose buffer, after all internal elements had been write, readback data carried out verification again.
2, the FLASH internal element method of testing of buffering is write in support as claimed in claim 1, it is characterized in that: the described buffer operation of writing is once to write full buffering area.
3, the FLASH internal element method of testing of buffering is write in support as claimed in claim 1 or 2, it is characterized in that: described is to be undertaken by the order that begins from lowest address to location end superlatively by sequence of addresses.
4, the FLASH internal element method of testing of buffering is write in support as claimed in claim 1 or 2, it is characterized in that: described is to carry out to the order that lowest address finishes by beginning from location superlatively by sequence of addresses.
5, the FLASH internal element method of testing of buffering is write in support as claimed in claim 1 or 2, it is characterized in that: the data block of described circulation walking 0, the data of its each row are 0 except one, and it does everybody is 1 entirely, and wherein 0 position is that order moves, the circulation walking.
6, the FLASH internal element method of testing of buffering is write in support as claimed in claim 5, it is characterized in that: it is one or more that described 0 position is that the next line data move to left than lastrow data.
7, the FLASH internal element method of testing of buffering is write in support as claimed in claim 5, and it is characterized in that: described 0 position is that the next line data are more one or more than lastrow data shift right.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031500161A CN100365787C (en) | 2003-07-29 | 2003-07-29 | Writing buffer-supporting FLASH internal unit testing metod |
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| CNB031500161A CN100365787C (en) | 2003-07-29 | 2003-07-29 | Writing buffer-supporting FLASH internal unit testing metod |
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| CN1577784A true CN1577784A (en) | 2005-02-09 |
| CN100365787C CN100365787C (en) | 2008-01-30 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101533673B (en) * | 2008-03-14 | 2012-07-04 | 海力士半导体有限公司 | Method of testing a non-volatile memory device |
| CN101770813B (en) * | 2008-12-31 | 2013-01-02 | 联咏科技股份有限公司 | Detection method for detecting interference phenomenon of adjacent blocks of non-volatile storage |
| CN103268267A (en) * | 2013-05-24 | 2013-08-28 | 北京航天自动控制研究所 | NANDFLASH bad sector dynamic label processing method based on blocks |
| CN104658613A (en) * | 2014-12-30 | 2015-05-27 | 中国电子科技集团公司第四十七研究所 | EEPROM durability test method and EEPROM durability test device |
| CN111563012A (en) * | 2019-12-27 | 2020-08-21 | 天津津航计算技术研究所 | Software testing method for detecting NORFLASH memory global bit line short-circuit fault |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5107501A (en) * | 1990-04-02 | 1992-04-21 | At&T Bell Laboratories | Built-in self-test technique for content-addressable memories |
| JPH03292700A (en) * | 1990-04-11 | 1991-12-24 | Nec Corp | Ram test system |
| JP3292700B2 (en) * | 1998-08-28 | 2002-06-17 | 株式会社ユニソン | Building blocks |
| CN1145972C (en) * | 2000-03-30 | 2004-04-14 | 华为技术有限公司 | Automatic test method and circuit for RAM |
-
2003
- 2003-07-29 CN CNB031500161A patent/CN100365787C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101533673B (en) * | 2008-03-14 | 2012-07-04 | 海力士半导体有限公司 | Method of testing a non-volatile memory device |
| CN101770813B (en) * | 2008-12-31 | 2013-01-02 | 联咏科技股份有限公司 | Detection method for detecting interference phenomenon of adjacent blocks of non-volatile storage |
| CN103268267A (en) * | 2013-05-24 | 2013-08-28 | 北京航天自动控制研究所 | NANDFLASH bad sector dynamic label processing method based on blocks |
| CN104658613A (en) * | 2014-12-30 | 2015-05-27 | 中国电子科技集团公司第四十七研究所 | EEPROM durability test method and EEPROM durability test device |
| CN111563012A (en) * | 2019-12-27 | 2020-08-21 | 天津津航计算技术研究所 | Software testing method for detecting NORFLASH memory global bit line short-circuit fault |
| CN111563012B (en) * | 2019-12-27 | 2023-09-26 | 天津津航计算技术研究所 | Software testing method for detecting NORFLASH memory global bit line short-circuit fault |
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| CN100365787C (en) | 2008-01-30 |
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