JP2008146255A - Storage device, computer system, and data processing method for storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device, a computer system and the data processing method of the storage device for easily determining whether data stored in a flash memory device are new or old, and for executing the reconstruction or wear leveling of a table in a simple system. <P>SOLUTION: A flash memory device 39 is provided with a plurality of blocks being independent erasure regions, and a write pointer circulating in a specific sequence on the address of the flash memory device 39 while detecting an erased unused block is set in a second memory 40. A control part 32 executes data writing in the flash memory device 39 along the write pointer, and records the association of the logical address of each data with the write pointer on a table on the second memory 40 according to the writing, and a counter value uniquely corresponding to the number of times of circulation of the write pointer is described with the data in the flash memory device 39. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a storage device including a non-volatile memory, a computer system, and a data processing method for the storage device.

  In recent years, flash memory has attracted attention as a storage medium for digital still cameras and mobile computer devices.

Flash memory is a semiconductor memory that uses tunneling or hot electron acceleration to pass electrons through a gate insulating film, inject them into a floating gate or trap layer, and store data by changing the threshold value of a cell transistor. . Since a memory cell can be configured with only one transistor using a stacked gate structure, an MNOS structure, or the like, an inexpensive and large-capacity memory can be realized.
A typical example is a NAND flash memory.

FIG. 1 is a diagram illustrating an internal configuration example of a NAND flash memory.
In the NAND flash memory of FIG. 1, a plurality of memory units 1-1 to 1-n connected to bit lines BL1 to BLn are arranged in an array (vertically and horizontally).
For example, the gate of the selection transistor 2 is connected to the selection gate line SL1, and the gate of the selection transistor 3 is connected to the selection gate line SL2. The gates of the memory cells N0 to N15 are connected to the word lines WL0 to WL15.

  Each of the memory cells N0 to N15 has a stacked gate structure, and stores data according to the charge accumulation amount in the floating gate. That is, if many electrons are accumulated in the floating gate, the threshold value of the transistor rises. Therefore, whether or not current is passed from the charged bit lines BL1 to BLn to the memory units 1 (-1 to -n) is checked. The data is determined by detection by the access circuit 4 including a sense amplifier.

  Such a NAND flash memory is not particularly required to provide a contact area to the bit line for each memory cell, and is particularly suitable for a medium of a large capacity and inexpensive storage device.

  By the way, generally, the programming speed of the flash memory is very slow and requires several hundred micro (μ) seconds per cell. Further, since data cannot be overwritten, it is necessary to erase data prior to programming, which takes several milliseconds. Such a problem is dealt with by processing many memory cells in parallel.

  That is, for example, by simultaneously writing the memory cell group 5 connected to the same word line WL0 and forming a page unit at the same time and further erasing all the cell blocks 6 formed of page groups sharing the memory unit with each other. The program transfer speed has been improved.

  Specifically, for example, Non-Patent Document 1 discloses a 1 Gb NAND flash memory, which has a page size of 2 kbytes and an erase block size of 128 kB. That is, a 128 kbyte memory cell group is erased in parallel in one memory array, and the memory cells are programmed in parallel every 2 kbytes, thereby realizing a program transfer rate of 10 MB / s.

Each page of the normal NAND flash has a 64-byte spare area for a user data storage area of 2 kbytes, for example.
In the spare area, various management data such as parity bits can be stored on the system side using the NAND flash. This writing to the spare area usually needs to be performed at the same time as writing to the user data area, and both are always handled as a set.

By the way, a restriction to be noted in using the flash memory is that an upper limit of the number of erasures is defined.
If rewriting of the same block is repeated and the number of erasures exceeds the upper limit value, data retention in the block cannot be guaranteed. For example, the upper limit of the number of erases of the NAND flash is 100,000 times or less.
In the future, the threshold variation of the cell transistor will increase with the miniaturization of the memory cell, and the operation margin will deteriorate, so that the upper limit of the number of times of erasing tends to decrease further.

  Further, due to changes in internal structure and writing mechanism accompanying miniaturization in recent years, the following restrictions tend to be imposed on NAND flash in particular.

First, the writing order of each page in the block is restricted.
That is, writing of each page is restricted in the forward direction from the lower address to the upper address, and writing in the reverse direction is prohibited. For example, once writing is performed on some page, data cannot be written there even if the lower address in the same block is not yet written.

Furthermore, multiple writing of each page has become difficult. That is, data in the same page cannot be written in two steps. Therefore, it is not possible to use various techniques previously used for flash memory management, such as pre-marking some bits in the spare area before writing data to each page, or setting a flag in the spare area after writing data. It is becoming.
ISSCC2002 Proceedings p106, Session 6.4 JP-A-8-328762

In recent years, an alternative to flash memory is expected to solve problems such as the power consumption of a hard disk, the length of seek time, impact resistance, and portability.
However, as described above, the flash memory has a drawback that the speed cannot be increased unless the access unit is increased. Also, since data cannot be overwritten, erasure is always required for rewriting, and the erase block at that time is even larger. The reason why the erase unit is several tens of times larger than the access unit in this way is a general specification for a flash memory in which the erase time is long and disturbance occurs in unselected cells during writing.

A write-once type storage system has been proposed to cope with such flash memory specifications and to rewrite small data at high speed.
In such a system, rewriting is performed by adding update data to an empty area and invalidating the original data.
More specifically, an address conversion table for associating a logical address with a physical address for each page is used, and rewriting is performed by changing the physical address of the reference data and adding it to an empty area of the storage medium.

  For example, Patent Document 1 describes details of a management method in a write-once storage system using an address conversion table. An example is shown in FIG.

  In FIG. 2, 21 indicates a block, 22 indicates a page area, 23 indicates a page buffer, 24 indicates an erased empty block, 25 indicates an address conversion table, and 26 indicates a page area.

From the address conversion table 25, a physical page address (Physical Page Address = PPA), which is an address on the flash memory of the corresponding page, can be obtained using the logical page address (Logical Page Address = LPA) as an index.
For example, for the write to the logical page address “0x5502” designated by the host, the address conversion is performed in page units using the address conversion table, and the physical page address “0x6B05” on the flash memory is acquired. As a result, the corresponding page area 22 in the block 21 is accessed.

  On the other hand, when updating the same page, an appropriate empty page area to be directly written in the flash memory is searched. For example, when the first page area 26 of the erased empty block 24 corresponding to the physical block address “0xAA” is selected as an appropriate write destination, only the data in the page area 22 is updated via the page buffer 23 and the page area 26 is updated. Is written to. At this time, the logical page address “0x5502” is remapped to the physical address “0xAA00” of the page area 26. The old data on the page area 22 is left as it is for the time being and is treated as invalid.

When the invalidated pages are accumulated, the storage area of the storage is compressed. Therefore, a block including many pages invalidated in a timely manner is selected, and the recovery process is performed there.
Specifically, only the valid page is copied to another block before erasure, the physical address written in the conversion table is rewritten accordingly, and finally the original block is erased. These operations are performed when the storage device is waiting or when the system is idle, so that the overhead can be hidden from the user.

  If such management is performed, as long as an empty area exists in the flash memory, data for one page may be written for each page data update. Therefore, rewriting can be performed at high speed. Since there is no need for erasure during that time, the number of times the flash memory is rewritten can be greatly reduced, and its life can be improved.

By the way, in such a storage device, it is often necessary to determine whether each data is new or old in its internal management.
For example, as means for determining that old data after being updated is invalid, a flag is set in the form of additional writing in the redundant portion of the invalidated page area.

  However, in recent flash memories such as NAND type, it is not possible to write data in a page area that has been written once. Therefore, at the same time as the data writing, it is necessary to describe some history in the redundant portion of the same page area so that it can be distinguished from the updated data.

The new / old determination of stored data can also be used for work called wear leveling. This is means for adjusting the number of erasures of each block in the memory to be uniform.
The data stored in the flash memory is a mixture of static data with a very low rewrite frequency such as an application program or operating system (OS) and dynamic data with a high rewrite frequency such as user data.
The block in which the former is stored hardly generates invalid pages, but the latter block is rewritten frequently, and invalid pages are likely to occur.
Here, when the latter block is subjected to a recovery process, they are released again as storage areas, and the possibility that dynamic data is stored again increases. On the other hand, the former block is left without being rewritten at all. In this way, rewriting and erasing are concentrated only on the latter, and there is a concern that the upper limit of the number of erasures may be exceeded and a defect may occur.

If a block that has not been rewritten for a long time can be discriminated, it is possible to contribute to the uniformization by releasing the block and providing it as a new data writing area.
However, no appropriate index has been proposed so far for determining whether the stored data is new or old.

  The present invention can easily determine whether data stored in a flash memory device is new or old, can perform table reconstruction and wear leveling with a simple system, and can improve the reliability of stored data. To provide a storage device, a computer system, and a data processing method for the storage device.

  A storage device according to a first aspect of the present invention includes a flash memory device as a main storage medium, a second memory, and a control unit that controls the flash memory device and the second memory. Each device has a plurality of blocks that are independent erase areas, and a write pointer that circulates in a prescribed order over the address of the flash memory device while detecting an erased unused block in the second memory. The control unit performs data writing to the flash memory device along the write pointer, and associates the logical address of each data with the write pointer with the second memory along with the writing. Record in the table above, the flash memory device is unique to the number of circulation of the write pointer The corresponding counter value, described with the data.

  Preferably, the counter value is used for new / old determination of each data in the internal management of the apparatus or system.

  Preferably, it has a function of autonomously selecting an unerased block based on at least the number of times, moving the data of the block to an arbitrary erased area, and further erasing the block.

  Preferably, the control unit performs the operation according to a certain amount of write data.

  Preferably, the control unit has a function of describing a logical address together with data in the flash memory device and reconstructing the table from the logical address and counter value corresponding to each data.

  According to a second aspect of the present invention, a flash memory device as a main storage medium, a second memory, a control unit for controlling the flash memory device and the second memory, and data in the flash memory device can be accessed. And the flash memory device has a plurality of blocks, each of which is an independent erase area, and detects an unused block erased in the second memory, and detects the address of the flash memory device. A write pointer that circulates in a prescribed order is installed, and the control unit performs data writing to the flash memory device along the write pointer, and the logical address of each data and The correspondence with the write pointer is recorded in the table on the second memory, and the flash memory is recorded. The DEVICES, the counter value uniquely corresponds to the circulation frequency of the write pointer, described along with the data.

  According to a third aspect of the present invention, there is provided a data processing method for a storage device having a flash memory device and a second memory as main storage media, wherein the flash memory device includes a plurality of blocks each being an independent erase area. A write pointer that circulates in a prescribed order on the address of the flash memory device while detecting an unused block that has been erased in the second memory. Writing is performed along the write pointer, and the correspondence between the logical address of each data and the write pointer is recorded in the table on the second memory along with the writing, and the write pointer is stored in the flash memory device. The counter value uniquely corresponding to the number of circulations is described together with the data.

According to the present invention, data writing is executed according to a write pointer that circulates in the flash memory in a fixed order, and a counter value corresponding to the cumulative number of laps is written in the redundant area of the flash memory together with each data.
Since the same writing order in the circulation is predetermined, the old and new during that time can be determined based on that, and the new and old during each lap can be determined by comparing the counter values. As a result, it is possible to determine whether data is new or old on a page basis.
Furthermore, by utilizing this index, wear leveling is executed by releasing blocks that have not been rewritten for a long time. Alternatively, when the address conversion table disappears due to an instantaneous power interruption or the like, it is used for valid data determination at the time of reconstruction.

  According to the present invention, it is possible to easily determine whether a page stored in a flash memory is new or old, and use this to perform table reconstruction and wear leveling with a simple system. As a result, the reliability of data stored in the storage device or system can be greatly improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 3 is a diagram illustrating a configuration example of a computer system that employs the storage device according to the embodiment of the present invention.

This computer system COMSYS has a storage device 30 and a host system (processing device) 50 as main components.
The storage device 30 includes an interface circuit (I / F) 31, a control circuit 32, an internal bus 33, a page buffer 34, NAND flash memories 35 and 36, a control circuit 37, and a memory bus 38.
The control circuit 32 includes a RAM 40 as a second memory, and a working area 41 is provided in the RAM 40. An address conversion table 42, a search table 43, an invalid counter table 44, a write pointer 45, and a write pointer circulation counter 46 are provided. Has been built.
The host system 50 includes a CPU, RAM, ROM, system bus, and the like.

Inside the storage device 30, two-chip 8 Gb NAND flash memories (sometimes referred to as flash memory chips) 35 and 36 having 16-bit input / output are connected in parallel to a 32-bit memory bus 38. The two chips are accessed simultaneously in parallel for reading and writing. That is, the memory bus 38 has a configuration including two channels of 16-bit buses. Each flash memory performs write or read access in units of 4 kB pages, for example. Therefore, 8 kB is collectively accessed as the actual page size.
The page buffer 34 temporarily stores data of the accessed page area. Data transmission / reception between the flash memories 35 and 36 and the page buffer 34 is controlled by a control circuit 37.
Furthermore, the control circuit 37 performs error correction by ECC encoding on the transfer data as necessary, and manages defective blocks in the flash memory. Both flash memories 35 and 36 input / output data to / from the internal bus 33 of the storage device via the page buffer 34.
That is, the circuit group of the page buffer 34, the NAND flash memories 35 and 36, the control circuit 37, and the memory bus 38 substantially constitutes one flash memory device (sometimes referred to as a flash memory module) 39, and the storage device It can be regarded as being connected to 30 internal buses 33. The total capacity is 16 Gb (2 GB), and the actual page size is 8 kB. That is, 256k pieces of page data are stored in the apparatus.

Further, an interface circuit 31 and a control circuit 32 are connected to the internal bus 33.
The interface circuit 31 transmits and receives data and commands to and from the host system 50 in accordance with standards such as ATA and PCI express.
The control circuit 32 manages data transmission / reception between the page buffer 34 and the interface circuit 31 inside the storage device.
The RAM 40 built in the control circuit 32 is provided with a code area and a working area 41 for executing a program, and further searches an address conversion table 42 that manages virtual addresses in units of pages, and normal empty blocks. A search table 43, an invalid counter table 44 for managing the number of invalid pages in each block, a write pointer 45, a write point circulation counter 46, and the like are constructed.

In the computer system COMSYS, the host system 50 is controlled by a built-in CPU, and stores user data in the flash memory device 39 via the storage device 30 in response to a request from an application or an operating system (OS).
The control circuit 32 intervenes in the data exchange between them, and performs access management with address conversion using the address conversion table 42 and the like.

The storage device 30 uses a 512-byte sector as an access unit in the same manner as the hard disk.
For simplicity in the storage device, it is assumed that hexadecimal addresses are allocated as follows.
For example, when the external input address is “0x05502C”, the upper 24 bits “0x05502” are page addresses, and a maximum of 1M pages can be managed. On the other hand, “0xC” of the lower 4 bits is a sector address in the page area, and 16 sectors are included in one page.
This storage device allows random access in units of one sector by selecting data in the page buffer 34.

Hereinafter, the internal operation of the storage device 30 will be described.
In this embodiment, page-by-page virtual address management is employed.

  FIG. 4 is a diagram illustrating a configuration example of the address conversion table 42, the search table 43, and the invalid counter table 44. FIG. 5 is a diagram showing a flow of data access using such a table. The specific access to the flash memory device 39 inside the storage device 30 is executed in the following procedure according to the flowchart of FIG.

<Data read operation>
Step ST1 :
When the sector address “0x005502C” is input from the host system 50 together with the user data access command, the control circuit 32 refers to the address conversion table 42 using the logical page address part LPA “0x005502” as an index, and the user data to be accessed The physical page address (PPA) “0x0060B0” is acquired.

Step ST2 :
The flash memory device 39 is accessed with the physical page address, and a page group in which user data is stored in the page buffer 34 is read. Thereafter, a portion corresponding to the sector address “0xC” is selectively output from the page buffer 34 to the host, and the read operation is completed.
Furthermore, the data is updated as follows. Assume that the same sector “0x005502C” is updated.

<Data update (write) operation>
Steps ST1 and ST2 :
As in reading, the desired data read from the flash memory device 39 is stored in the page buffer 34.

Step ST3 :
Update the desired sector location on the page buffer.

Step ST4 :
A physical page address PPA of an appropriate page area is selected from the search table 43 and the write pointer 45 resident in the RAM 40 as a writing destination of the updated user data to the flash memory device 39.

Details of the procedure will be described below. Here, for simplicity, it is assumed that the physical page address is composed of an upper 16-bit physical block address part (Physical Block Address: PBA) and a lower 8-bit page offset part. At this time, each erase block is composed of 256 pages (2 ⁸ ). The search table 43 is marked with “Used Flag” as to whether each block is currently being used or has been erased. Further, in the case of a defective block, “Defect Flag” is “1”.

  First, the write pointer 45 circulates while searching for a good erased block from the lower order to the higher order in the address of the search table 43 according to the increment of the physical block address portion. Once the target block is detected, “1” is set in a predetermined “Used Flag” of the search table 43, and the first page is first selected as the write destination.

  Further, from this point, the write destination pages are sequentially selected from the lower address according to the increment of the page offset portion. When the selection reaches the end of the block, the search for the next unused and non-defective block is advanced in accordance with the increment of the physical block address portion.

  In this way, the write pointer 45 circulates over the address of the flash memory device 39. When the block at the end address of the search table 43 is reached, or when the end page is reached, the circulation counter 46 is incremented by one and the head address is returned again.

  The value of the write pointer 45 is currently “0x00AA01”, and the control circuit 32 first selects the physical page address “0x00AA02” obtained by incrementing it as the user data write destination.

Step ST5 :
The flash memory device 39 is accessed with the physical page address, and user data in the page buffer 34 is written to the flash memory device 39 at once. At the same time, the counter value “0x000352” of the circulation counter 46 and the logical page address “0x005502” of the data are written in the redundant portion in the page area.
When the writing is completed, the address conversion table 42 is updated, and the physical page address PPA corresponding to the logical page address LPA “0x005502” is updated to “0x00AA02”.

Step ST6 :
As a result, the page area corresponding to the old physical page address “0x0060B0” becomes invalid. Therefore, in response to the generation of the invalid page, the counter value corresponding to the physical block address “0x0060” in the invalid counter table 44 is incremented from “0x10” to “0x11”.

By the way, when write-once writing as described above is performed, the page area corresponding to the physical page address “0x0060B0” in which the data before update is stored is deleted from the physical address field of the address conversion table 42 and can be accessed from the outside. Disappear. That is, it is invalidated.
However, data is written in them and cannot be used as a free area as it is. If the rewriting as described above is repeated many times, many invalid page areas are generated. They must be erased and recovered so that they can be used again as free space. In this case, other valid data remaining in the erase block “0x0060” needs to be saved.

  In such a recovery process, for example, valid data in the target block is first read into the page buffer in the same manner as in the update, and then written in the empty area of another block, thereby substantially saving. Should be done. That is, by temporarily updating the valid page, all the original areas are invalidated. Thereafter, the recovery process is performed by erasing the target block.

  6A to 6C conceptually illustrate a procedure for saving valid data in the erase blocks 51 and 52 and substantially restoring an invalid page area.

Step ST11 :
As described above, rewriting by additional writing proceeds, and after the data is once written in the erasure blocks 51 and 52, the page area groups 56 and 58 invalidated by updating are changed to valid page area groups 55, 57, and 59. And coexist.
Here, it is necessary to restore the invalidation area to a free area while leaving the data of the valid page area.
On the other hand, 53 and 54 are currently selected by the write pointer 45 and indicate erase blocks used as free space for additional writing, and the page area 60 has been written.

Step ST12 :
Data in valid page area groups 55, 57, and 59 is copied to the empty page area groups 61, 62, and 63 in the erase blocks 53 and 54 in order, and copied in order.
On the other hand, invalid page area groups 56 and 58 are not copied. Whether each page is valid / invalid is determined by, for example, writing a logical page address in the redundant part at the time of data writing and checking whether the correspondence between the page and the physical page address matches the address conversion table 42. carry out.
In the case of a valid page, the entire data in the target page is read into the page buffer 34, and the erase blocks 53 and 54 are written according to the increment of the write pointer. At this time, in the redundant area of each page, the logical address and the counter value of the circulation counter 46 are written as in the normal data writing.
Further, the address conversion table 42 is updated. That is, the physical page address of the copy destination is registered in the physical address field corresponding to the logical address of each page area. As a result of this work, the original page areas 55, 57, and 59 are invalidated. Therefore, the counter value of the corresponding block in the invalid counter table 44 is incremented for each page processing.
This operation is equivalent to the operation of rewriting the effective page area group 55, 57, 59 by the additional recording method.
Actually, only copying is performed without rewriting, but all pages in the erase blocks 51 and 52 are invalidated by this work, and data in the valid page area is substantially saved in the erase blocks 53 and 54.

Step ST13 :
Erase blocks 51 and 52 are erased. Accordingly, the “Used Flag” of the corresponding block in the search table 43 is reset to zero. The counter value of the corresponding block in the invalid counter table 44 is also reset to zero. As a result, all the inside becomes an empty area and can be used for later appending.
With this, the invalid areas 56 and 58 are effectively recovered.

  As described above, the invalid page area recovery process includes a saving process by copying each valid page area and erasing the original erase block. In addition, if a dummy update is performed on the valid page in the erase block to be recovered in the same procedure as the normal update process, and then the page is saved, the effective page save during the recovery process is restored to the normal write algorithm. Can be integrated. In this case, not only the control is facilitated, but also various measures for improving the reliability of writing such as uniform writing to the flash memory can be applied to the recovery processing, and the overall storage device Reliability can be improved.

  The above recovery processing can be concealed from the user by executing it during standby of the storage device or when the system is idle. In this case, for example, the storage device 30 is provided with a function of automatically executing the recovery process when the standby state is entered, or the host system 50 transmits a recovery process command when the system enters the idle state, and stores it accordingly. The device 30 executes a recovery process. At this time, a function for selecting a target block for recovery processing is required. For example, a part or all of the invalid counter table 44 is scanned, and a block with many invalid pages is searched for as a recovery target. Thus, efficient recovery processing can be performed.

  By the way, since the address conversion table 42 is stored in the RAM 40, there is a possibility that the address conversion table 42 may be lost due to an instantaneous power interruption. If this does not exist, user data cannot be accessed itself, which is fatal. Therefore, a mechanism and procedure that can reconstruct them are required.

  FIG. 7 is a diagram for explaining the address conversion table reconstruction process.

In FIG. 7, reference numeral 65b denotes a redundant portion in each page of the flash memory device 39. The redundant portion of each page stores a corresponding logical address 66b, a counter value (67b) of the circulation counter 46, and an 8-bit status flag 68b. These are simultaneously written in the redundant portion of the same page when user data is written.
Note that the status flag indicates the status of each page, and all the bits of the erased unused page are “1”, so “0xFF”. When data is written to the page, “0x00” is simultaneously written to this flag. If an intermediate value that is neither one of the left is described in this flag, the block to which the page belongs is defective. This is marked in advance at the time of shipment of the apparatus, or marked when writing or erasing fails.

  Here, all pages of the flash memory device 39 are scanned in order from the lower physical address, and the redundant portion is read. The search table 43b can be reconstructed from the status flag 68b of each page. Further, by acquiring the logical address 66b, the correspondence between the logical address and the physical address is understood, and the address conversion table 42b can be reconstructed.

  However, when there is a page that has been updated and invalidated, the logical address written on the page overlaps with the logical address of the newly written page after the update. In this case, the circulation counter value (67b) is compared, and the larger one is determined to be newer. If this is the same value, it is determined that the page of the higher physical address is new from the order of progress of the write pointer.

  The correspondence between the logical address and the physical address is correct for the newest page, and all other pages with overlapping logical addresses are invalid pages. By making this determination for all pages, the invalid counter table 44b can also be reconstructed.

  For example, as a result of the data update described above with reference to FIG. 4, in the redundant part 65b of FIG. Duplicate. In this case, when the circulation counter values are compared, the latter is newer data, and the correspondence of the latter is reflected in the address conversion table 42b. On the other hand, the former is determined to be an invalid page, and the invalid counter value of the corresponding block “0x0060” of the invalid counter table 44b is incremented by one.

  Next, the wear leveling operation will be described with reference to FIG.

  In FIG. 8, reference numeral 65 c denotes a circulation counter value written in the redundant portion 65 b in each page of the flash memory device 39. The redundant part 65b also includes other logical addresses, status flags, etc., which are omitted in this figure. For data writing, a target empty page is selected by the search table 43c and the write pointer 45c. Writing has been performed up to the last page of the physical block address “0x0140”, and the next erased block is “0x0141”.

  On the other hand, 70c represents a counter for the number of blocks to be written, and the counter 70c is incremented each time a new block is written. When data is written by the execution of the write command or the above-described recovery process and this counter reaches “0x40” or more, wear leveling is executed when the command execution is completed or when the next device is on standby or when the system is idle. That is, here, wear leveling is performed in accordance with data writing for 64 blocks.

  Since the current counter value is “0x3F” and the write pointer 45c is at the end of the block, the counter is incremented by the next data write, reaches “0x40”, and wear leveling is performed.

  Wear leveling refers to the lap counter values in a plurality of blocks, and selects a smaller value from the lap counter values as a target of recovery work. The circulation counter value is described in the redundant area of each page, and is the same value in the pages in the same block. For example, it can be referred to by reading the redundant area of the first page of each block. It can be seen that the smaller this value is, the older data is, that is, the block has not been erased for a long time.

Here, a wear leveling pointer 69 for searching the entire area of the flash memory device 39 by 16 blocks is provided. Each time 64 blocks are written and wear leveling is started, the redundancy area of the first page of 16 blocks is checked along with the increment of this pointer, and the used block with the smallest lap counter value is recovered. Selected as the target of
In the example of FIG. 8, when wear leveling is performed next, the first page of each block is read as PPA “0x006000”, “0x006100”, “0x006200”,. Is checked.

  When a block having a small circulation counter value is selected as a recovery target in this way, a recovery operation similar to that described with reference to FIG. 6 is executed. That is, the effective data of the target block is temporarily updated and moved to another block, and then the target block is erased. As a result, a block that has been static up to now is released as a new data storage destination.

  It should be noted that the wear leveling is desirably performed at such a frequency that the extra recovery processing associated therewith does not impair the usability of the apparatus or system. There are various variations on the execution timing, for example, every time the write pointer passes a specific address, or when a random number is generated when entering a standby or idling state, and when it is within a certain range.

  Further, in selecting the recovery target at that time, it is desirable that the entire flash memory device is inspected without any deviation, such as a cyclic inspection on the address by incrementing the pointer or the like, or determining the inspection target by a random number, etc. Various methods are conceivable. A block having a small circulation counter value is preferentially selected from the plurality of blocks inspected in this way.

  Up to this point, the case where various controls such as address conversion are implemented in an independent storage device has been described. However, the management of the address conversion table and related processing can also be performed under the control of the host side. Such a configuration is particularly suitable for an inexpensive computer system in which a flash memory is incorporated. An example of such a computer system is shown in FIG.

  FIG. 9 is a diagram illustrating a configuration example of a computer system that performs management of the address conversion table and related processing under the control of the host side.

In this case, the host system 80d includes a CPU 81d and a system memory 82d.
The CPU 81d is connected to a RAM 82d, which is a system memory, via a 32-bit system bus 83d. Further, a bridge circuit 84d is connected to the system bus 83d, and two-chip NAND flash memories 35d and 36d having 16-bit input / output are connected in parallel to the 32-bit data bus 38d connected to the bridge circuit 84d. Has been. The two chips are accessed simultaneously in parallel for reading and writing. A page buffer 34d for temporarily storing the accessed page area is built in the bridge circuit 84d.

The bridge circuit 84d receives various commands from the CPU 81d and mediates data exchange between the flash memories 35d and 36d and the CPU 81d or the system memory 82d using the page buffer 34d. Further, error correction by ECC encoding is performed on the transfer data as necessary.
The command received by the bridge circuit 84d is, for example, access to a predetermined page of the flash memories 35d and 36d, erasing a predetermined block of the flash memory, copying to a specified address of the predetermined page, resetting the flash memory, and the like. .

On the other hand, a driver 86d for controlling the flash storage system is resident in the system memory 82d. The driver 86d receives access to the storage device from the OS or application, and converts the page address at the time of access with reference to the address conversion table 42d configured in the same memory.
When updating data, the write destination page address is determined with reference to the search table 43d and the write pointer 45d, and a write command to the flash memory is transmitted to the bridge circuit 84b together with the update data. Alternatively, when an updated and invalidated page is generated, it is reflected in the invalid counter table 44d.

  That is, in such a case, the host system 85d itself comprising the CPU 81d and the system memory 82d substitutes for the role of the control circuit 32 in FIG. 3, and manages the address conversion table and various related processes. That is, the driver 86d uses various tables and pointers, receives a logical address from the OS or application, generates a physical address PPA, and transmits a command to the bridge circuit 84d, thereby performing various accesses to the flash memories 35d and 36d. .

  For the address conversion table 42d, search table 43d, invalid counter table 44d, and write pointer 45d, for example, the same tables 42, 43, 44, and pointer 45 shown in FIG. 5 are used.

  The concept of the present invention can be similarly applied to such a system. That is, the host system 80d is further provided with a circulation counter 46d in the RAM 82d. The write pointer 45d circulates over the addresses of the flash memories 35d and 36d in a predetermined order, and the number of turns is recorded in the counter 46d. The value is written in the redundant area of each page simultaneously with the data writing. Further, a logical page address and a status flag are described in each redundant area.

  When various tables in the RAM are lost due to an instantaneous power interruption of the system, the driver 86d reconstructs the various tables on the RAM using the data written in the redundant area of the flash memory. In particular, the address conversion table 44d is correctly reconstructed with reference to the logical address and the circulation counter value. The procedure is the same as that described in FIG.

  Further, the driver 86d performs wear leveling in response to writing a certain amount of data. At that time, with reference to the circulation counter value described in the redundant portion of the first page for a plurality of blocks, the block having the smaller value is preferentially set as the recovery target. Then, the valid page in the corresponding block is copied to an unused page in another block, and then the target block is erased to make it unused.

It is a figure which shows the example of an internal structure of a NAND type flash memory. It is a figure for demonstrating the write-in and mapping procedure in flash memory. It is a figure which shows the structural example of the computer system which employ | adopted the memory | storage device which concerns on embodiment of this invention. It is a figure which shows the structural example of an address conversion table, a search table, and an invalid counter table. 4 is a flowchart for explaining specific access processing to a flash memory device in a storage device. It is a figure which shows notionally the procedure which saves the effective data inside an erase block, and restore | restores an invalid page area | region substantially. It is a figure for demonstrating the reconstruction process of an address conversion table. It is a figure for demonstrating the operation | work of wear leveling. It is a figure which shows the structural example of the computer system which implements management of an address conversion table, and a related process by control by the host side.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 30 ... Memory device, 31 ... Interface circuit, 32 ... Control circuit, 33 ... Internal bus, 34 ... Page buffer, 35, 36 ... NAND type flash memory, 37 ... Control circuit 38... Memory bus 39 39 Flash memory device (flash memory module) 40. RAM 41. Working area 42 42 b 42 d Address conversion table 43 43b, 43d ..., search table, 44, 44b, 44d ... invalid counter table, 45, 45c, 45d ... write pointer, 46, 46d ... round counter, 50, 80d ... host system

Claims (11)

A flash memory device as a main storage medium;
A second memory;
A control unit for controlling the flash memory device and the second memory;
The flash memory device has a plurality of blocks each being an independent erase area,
In the second memory, a write pointer that circulates in a prescribed order on the address of the flash memory device while detecting an erased unused block is installed,
The control unit
Data writing to the flash memory device is performed along the write pointer, and the correspondence between the logical address of each data and the write pointer is recorded in the table on the second memory along with the writing, and the flash memory In the device, a counter value uniquely corresponding to the number of circulations of the write pointer is described together with data. The storage device according to claim 1, wherein the counter value is used for new / old determination of each data in internal management of the apparatus or system. The storage device according to claim 1, further comprising a function of autonomously selecting an unerased block based on at least the number of times, moving data of the block to an arbitrary erased area, and further erasing the block. The storage device according to claim 3, wherein the control unit executes the work according to a certain amount of write data. The storage device according to claim 1, wherein the control unit has a function of describing a logical address together with data in the flash memory device, and reconstructing the table from a logical address and a counter value corresponding to each data. A flash memory device as a main storage medium;
A second memory;
A control unit for controlling the flash memory device and the second memory;
A processing device capable of accessing the data of the flash memory device,
The flash memory device has a plurality of blocks each being an independent erase area,
In the second memory, a write pointer that circulates in a prescribed order on the address of the flash memory device while detecting unused erased blocks is installed,
The control unit
Data writing to the flash memory device is performed along the write pointer, and the correspondence between the logical address of each data and the write pointer is recorded in the table on the second memory along with the writing, and the flash memory A computer system in which a counter value uniquely corresponding to the number of circulations of the write pointer is described in the device together with data. The computer system according to claim 6, wherein the counter value is used for new / old determination of each data in internal management of the apparatus or system. The computer system according to claim 6, further comprising a function of autonomously selecting an unerased block based on at least the number of times, moving data of the block to an arbitrary erased area, and further erasing the block. The computer system according to claim 8, wherein the control unit executes the work according to a certain amount of write data. The computer system according to claim 6, wherein the control unit has a function of describing a logical address together with data in the flash memory device and reconstructing the table from a logical address and a counter value corresponding to each data. A data processing method for a storage device having a flash memory device as a main storage medium and a second memory,
The flash memory device has a plurality of blocks each being an independent erase area,
In the second memory, a write pointer that circulates in a prescribed order on the address of the flash memory device while detecting an erased unused block is installed,
Write data to the flash memory device along the write pointer,
Along with the writing, the correspondence between the logical address of each data and the write pointer is recorded in the table on the second memory,
A data processing method for a storage device, wherein a counter value uniquely corresponding to the number of circulations of the write pointer is described together with data in the flash memory device.

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