CN111524976A - 一种低栅电荷的功率mos器件及其制造方法 - Google Patents

一种低栅电荷的功率mos器件及其制造方法 Download PDF

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CN111524976A
CN111524976A CN202010352084.0A CN202010352084A CN111524976A CN 111524976 A CN111524976 A CN 111524976A CN 202010352084 A CN202010352084 A CN 202010352084A CN 111524976 A CN111524976 A CN 111524976A
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CN111524976B (zh
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乔明
王正康
董仕达
张波
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University of Electronic Science and Technology of China
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Abstract

本发明提供一种低栅电荷的功率MOS器件及其制造方法，M型栅极结构降低控制栅与分离栅电极之间的交叠面积，引入低k材料可降低隔离介质的介电常数，二者相结合可使器件寄生电容Cgs极大降低，提高器件开关速度，降低开关损耗。本发明包括衬底，衬底上表面有外延层，外延层中有控制栅槽，控制栅槽中包含栅电极、分离栅电极。栅电极为M型，位于控制栅槽的上半部分，且位于分离栅电极的上方，栅电极和分离栅电极通过低介电常数材料隔开，栅电极通过栅介质与外延层中的阱区隔开，分离栅电极位于控制栅槽的下半部分，且通过槽内介质与外延层隔开，该介质层也可为低介电常数材料。阱区内包含阱区电极，阱区上部为源区，源区与阱区电极通过金属相连并引出电极。

Description

一种低栅电荷的功率MOS器件及其制造方法
技术领域
本发明属于半导体技术领域，具体涉及一种低栅电荷的功率MOS器件及其制造方法。
背景技术
功率管理系统要求功率半导体器件具有低的导通电阻和寄生电容，以降低器件导通损耗和开关损耗。功率VDMOS因栅驱动功耗低，开关速度快，容易并联等特点被广泛应用于功率管理系统中。B.J.Baliga在U.S.Patent No.5,998,833中提出了分离栅深槽MOS器件结构。该结构利用分离栅电极屏蔽控制栅电极与外延层之间的电容耦合作用来减小栅漏寄生电容Cgd。此分离栅功率MOS器件结构的出现，既降低了阶梯氧化层(RSO)MOS器件中栅场板与外延层交叠引入的Cgd，又保留了栅场板对外延层的辅助耗尽作用。因此分离栅深槽MOS器件具有更低的栅电荷Qg，同时导通电阻Ron不退化，有利于功率管理系统开关特性和工作效率的提高。然而，分离栅深槽MOS器件中与源极连接的分离栅电极在降低器件Cgd的同时，也额外引入了栅极与分离栅电极之间的寄生电容Cgs，以及分离栅电极与漏极之间的寄生电容Cds，这使分离栅深槽MOS器件的输入电容Ciss(Ciss＝Cgs+Cgd)以及输出电容Coss(Coss＝Cds+Cgd)增大，一定程度地抵消了分离栅深槽MOS器件降低Cgd的优势。
因此，为了部分解决上述问题，有必要降低传统分离栅功率MOS器件中分离栅电极引入的寄生电容Cgs，本发明的实施例就是在这种背景下出现的。
发明内容
本发明提供一种低栅电荷的功率MOS器件及其制造方法，M型栅极结构降低控制栅与分离栅电极之间的交叠面积，低k介质的引入降低了隔离介质的介电常数，二者相结合可使器件寄生Cgs极大降低，利于器件开关速度的提高和开关损耗的降低。同时，在器件漂移区中引入N/P条，可以降低器件Ron。采用阶梯状的分离栅电极，还可以使器件漂移区电场分布更均匀，实现击穿电压BV的改善。
为实现上述发明目的，本发明技术方案如下：
一种低栅电荷的功率MOS器件，包括衬底10，衬底10上表面有外延层11，外延层11中有控制栅槽12，控制栅槽12中包含控制栅电极15、分离栅电极14，控制栅电极15位于控制栅槽12的上半部分且位于分离栅电极14的上方，控制栅电极15为M型，M型包含左右两侧的垂直段以及连接在两个垂直段中间的一个圆弧段，垂直段与栅介质100接触，栅电极15和分离栅电极14通过槽内介质13隔开，控制栅电极15通过栅介质100与外延层11中的阱区16隔开；分离栅电极14位于控制栅槽12的下半部分，分离栅电极14通过槽内介质13与外延层11隔开，阱区16内包含阱区电极17，阱区16上部为源区18，源区18与阱区电极17通过金属相连并引出电极。
作为优选方式，通过低介电常数材料131将控制栅电极15和分离栅电极14隔开。
作为优选方式，控制栅槽下半部分介质材料使用低介电常数材料131。
作为优选方式，低介电常数材料的介电常数低于3.9。
作为优选方式，器件漂移区中设置交替分布的N条和P条。
作为优选方式，器件分离栅电极14为阶梯型。
为实现上述发明目的，当通过低介电常数材料131将控制栅电极15和分离栅电极14隔开时，本发明还提供一种低栅电荷的功率MOS器件的制造方法，包括如下步骤：
1)在外延层上形成一系列的槽；
2)通过热氧化或者淀积二氧化硅在槽内形成介质层；
3)在槽内淀积多晶硅并回刻形成分离栅电极；
4)采用各向同性刻蚀，刻蚀槽内的介质层；
5)在槽内淀积低介电常数材料并回刻；
6)在槽内侧壁生长栅介质；
7)在器件表面淀积多晶硅，使槽内的多晶硅为U型；
8)采用各向异性刻蚀，只保留槽内侧壁栅电极；
9)淀积二氧化硅，并采用各向同性刻蚀进行回刻，使栅介质不被完全刻蚀；
10)淀积多晶硅并采用各向异性刻蚀，形成M型栅电极；
11)离子注入形成阱区和源区、淀积介质层、刻蚀介质层和硅层并离子注入形成阱区电极、引出电极。
本发明的有益效果为：将控制栅电极做成M形状，使栅电极与分离栅之间的介质层更厚从而完全分离开，增加了控制栅与分离栅的耦合距离，同时减小了控制栅与分离栅的耦合面积，有效降低了栅源电容。同时通过低k材料将栅电极与分离栅电极隔开，进一步降低了两者之间的耦合电容，从而有效降低了器件开启所需栅电荷。M型的控制栅利于电极引出，还可以缓解较窄的栅极引起的栅电阻增加问题。另外，槽下半部分介质材料也可以使用低介电常数材料，降低器件寄生电容Cds。
附图说明
图1为传统分离栅器件结构。
图2为本发明实施例1所提出的一种低栅电荷的功率MOS器件。
图3为本发明实施例2所提出的一种低栅电荷的功率MOS器件。
图4为本发明实施例3所提出的一种低栅电荷的功率MOS器件。
图5(a)-5(o)为图3的实施例2所提出的一种低栅电荷的功率MOS器件的主要工艺步骤。
图6对比了本发明所提出的结构与传统器件结构栅电荷特性的仿真结果。其中，直线①为如图1所示传统结构的栅电荷曲线，直线②为如图2所示本发明实施例1器件结构的栅电荷曲线，直线③为如图3所示本发明实施例2器件结构的栅电荷曲线。
其中，10为衬底，11为外延层，12为控制栅槽，13为槽内介质，14为分离栅电极，15为控制栅电极，16为阱区，17为阱区电极，18为源区，19为源极金属，100为栅介质，131为低介电常数材料。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
实施例1
如图2所示，本实施例提供一种低栅电荷的功率MOS器件，包括衬底10，衬底10上表面有外延层11，外延层11中有控制栅槽12，控制栅槽12中包含控制栅电极15、分离栅电极14，控制栅电极15位于控制栅槽12的上半部分且位于分离栅电极14的上方，控制栅电极15为M型，M型包含左右两侧的垂直段以及连接在两个垂直段中间的一个圆弧段，垂直段与栅介质100接触，栅电极15和分离栅电极14通过槽内介质13隔开，控制栅电极15通过栅介质100与外延层11中的阱区16隔开；分离栅电极14位于控制栅槽12的下半部分，分离栅电极14通过槽内介质13与外延层11隔开，阱区16内包含阱区电极17，阱区16上部为源区18，源区18与阱区电极17通过金属相连并引出电极。
实施例2
如图3所示，本实施例和实施例1的区别在于：通过低介电常数材料131将控制栅电极15和分离栅电极14隔开。低介电常数材料的介电常数低于3.9。
本实施例的一种低栅电荷的功率MOS器件的制造方法，包括如下步骤：
1)在外延层上形成一系列的槽；
2)通过热氧化或者淀积二氧化硅在槽内形成介质层；
3)在槽内淀积多晶硅并回刻形成分离栅电极；
4)采用各向同性刻蚀，刻蚀槽内的介质层；
5)在槽内淀积低介电常数材料并回刻；
6)在槽内侧壁生长栅介质；
7)在器件表面淀积多晶硅，使槽内的多晶硅为U型；
8)采用各向异性刻蚀，只保留槽内侧壁栅电极；
9)淀积二氧化硅，并采用各向同性刻蚀进行回刻，使栅介质不被完全刻蚀；
10)淀积多晶硅并采用各向异性刻蚀，形成M型栅电极；
11)离子注入形成阱区和源区、淀积介质层、刻蚀介质层和硅层并离子注入形成阱区电极、引出电极。
图6展示了本发明所提出的结构与传统器件结构栅电荷特性的仿真结果。其中，直线①为如图1所示传统结构的栅电荷曲线，直线②为如图2所示本发明实施例1器件结构的栅电荷曲线，直线③为如图3所示本发明实施例2的器件结构的栅电荷曲线。在仿真中，三种结构的尺寸、掺杂浓度等参数均相同。由图6可得，在相同条件下，本发明结构能有效降低器件开关所需的栅电容，缩短充电时间。
实施例3
如图4所示，本实施例和实施例1的区别在于：控制栅槽下半部分介质材料使用低介电常数材料131。
实施例4
本实施例和实施例1的区别在于：器件漂移区中设置交替分布的N条和P条。
实施例5
本实施例和实施例1的区别在于：器件分离栅电极14为阶梯型。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (7)

1.一种低栅电荷的功率MOS器件，其特征在于：包括衬底(10)，衬底(10)上表面有外延层(11)，外延层(11)中有控制栅槽(12)，控制栅槽(12)中包含控制栅电极(15)、分离栅电极(14)，控制栅电极(15)位于控制栅槽(12)的上半部分且位于分离栅电极(14)的上方，控制栅电极(15)为M型，M型包含左右两侧的垂直段以及连接在两个垂直段中间的一个圆弧段，垂直段与栅介质(100)接触，栅电极(15)和分离栅电极(14)通过槽内介质(13)隔开，控制栅电极(15)通过栅介质(100)与外延层(11)中的阱区(16)隔开；分离栅电极(14)位于控制栅槽(12)的下半部分，分离栅电极(14)通过槽内介质(13)与外延层(11)隔开，阱区(16)内包含阱区电极(17)，阱区(16)上部为源区(18)，源区(18)与阱区电极(17)通过金属相连并引出电极。
2.根据权利要求1所述的一种低栅电荷的功率MOS器件，其特征在于：通过低介电常数材料(131)将控制栅电极(15)和分离栅电极(14)隔开。
3.根据权利要求1所述的一种低栅电荷的功率MOS器件，其特征在于：控制栅槽下半部分介质材料使用低介电常数材料(131)。
4.根据权利要求2或3所述的一种低栅电荷的功率MOS器件，其特征在于：低介电常数材料的介电常数低于3.9。
5.根据权利要求1所述的一种低栅电荷的功率MOS器件，其特征在于：器件漂移区中设置交替分布的N条和P条。
6.根据权利要求1所述的一种低栅电荷的功率MOS器件，其特征在于：器件分离栅电极(14)为阶梯型。
7.权利要求2所述的一种低栅电荷的功率MOS器件的制造方法，其特征在于包括如下步骤：
1)在外延层上形成一系列的槽；
2)通过热氧化或者淀积二氧化硅在槽内形成介质层；
3)在槽内淀积多晶硅并回刻形成分离栅电极；
4)采用各向同性刻蚀，刻蚀槽内的介质层；
5)在槽内淀积低介电常数材料并回刻；
6)在槽内侧壁生长栅介质；
7)在器件表面淀积多晶硅，使槽内的多晶硅为U型；
8)采用各向异性刻蚀，只保留槽内侧壁栅电极；
9)淀积二氧化硅，并采用各向同性刻蚀进行回刻，使栅介质不被完全刻蚀；
10)淀积多晶硅并采用各向异性刻蚀，形成M型栅电极；
11)离子注入形成阱区和源区、淀积介质层、刻蚀介质层和硅层并离子注入形成阱区电极、引出电极。
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