CN111524903B - Goa阵列基板及制备方法 - Google Patents

Goa阵列基板及制备方法 Download PDF

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CN111524903B
CN111524903B CN202010328508.XA CN202010328508A CN111524903B CN 111524903 B CN111524903 B CN 111524903B CN 202010328508 A CN202010328508 A CN 202010328508A CN 111524903 B CN111524903 B CN 111524903B
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metal layer
goa
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insulating layer
array substrate
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CN111524903A (zh
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肖邦清
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to PCT/CN2020/089472 priority patent/WO2021212559A1/zh
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Abstract

本申请公开了一种GOA阵列基板及制备方法，所述GOA阵列基板包括衬底基板以及设于所述衬底基板上的GOA驱动电路，所述GOA驱动电路包括多个相连接的GOA单元，每一所述GOA单元包括薄膜晶体管阵列层、形成于所述薄膜晶体管阵列层上的第一金属层、设于所述第一金属层上的绝缘层以及设于所述绝缘层上的第二金属层；其中，所述第一金属层在与所述第二金属层跨线的位置具有图案化的信号线，所述信号线包括主干部及由所述主干部相对两侧形成的侧壁，所述侧壁设置为一弧状凹槽。本申请实施例能够防止第一金属层形成的信号线与第二金属层形成的信号线在跨线位置处短路，进一步提升了GOA阵列基板中GOA驱动电路的稳定性。

Description

GOA阵列基板及制备方法
技术领域
本申请涉及显示技术领域，尤其涉及一种GOA阵列基板及制备方法。
背景技术
随着液晶面板技术的不断发展，阵列基板行驱动(Gate Driver on Array，简称GOA)技术被广泛应用到液晶面板的电路设计中，为此，越来越多的相关电路走线也同样被集成到面板上。GOA技术是利用现有薄膜晶体管液晶显示器(Thin Film TransistorLiquid Crystal Display，简称TFT-LCD)的阵列制程将栅极行驱动电路制作在阵列(Array)基板上，实现对栅极逐行扫描的驱动方式的一项技术。GOA技术可以节省栅极芯片(Gate IC)，有利于显示屏栅极行驱动(Gate Driver)侧窄边框(narrow border)的设计和成本的降低，得到广泛地应用和研究。
在现有的GOA阵列基板的总线(Busline)设计中，会用跨线的方式把GOA驱动的时钟信号从总线上引入到GOA单元，GOA单元在跨线结束的位置容易由于此处第一金属层(M1)沉积的时候容易产生taper角(锥角)，使得此处的绝缘层沉积厚度不均一，比水平位置偏薄。当时钟信号(CK)处有高频信号时，在第一金属层(M1)和第二金属层(M2)间容易产生发热以及两者的电容效应容易击穿绝缘层，造成信号间的短路，触发显示面板设置的过电流保护，进而导致显示面板黑屏。有鉴于此，如何改善GOA阵列基板在GOA总线区的信号线经过跨线位置时第一金属层(M1)和第二金属层(M2)短路的几率，实为亟需解决的课题。
发明内容
本申请实施例提供一种GOA阵列基板及制备方法，能够有效降低GOA总线区的信号线经过跨线位置时第一金属层(M1)和第二金属层(M2)短路的风险，增加GOA驱动线路的稳定性，以解决现有技术的GOA阵列基板及制备方法，由于GOA单元中的第一金属层(M1)与第二金属层(M2)在跨线结束的位置时容易短路，触发过电流保护，进而导致显示器件黑屏的技术问题。
本申请实施例提供了一种GOA阵列基板，所述GOA阵列基板包括衬底基板以及设于所述衬底基板上的GOA驱动电路，所述GOA驱动电路包括多个相连接的GOA单元，每一所述GOA单元包括薄膜晶体管阵列层、形成于所述薄膜晶体管阵列层上的第一金属层、设于所述第一金属层上的绝缘层以及设于所述绝缘层上的第二金属层；
其中，所述第一金属层在与所述第二金属层跨线的位置具有图案化的信号线，所述信号线包括主干部及由所述主干部相对两侧形成的侧壁，所述侧壁设置为一弧状凹槽。
在一些实施例中，所述弧状凹槽由所述信号线采用半色调光罩并通过光刻图案工艺形成。
在一些实施例中，所述半色调光罩包括非全透光区，所述非全透光区具有多种光罩穿透率。
在一些实施例中，位于所述弧状凹槽上的部分所述绝缘层的厚度与位于所述主干部上的部分所述绝缘层的厚度相同。
在一些实施例中，所述绝缘层的材料为氮硅氮化物或者硅氧化物。
在一些实施例中，所述第一金属层的材料与所述薄膜晶体管阵列层的栅极金属层的材料相同；所述第二金属层的材料与所述薄膜晶体管阵列层的源漏极金属层的材料相同。
在一些实施例中，所述薄膜晶体管阵列层包括多条相互平行的扫描线，所述G0A驱动电路用于对多条所述扫描线进行驱动。
本申请实施例还提供一种如上所述的GOA阵列基板的制备方法，所述方法包括：
S10，在一衬底基板的GOA驱动电路区域上形成第一金属层，所述第一金属层位于所述GOA驱动电路区域的跨线位置具有图案化的信号线，所述信号线包括主干部及由所述主干部相对两侧形成的侧壁；
S20，使用半色调光罩并通过光刻图案工艺对所述侧壁进行蚀刻，形成弧状凹槽；
S30，在所述第一金属层上形成绝缘层，所述绝缘层填充所述弧状凹槽；
S40，在所述绝缘层上形成第二金属层。
在一些实施例中，所述S20中，所述半色调光罩包括非全透光区，所述非全透光区具有多种光罩穿透率。
在一些实施例中，所述S30中，位于所述弧状凹槽上的部分所述绝缘层的厚度与位于所述主干部上的部分所述绝缘层的厚度相同。
本申请实施例所提供的GOA阵列基板及制备方法，通过设计图案化的第一金属层形成的信号线，在与第二金属层形成的信号线的跨线结尾的位置设计一定弧度的凹槽，增加了此处绝缘层的沉积厚度，防止第一金属层形成的信号线与第二金属层形成的信号线之间的短路，进一步提升了GOA阵列基板中GOA驱动电路的稳定性。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的GOA阵列基板面板的GOA单元位于跨线处的截面结构示意图。
图2为本申请实施例提供的GOA阵列基板的制备方法流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本申请实施例针对现有技术的GOA阵列基板及制备方法，由于GOA单元中的第一金属层(M1)与第二金属层(M2)在跨线结束的位置时容易短路，触发过电流保护，进而导致显示器件黑屏的技术问题，本实施例能够解决该缺陷。
如图1所示，为本申请实施例提供的GOA阵列基板面板的GOA单元位于跨线处的截面结构示意图。从图中可以很直观地看到本申请实施例的各组成部分，以及各组成部分之间的相对位置关系。
具体地，所述GOA阵列基板包括衬底基板10以及设于所述衬底基板10上的GOA驱动电路，所述GOA驱动电路包括多个相连接的GOA单元20，每一所述GOA单元20包括薄膜晶体管阵列层21、形成于所述薄膜晶体管阵列层21上的第一金属层(M1)22、设于所述第一金属层(M1)22上的绝缘层23以及设于所述绝缘层23上的第二金属层(M2)24；
其中，所述第一金属层(M1)22在与所述第二金属层(M2)24跨线的位置具有图案化的信号线，所述信号线包括主干部221及由所述主干部221相对两侧形成的侧壁222，所述侧壁222设置为一弧状凹槽。
具体地，所述衬底基板10可以是玻璃基板，其中，所述玻璃基板材质均匀，具有高透明度和低反射率，并且有好的热稳定性，从而能在多次高温工艺之后保持性质稳定。本优选实施例不对所述衬底基板10进行限制，在制作所述GOA阵列基板时，工艺人员可以根据具体需要选择所述衬底基板10。
具体地，所述薄膜晶体管阵列层21包括多条相平行的扫描线(未标号)。所述G0A驱动电路用于对所述多条扫描线进行驱动，用于驱动所述GOA阵列基板的显示区域中像素的开启或关闭。
具体地，所述第一金属层(M1)22可以是多层金属形成的金属化合物导电层。所述第一金属层(M1)22通常通过气相沉积技术形成，然后经过蚀刻工艺等形成各种信号线。进一步地，所述第一金属层(M1)22的材料与所述薄膜晶体管阵列层的栅极金属层的材料相同。
进一步地，所述弧状凹槽由所述图案化的信号线采用半色调光罩并通过光刻图案工艺形成，所述半色调光罩包括非全透光区，所述非全透光区具有多种光罩穿透率。其中，采用所述半色调光罩对光阻材料进行曝光、显影及蚀刻的光刻工艺，使所述第一金属层(M1)22形成有图案化的信号线，且所述图案化的信号线位于GOA总线区的跨线位置。
具体地，所述绝缘层23覆盖在所述第一金属层(M1)22之上，所述绝缘层23可以为一层或两层，其可由硅氧化物、硅氮化物或者硅氮氧化合物形成。优选地，所述绝缘层23硅氮化物。其中，位于所述弧状凹槽上的部分所述绝缘层23的厚度与位于所述主干部221上的部分所述绝缘层23的厚度相同。
具体地，所述第二金属层(M2)24可以是多层金属形成的金属化合物导电层。所述第二金属层(M2)24通常通过气相沉积技术形成，然后经过蚀刻工艺等形成各种信号线。进一步地，所述第二金属层(M2)24的材料与所述薄膜晶体管阵列层的源漏极金属层的材料相同。
本申请实施例提供的GOA阵列基板，通过在GOA单元中第一金属层(M1)形成的信号线在经过跨线结尾的位置，制作出一定弧度的凹槽，增加此处绝缘层的沉积厚度，能有效防止第一金属层(M1)形成的信号线与第二金属层(M2)形成的信号线之间的短路，进而提升了GOA驱动电路的稳定性。
如图2所示并结合图1，为本申请实施例提供的所述GOA阵列基板的制备方法流程图，其中，所述方法包括：
S10，在一衬底基板10的GOA驱动电路区域上形成第一金属层22，所述第一金属层22位于所述GOA驱动电路区域的跨线位置具有图案化的信号线，所述信号线包括主干部221及由所述主干部221相对两侧形成的侧壁222。
具体地，所述S10还包括：
首先，提供一衬底基板10，所述衬底基板10上设置有薄膜晶体阵列层21，所述薄膜晶体管阵列层21包括多条相平行的扫描线(未标号)；之后，在所述衬底基板10的GOA驱动电路区域上沉积第一金属层(M1)22，所述第一金属层(M1)22位于所述薄膜晶体管阵列层21上。其中，所述第一金属层(M1)22可以是多层金属形成的金属化合物导电层。所述第一金属层(M1)22经过蚀刻工艺等形成各种信号线。进一步地，所述第一金属层(M1)22的材料与所述薄膜晶体管阵列层的栅极金属层的材料相同。
S20，使用半色调光罩并通过光刻图案工艺对所述侧壁222进行蚀刻，形成弧状凹槽。
具体地，所述S20还包括：
首先，使用半色调光罩并通过光刻图案工艺对所述侧壁222进行蚀刻，形成弧状凹槽。其中，所述弧状凹槽由所述图案化的信号线采用半色调光罩并通过光刻图案工艺形成，所述半色调光罩包括非全透光区，所述非全透光区具有多种光罩穿透率。进一步地，采用所述半色调光罩对光阻材料进行曝光、显影及蚀刻的光刻工艺，使所述第一金属层(M1)22形成有图案化的信号线，且所述图案化的信号线位于GOA总线区的跨线位置。
S30，在所述第一金属层22上形成绝缘层23，所述绝缘层23填充所述弧状凹槽。
具体地，所述S30还包括：
采用PECVD工艺(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积法)在所述第一金属层22上形成绝缘层23，所述绝缘层23填充所述弧状凹槽；所述绝缘层23可以为一层或两层，其可由硅氧化物、硅氮化物或者硅氮氧化合物形成。优选地，所述绝缘层23硅氮化物。其中，位于所述弧状凹槽上的部分所述绝缘层23的厚度与位于所述主干部221上的部分所述绝缘层23的厚度相同。
S40，在所述绝缘层23上形成第二金属层24。
具体地，所述S40还包括：
采用PVD(Physical Vapor Deposition)，物理气相沉积)工艺在所述绝缘层23上沉积第二金属层(M2)24。其中，所述第二金属层(M2)24可以是多层金属形成的金属化合物导电层。所述第二金属层(M2)24经过蚀刻工艺等形成各种信号线。进一步地，所述第二金属层(M2)24的材料与所述薄膜晶体管阵列层的源漏极金属层的材料相同。所述薄膜晶体管阵列层21、所述第一金属层(M1)22、所述绝缘层23以及所述第二金属层(M2)24形成GOA驱动电路中的GOA单元20，多个所述G0A单元20用于对连接所述薄膜晶体管阵列层21的多条扫描线进行驱动，用于驱动所述GOA阵列基板的显示区域中像素的开启或关闭。
综上所示，本申请实施例所提供的GOA阵列基板及制备方法，通过设计图案化的第一金属层形成的信号线，在与第二金属层形成的信号线的跨线结尾的位置设计一定弧度的凹槽，增加了此处绝缘层的沉积厚度，防止第一金属层形成的信号线与第二金属层形成的信号线之间的短路，进一步提升了GOA阵列基板中GOA驱动电路的稳定性。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种GOA阵列基板及制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (8)

1.一种GOA阵列基板，其特征在于，所述GOA阵列基板包括：
衬底基板；
GOA驱动电路，设于所述衬底基板上，所述GOA驱动电路包括多个相连接的GOA单元，每一所述GOA单元包括薄膜晶体管阵列层、形成于所述薄膜晶体管阵列层上的第一金属层、设于所述第一金属层上的绝缘层以及设于所述绝缘层上的第二金属层；
其中，所述第一金属层在与所述第二金属层跨线的位置具有图案化的信号线，所述信号线包括主干部及由所述主干部相对两侧形成的侧壁，所述侧壁设置为一弧状凹槽，位于所述弧状凹槽上的所述绝缘层的厚度与位于所述主干部上的所述绝缘层的厚度相同。
2.根据权利要求1所述的GOA阵列基板，其特征在于，所述弧状凹槽由所述信号线采用半色调光罩并通过光刻图案工艺形成。
3.根据权利要求2所述的GOA阵列基板，其特征在于，所述半色调光罩包括非全透光区，所述非全透光区具有多种光罩穿透率。
4.根据权利要求1所述的GOA阵列基板，其特征在于，所述绝缘层的材料为硅氧化物、硅氮化物或者硅氮氧化合物。
5.根据权利要求1所述的GOA阵列基板，其特征在于，所述第一金属层的材料与所述薄膜晶体管阵列层的栅极金属层的材料相同；所述第二金属层的材料与所述薄膜晶体管阵列层的源漏极金属层的材料相同。
6.根据权利要求1所述的GOA阵列基板，其特征在于，所述薄膜晶体管阵列层包括多条相互平行的扫描线，所述G0A驱动电路用于对多条所述扫描线进行驱动。
7.一种如权利要求1-6所述的GOA阵列基板的制备方法，其特征在于，所述方法包括：
S10，在一衬底基板的GOA驱动电路区域上形成第一金属层，所述第一金属层位于所述GOA驱动电路区域的跨线位置具有图案化的信号线，所述信号线包括主干部及由所述主干部相对两侧形成的侧壁；
S20，使用半色调光罩并通过光刻图案工艺对所述侧壁进行蚀刻，形成弧状凹槽；
S30，在所述第一金属层上形成绝缘层，所述绝缘层填充所述弧状凹槽，位于所述弧状凹槽上的所述绝缘层的厚度与位于所述主干部上的所述绝缘层的厚度相同；
S40，在所述绝缘层上形成第二金属层。
8.根据权利要求7所述的GOA阵列基板的制备方法，其特征在于，所述S20中，所述半色调光罩包括非全透光区，所述非全透光区具有多种光罩穿透率。
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