CN111524873B - 嵌入式封装模块及其封装方法 - Google Patents

嵌入式封装模块及其封装方法 Download PDF

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CN111524873B
CN111524873B CN201910105644.XA CN201910105644A CN111524873B CN 111524873 B CN111524873 B CN 111524873B CN 201910105644 A CN201910105644 A CN 201910105644A CN 111524873 B CN111524873 B CN 111524873B
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semiconductor device
positioning
layer
packaging
embedded
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CN111524873A (zh
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王增胜
郭雪涛
鲁凯
李辉
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Delta Electronics Shanghai Co Ltd
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Delta Electronics Shanghai Co Ltd
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Priority to US16/730,024 priority patent/US11552039B2/en
Publication of CN111524873A publication Critical patent/CN111524873A/zh
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Abstract

本公开是关于一种嵌入式封装模块，所述嵌入式封装模块包括：第一半导体器件、第一封装层和第一布线层，第一半导体器件具有第一面和第二面，所述第一半导体器件的第一面上设置有至少两个定位凸起和至少一焊盘；第一封装层形成于所述第一半导体器件的第一面及与所述第一面相邻的面，所述定位凸起位于所述第一封装层，所述第一封装层中设置有至少一第一过孔，所述第一过孔的底部位于所述焊盘内且与所述焊盘接触；第一布线层位于所述第一封装层远离所述第一半导体器件的一侧，通过所述第一过孔与所述焊盘电性连接。通过设置于第一半导体器件上的定位凸起，提高了第一过孔位置精度。

Description

嵌入式封装模块及其封装方法
技术领域
本公开涉及芯片封装技术领域，具体而言，涉及一种嵌入式封装模块及其封装方法。
背景技术
随着技术的发展和进步，芯片在各类电子产品中的应用越来越广泛，由于芯片功率和电流增大，导致芯片的尺寸增大，进而芯片的封装尺寸增大，对于芯片的封装可靠性带来严峻的考验。并且各类电子产品对于芯片的集成度要求越来越高，同时要求芯片具有更低的堆叠高度。
目前，为了增加芯片封装的可靠性，并且降低芯片堆叠高度，嵌入式封装结构成为一种芯片通常通过嵌入式结构封装。但是，在封装过程中由于制程精度等的影响，导致嵌入式结构封装的良品率和可靠性低。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种嵌入式封装模块及其封装方法，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的一个或者多个问题。
根据本公开的一个方面，提供一种嵌入式封装模块，所述嵌入式封装模块包括：
第一半导体器件，具有第一面和第二面，所述第一半导体器件的第一面上设置有至少两个定位凸起和至少一焊盘；
第一封装层，形成于所述第一半导体器件的第一面及与所述第一面相邻的面，所述定位凸起位于所述第一封装层，所述第一封装层中设置有至少一第一过孔，所述第一过孔的底部位于所述焊盘内且与所述焊盘接触；
第一布线层，位于所述第一封装层远离所述第一半导体器件的一侧，通过所述第一过孔与所述焊盘电性连接。
根据本公开的一实施方式，所述至少两个定位凸起中至少一所述定位凸起设置于所述焊盘。
根据本公开的一实施方式，所述至少两个定位凸起中的至少一所述定位凸起设置于所述焊盘，设置有所述定位凸起的所述焊盘上还设置有至少一所述第一过孔。
根据本公开的一实施方式，所述第一过孔与所述定位凸起在所述第一半导体器件的第一面的投影不重叠。
根据本公开的一实施方式，所述定位凸起被包覆于所述第一封装层，所述第一封装层上还设置有至少一第二过孔，至少部分的所述定位凸起设置于至少一所述焊盘，且所述第二过孔和设置于所述焊盘的所述定位凸起接触且在所述第一半导体器件的第一面的投影至少部分交叠。
根据本公开的一实施方式，所述第二过孔和所述第一布线层电性连接。
根据本公开的一实施方式，所述嵌入式封装模块还包括封装框架，具有容置区，所述第一半导体器件设置于所述容置区中。
根据本公开的一实施方式，所述第一半导体器件的数量为多个，且均设置于所述容置区中。
根据本公开的一实施方式，所述第一半导体器件的数量为多个，所述容置区的数量为多个，且每一所述容置区中设置有至少一所述第一半导体器件。
根据本公开的一实施方式，所述封装框架包含多个相互不连接的金属块，且至少一所述第一半导体器件通过所述第一过孔和至少一所述金属块电性连接。
根据本公开的一实施方式，所述嵌入式封装模块还包括封装框架，所述第一半导体器件和所述封装框架堆叠设置。
根据本公开的一实施方式，所述嵌入式封装模块还包括：
至少一第二半导体器件，具有第一面和第二面，所述第二半导体器件的第一面上设置有至少两个定位凸起和至少一个焊盘，所述第二半导体器件的第二面连接于所述第一布线层；
第三封装层，形成于所述第一布线层远离所述第一半导体器件的一侧，并且覆盖所述第二半导体器件，所述第二半导体器件的所述定位凸起位于所述第三封装层，所述第三封装层上设置有至少一第三过孔，所述第三过孔的底部位于所述第二半导体器件的所述焊盘的区域内且接触所述第二半导体器件的所述焊盘；所述第三过孔与所述第二半导体器件的所述定位凸起在所述第二半导体器件的第一面的投影不重叠；
第三布线层，形成于所述第三封装层。
根据本公开的一实施方式，所述嵌入式封装模块还包括：
第三半导体器件，所述第三半导体器件的第一面上设置有至少两个定位凸起和至少一焊盘，所述第一半导体器件的第二面和所述第三半导体器件的第二面通过一连接层连接；
第二封装层，形成于所述第三半导体器件的第一面及与所述第一面相邻的面，所述第三半导体器件的所述定位凸起位于所述第二封装层，所述第二封装层上设置有至少一第四过孔，所述第四过孔的底部位于所述第三半导体器件的所述焊盘的区域内且接触所述第三半导体器件的所述焊盘；所述第四过孔与所述第三半导体器件的所述定位凸起在所述第三半导体器件的第一面的投影不重叠；
第二布线层，位于所述第二封装层远离所述第一半导体器件的一侧，通过所述第四过孔和所述第三半导体器件的所述焊盘电性连接。
根据本公开的一实施方式，所述定位凸起暴露于所述第一封装层，所述定位凸起和所述第一布线层电性连接。
根据本公开的一实施方式，所述第一过孔是金属实心过孔。
根据本公开的一实施方式，所述第一布线层的数量为至少一层，所述第一半导体器件的第二面的一侧设置有至少一层第四布线层，第一布线层和所述第四布线层的层数相同。
根据本公开的另一个方面，提供一种嵌入式封装模块的封装方法，所述方法包括：
提供第一半导体器件，所述第一半导体器件的第一面具有至少一焊盘；
在所述第一半导体器件的第一面上设置至少两个定位凸起；
将第一封装层压合，且覆盖所述第一半导体器件的第一面及与所述第一面相邻的面；
通过激光钻孔工艺，在所述第一封装层上加工至少一第一过孔，其中，激光钻孔位置确认的模式识别点为所述第一半导体器件第一面上的定位凸起，以使得所述第一过孔的底部位于所述焊盘的区域内且接触所述焊盘，且使得所述第一过孔与所述定位凸起在所述第一半导体器件的第一面的投影不重叠；
对所述第一过孔填充金属；
形成第一布线层，所述第一布线层位于所述第一封装层远离所述第一半导体器件的一侧，且所述第一布线层通过所述第一过孔和所述焊盘电性连接。
本公开提供的嵌入式封装模块，通过在第一半导体器件的第一面上设置至少两个定位凸起作为加工时的定位点，提高在第一封装层加工第一过孔的位置精度，并且通过第一过孔实现电流流通的需求；由于过孔加工位置精度的提高，可以增加焊盘上过孔的数量以及过孔的直径，进一步提升过孔的电流的流通能力和散热能力，同时可以减小芯片焊盘上电流的横向流动距离，从而减小芯片内部电流损耗，进而提高封装的可靠性。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术提供的一种芯片封装结构的结构示意图。
图2为本公开示例性实施例提供的第一种嵌入式封装模块的结构示意图。
图3为本公开示例性实施例提供的嵌入式封装模块的一种定位凸起分布示意图。
图4为本公开示例性实施例提供的嵌入式封装模块的另一种定位凸起分布示意图。
图5为本公开示例性实施例提供的嵌入式封装模块的另一种定位凸起分布示意图。
图6为本公开示例性实施例提供的嵌入式封装模块的另一种定位凸起分布示意图。
图7为本公开示例性实施例提供的嵌入式封装模块的另一种定位凸起分布示意图。
图8为本公开示例性实施例提供的第二种嵌入式封装模块的结构示意图。
图9为本公开示例性实施例提供的第三种嵌入式封装模块的结构示意图。
图10为本公开示例性实施例提供的第四种嵌入式封装模块的剖视示意图。
图11为本公开示例性实施例提供的第五种嵌入式封装模块的结构示意图。
图12为本公开示例性实施例提供的第六种嵌入式封装模块的剖视示意图。
图13为本公开示例性实施例提供的第七种嵌入式封装模块的结构示意图。
图14为本公开示例性实施例提供的第八种嵌入式封装模块的结构示意图。
图15为本公开示例性实施例提供的第九种嵌入式封装模块的结构示意图。
图16为本公开示例性实施例提供的一种过孔和焊盘位置关系示意图。
图17为本公开示例性实施例提供的另一种过孔和焊盘位置关系示意图。
图18为本公开示例性实施例提供的一种电流流向示意图。
图19为为本公开示例性实施例提供的一种嵌入式封装模块封装方法的流程图。
图中：100、第一半导体器件；110、焊盘；120、定位凸起；200、第一封装层；210、第一过孔；220、第二过孔；300、第一布线层；400、封装框架；410、容置区；420、金属块；500、第二半导体器件；510、焊盘；520、定位凸起；600、第三封装层；610、第三过孔；700、第三布线层；800、第三半导体器件；810、焊盘；820、定位凸起；900、第二封装层；910、第四过孔；1000、第二布线层；1100、第四布线层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本发明将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
相关技术中提供的一种芯片封装结构，如图1所示，该芯片封装结构中，芯片001封装于边框002内，芯片001和外部电路连接的过孔可以是在封装层通过激光加工形成，激光加工的识别点003设置于边框上，通过边框上的识别点003定位加工过孔，若芯片在边框中安装时位置偏离理想位置或者由于制程精度导致芯片在边框中的位置偏离理想位置，会造成过孔在芯片上的位置产生偏差，使得过孔和芯片的焊盘不对应，影响制程良率、模块通流能力以及可靠性。
本示例实施方式中首先提供了一种嵌入式封装模块，如图2和图3所示，该嵌入式封装模块包括：第一半导体器件100、第一封装层200和第一布线层300；第一半导体器件100具有第一面和第二面，所述第一半导体器件100的第一面上设置有至少两个定位凸起120和至少一焊盘110；第一封装层200形成于所述第一半导体器件100的第一面及与所述第一面相邻的面，所述定位凸起120位于所述第一封装层200，所述第一封装层200中设置有至少一第一过孔210，所述第一过孔210的底部位于所述焊盘110内且与所述焊盘110接触；第一布线层300位于所述第一封装层200远离所述第一半导体器件100的一侧，通过所述第一过孔210与所述焊盘110电性连接。
其中，第一过孔210可以是在第一封装层200中通过激光加工形成，定位凸起120可以作为激光加工时的定位点，由于定位凸起120位于第一半导体器件100上，避免了由于制程精度等问题导致的激光加工定位不准确的问题。
本公开实施中所述的半导体器件可以是芯片等器件，第一半导体器件100的第一面可以是电极面，第二面可以是和电极面相对的背面，定位凸起120设于电极面上，电极面上设置第一封装层200，定位凸起120可以包覆在第一封装层200内，也可以是暴露于第一封装层200，如定位凸起120的上表面和第一封装层200的上表面平齐。
本公开实施例提供的嵌入式封装模块，通过在第一半导体器件100的第一面上设置至少两个定位凸起120作为加工时的定位点，提高在第一封装层200加工第一过孔210的精度，并且通过第一过孔210实现电流流通的需求；由于过孔加工精度的提高，可以增加焊盘110上过孔的数量和/或过孔的直径，进一步提升过孔的电流的流通能力和散热能力，同时可以减小芯片焊盘上电流的横向流动距离，从而减小芯片内部电流损耗，进而提高封装的可靠性。
下面将对本公开实施例提供的嵌入式封装模块进行详细说明：
在本公开一可行的实施方式中，至少两个定位凸起120中至少一所述定位凸起120设置于所述焊盘110，并且设置有定位凸起120的焊盘110上未设置第一过孔210。比如，如图4所示，两个定位凸起120设置于同一焊盘110，并且设置有定位凸起120的焊盘110上未设置第一过孔210；或者如图5所示，两个定位凸起120分别设置于一焊盘110，并且设置有定位凸起120的焊盘110上未设置第一过孔210。
在本公开另一可行的实施方式中，至少两个定位凸起120中的至少一所述定位凸起120设置于一所述焊盘110，设置有所述定位凸起120的所述焊盘110上还设置有至少一所述第一过孔210。比如，如图6所示，两个定位凸起120分别设置于一焊盘110，其中一个设置有定位凸起120的焊盘110上还设置有至少一个第一过孔210；或者如图7所示，两个定位凸起120设置于同一焊盘110，且该焊盘110上还设置有第一过孔210；或者如图3所示，两个定位凸起120分别设置于两个焊盘110，并且该两个焊盘110上还设置有第一过孔210。第一半导体器件100表面同时设置定位凸起120和第一过孔210，既可提高激光钻孔位置，也可以实现符合功率模块的大电流通流。
其中，所述第一过孔210与所述定位凸起120在所述第一半导体器件100的第一面的投影不重叠。也即是第一过孔210和定位凸起120相互独立，但本案不以此为限。
当然在实际应用中，定位凸起120也可以设置于第一半导体器件100第一面上非焊盘110区域等，本公开实施例对此不做具体限定。
如图8所示，当定位凸起120被包覆于所述第一封装层200，所述第一封装层200上还设置有至少一第二过孔220，所述第二过孔220和所述定位凸起120接触且在所述第一半导体器件100的第一面的投影至少部分交叠。其中，至少部分的所述定位凸起120设置于至少一所述焊盘110，且所述第二过孔220和设置于所述焊盘110的所述定位凸起120接触，且在所述第一半导体器件的第一面的投影至少部分交叠。在实际应用中，可以根据实际需求，选择在部分或者全部的定位凸起120上设置第二过孔220。
通过定位凸起120和第二过孔220连接第一半导体器件100和第一布线层300，可以提高焊盘110的利用率，尤其适用于焊盘110尺寸较小的半导体器件的封装。
需要说明的是，在本公开实施例中所述的所有过孔中可以为实心金属过孔，以减小过孔电阻进而增加电流流通能力，降低能耗。当然在实际应用中，过孔材料也可以是其他导电材料，其结构也可以是非实心结构，本公开实施例对此不做具体限定。定位凸起120可以是导电材料制成，定位凸起120和焊盘110电连接，第二过孔220可以和第一布线层300电连接。
进一步的，所述嵌入式封装模块还包括封装框架400，在本公开实施例提供的一种封装框架400，封装框架400具有容置区410，例如环绕形成的空间、挖槽形成的空间等。所述第一半导体器件100设置于所述容置区410中。其中，在本公开一可行的实施方式中，封装框架400可以是PCB板，容置区410为设于PCB板上的盲孔或通孔等，该容置区410横截面可以是矩形，当然在实际应用中，容置区410的横截面也可以是圆形或者多个矩形组成不规则形状等，本公开实施例对此不做具体限定。在本公开另一可行的实施方式中，封装框架400可以是引线框，具有容置区410，其材料可以是导电材料或者绝缘材料，比如，引线框可以包括多个导电块，多个导电块围成容置区410，多个导电块可以是彼此独立或者首尾相接，本公开实施例对此不做具体限定。
如图9和10所示，封装框架400可以包括一个或多个容置区410，在一个容置区410中可以设置一个或多个半导体器件。当容置区410中设置一个半导体器件时，可以使用封装层材料填充半导体器件和封装框架400之间的空隙，以固定半导体器件。当容置区410中设置有多个半导体器件时，多个半导体器件可以呈阵列式分布，通过封装层材料填充半导体器件和封装框架400以及相邻的半导体器件之间的空隙，以固定半导体器件。多个容置区410在封装框架400内可以是呈阵列式分布。
进一步的，如图12所示，所述封装框架400还可以包括多个相互不连接的金属块420，且至少一所述第一半导体器件100通过所述第一过孔210和第一布线层300与至少一所述金属块420电性连接。以多个金属块420作为半导体器件电极扇出的引脚阵列，可以将半导体器件电极就近引出，缩短电流回路，降低损耗。
如图11所述，本公开实施例提供的另一种封装框架400，可以是板状结构，第一半导体器件100和所述封装框架400堆叠设置，第一半导体器件100的背面和封装框架400接触，第一封装层200包覆第一半导体器件100，并且第一封装层200可以设置在封装框架400上第一半导体器件100投影区域之外，第一封装层200和封装框架400接触。
进一步的，如图13所示，所述嵌入式封装模块还包括：至少一第二半导体器件500、第三封装层600和第三布线层700；至少一第二半导体器件500具有第一面和第二面，所述第二半导体器件500的第一面上设置有至少两个定位凸起520(图中仅示出一个定位凸起)和至少一个焊盘510，所述第二半导体器件500的第二面连接于所述第一布线层300；第三封装层600形成于所述第一布线层300远离所述第一半导体器件100的一侧，并且覆盖所述第二半导体器件500，所述第二半导体器件500的所述定位凸起520位于所述第三封装层600，所述第三封装层600上设置有至少一第三过孔610，所述第三过孔610的底部位于所述第二半导体器件500的所述焊盘510的区域内且接触所述第二半导体器件500的所述焊盘510；所述第三过孔610与所述第二半导体器件500的所述定位凸起520在所述第二半导体器件500的第一面的投影不重叠；第三布线层700形成于所述第三封装层600，第三布线层700和所述第二半导体器件500通过第三过孔610电性连接。第一布线层300和第三布线层700之间也可以通过过孔电性连接，该过孔设于第三封装层600。
其中，第二半导体器件500上的定位凸起520可以是包覆于第三封装层600，也可以是暴露于第三封装层600，比如，其上表面和第三封装层600上表面平齐。第二半导体器件500和第一布线层300可以通过焊接或者胶粘接的方式连接，由于在焊接或胶连接的过程中，第二半导体器件500相对于第一半导体器件100出现位置精度偏差，若在加工第三封装层600中的第三过孔610时，采用封装框架400或者第一半导体器件100上的定位点进行过孔加工，其过孔加工精度相对较差，因此在第二半导体器件500上设置定位凸起520，能够提升第三过孔610的位置精度。
在如图13所示的多层堆叠结构中，每一层的过孔都以所在层中半导体器件上的定位凸起为加工识别点，避免堆叠结构中位置误差的累加，提高过孔加工的精确度。
如图14所示，所述嵌入式封装模块还包括：第三半导体器件800、第二封装层900和第二布线层1000；第三半导体器件800具有第一面和第二面，所述第三半导体器件800的第一面上设置有至少两个定位凸起820(图中仅示出一个)和至少一焊盘810，所述第一半导体器件100的第二面和所述第三半导体器件800的第二面例如通过一连接层连接；第二封装层900形成于所述第三半导体器件800的第一面及与所述第一面相邻的面，所述第三半导体器件800的所述定位凸起820位于所述第二封装层900，所述第二封装层900上设置有至少一第四过孔910，所述第四过孔910的底部位于所述第三半导体器件800的所述焊盘810的区域内且接触所述第三半导体器件800的所述焊盘810；所述第四过孔910与所述第三半导体器件800的所述定位凸起820在所述第三半导体器件800的第一面的投影不重叠；第二布线层1000位于所述第二封装层900远离所述第一半导体器件100的一侧，通过所述第四过孔910和所述第三半导体器件800的焊盘810电性连接。
其中，第三半导体器件800上的定位凸起820可以是包覆于第二封装层900，也可以是暴露于第二封装层900，比如，其上表面和第二封装层900上表面平齐。第一半导体器件100和第三半导体器件800背靠背设置，第一半导体器件100和第三半导体器件800通过焊接或者胶连接的方式连接，由于在焊接或胶连接的过程中，第三半导体器件800相对第一半导体器件100的位置可能会有偏移，若采用封装框架400或者第一半导体器件100上的定位点进行过孔加工，其精度差，因此在第三半导体器件800上设置第二定位凸起820，能够提升第四过孔910的位置精度。
如图15所示，所述第一布线层300的数量为至少一层，所述第一半导体器件100的第二面的一侧设置有至少一层第四布线层1100，第一布线层300和所述第四布线层1100的层数相同。多层布线结构可以提供更加灵活的布线方式，且半导体器件两面的布线层数相同，可以减小封装模块的翘曲。相对于单布线层结构，此多布线层结构使得嵌入式封装模块散热路径增加，提高了嵌入式封装模块的散热能力和可靠性。
本公开实施例提供的嵌入式封装模块，通过在半导体器件上设置定位凸起，将定位凸起作为激光加工识别点进行过孔加工的识别点，提高了过孔的位置精度。如图16和17所示，图中D为钻孔位置偏差，d为过孔直径，P为相邻焊盘的间距。通过在半导体器件上设置定位凸起，解决了相关技术中钻孔位置偏差包括的引线框架加工偏差、半导体器件贴片偏差以及ABF(Ajinomoto Build-Up Film，Ajinomoto合成膜)压合半导体器件偏移偏差，能够将钻孔位置偏差从30um降低至5um。半导体器件表面同时设置定位凸起和过孔，既可提高激光钻孔位置，也可以实现符合功率模块的大电流通流；激光钻孔位置偏差D的减小，有助于改善制程良率、提高模块的通流能力，散热能力以及封装可靠性。
钻孔位置偏差D的减小，可以增加过孔与半导体器件焊盘连接处过孔的直径d和单个焊盘上的过孔数量，从而可以增加焊盘过孔的通流能力以及芯片的散热能力，进而提高封装的可靠性；钻孔偏差D的减小，可以减小两个芯片焊盘之间的距离P，实现小间距焊盘的半导体器件的封装。
电流从晶胞到焊盘的流向如图18所示，过孔直径d的增加、单个焊盘上过孔数量的增加以及焊盘间距的减小都可以减少电流从晶胞流到焊盘的横向距离，进而减小半导体器件的内阻。
本示例实施方式中首先提供了一种嵌入式封装模块的封装方法，如图19所示，所述方法包括如下步骤：
步骤S110，提供第一半导体器件100，所述第一半导体器件100的第一面具有至少一焊盘110；
步骤S120，在所述第一半导体器件100的第一面上设置至少两个定位凸起120；
步骤S130，将第一封装层200压合，且覆盖所述第一半导体器件100的第一面及与所述第一面相邻的面；
步骤S140，通过激光钻孔工艺，在所述第一封装层200上加工至少一第一过孔210，其中，激光钻孔位置确认的模式识别点为所述第一半导体器件100第一面上的定位凸起120，以使得所述第一过孔210的底部位于所述焊盘110的区域内且接触所述焊盘110，且使得所述第一过孔210与所述定位凸起120在所述第一半导体器件100的第一面的投影不重叠；
步骤S150，对所述第一过孔210填充金属；
步骤S160，形成第一布线层300，所述第一布线层300位于所述第一封装层200远离所述第一半导体器件100的一侧，且所述第一布线层300通过所述第一过孔210和所述焊盘110电性连接。
本公开实施例提供的嵌入式封装模块的封装方法，通过在半导体器件的第一面上设置至少两个定位凸起120作为过孔加工时的定位点，提高在对应封装层中加工对应过孔的精度，并且通过加工的过孔实现电流流通的需求；由于过孔加工精度的提高，可以增加焊盘上过孔的数量，进一步提升焊盘上电流的流通能力和散热能力，进而提高封装的可靠性。
在步骤S120中，可以通过球焊工艺或者电镀工艺在第一半导体器件100的第一面上设置至少两个定位凸起120，至少两个定位凸起120可以是设置于同一焊盘110，或者每个定位凸起120分别位于一焊盘110，比如，三个定位凸起120，其中一个位于一焊盘110，另外两个位于另一焊盘110。当然在实际应用中，定位凸起120也可以设置于半导体器件第一面上非焊盘110区域等，本公开实施例对此不做具体限定。
在步骤S130中，可以将第一封装层200压合，且覆盖所述第一半导体器件100的第一面及与所述第一面相邻的面，第一封装层200可以是塑胶层。
当嵌入式封装模块还包括封装框架400时，步骤S120之前还可以包括，在封装框架400一端面粘贴胶带，将半导体器件放入封装框架400，半导体器件的第一面远离封装框架400粘贴胶带的一端；在步骤S120之后还可以包括，在半导体器件的第二面上压合塑胶层。
在步骤S140中，可以通过激光钻孔工艺，在所述第一封装层200上加工至少一第一过孔210，其中，激光钻孔位置确认的模式识别点为所述第一半导体器件100第一面上的定位凸起120，以使得所述第一过孔210的底部位于所述焊盘110的区域内且接触所述焊盘110，且使得所述第一过孔210与所述定位凸起120在所述第一半导体器件100的第一面的投影不重叠。
通过定位凸起120作为模式识别点，使得第一过孔210的位置精度提高，激光钻孔位置偏差D的减小，有助于改善制程良率、提高模块的通流能力，散热能力以及封装可靠性。
在步骤S150和步骤S160中，可以通过电镀工艺填充第一过孔210和形成第一布线层300，第一过孔210和第一布线层300可以是一次电镀成型，也可以是分别电镀成型。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (17)

1.一种嵌入式封装模块，其特征在于，所述嵌入式封装模块包括：
第一半导体器件，具有第一面和第二面，所述第一半导体器件的第一面上设置有至少两个定位凸起和至少一焊盘，所述定位凸起的上表面高于所述焊盘的上表面；
第一封装层，形成于所述第一半导体器件的第一面及与所述第一面相邻的面，所述定位凸起位于所述第一封装层，所述第一封装层中设置有至少一第一过孔，所述第一过孔的底部位于所述焊盘内且与所述焊盘接触；
第一布线层，位于所述第一封装层远离所述第一半导体器件的一侧，通过所述第一过孔与所述焊盘电性连接。
2.如权利要求1所述的嵌入式封装模块，其特征在于，所述至少两个定位凸起中至少一所述定位凸起设置于所述焊盘。
3.如权利要求2所述的嵌入式封装模块，其特征在于，所述至少两个定位凸起中的至少一所述定位凸起设置于所述焊盘，设置有所述定位凸起的所述焊盘上还设置有至少一所述第一过孔。
4.如权利要求1所述的嵌入式封装模块，其特征在于，所述第一过孔与所述定位凸起在所述第一半导体器件的第一面的投影不重叠。
5.如权利要求1所述的嵌入式封装模块，其特征在于，所述定位凸起被包覆于所述第一封装层，所述第一封装层上还设置有至少一第二过孔，至少部分的所述定位凸起设置于至少一所述焊盘，且所述第二过孔和设置于所述焊盘的所述定位凸起接触且在所述第一半导体器件的第一面的投影至少部分交叠。
6.如权利要求5所述的嵌入式封装模块，其特征在于，所述第二过孔和所述第一布线层电性连接。
7.如权利要求1所述的嵌入式封装模块，其特征在于，所述嵌入式封装模块还包括封装框架，具有容置区，所述第一半导体器件设置于所述容置区中。
8.如权利要求7所述的嵌入式封装模块，其特征在于，所述第一半导体器件的数量为多个，且均设置于所述容置区中。
9.如权利要求7所述的嵌入式封装模块，其特征在于，所述第一半导体器件的数量为多个，所述容置区的数量为多个，且每一所述容置区中设置有至少一所述第一半导体器件。
10.如权利要求7所述的嵌入式封装模块，其特征在于，所述封装框架包含多个相互不连接的金属块，且至少一所述第一半导体器件通过所述第一过孔和至少一所述金属块电性连接。
11.如权利要求1所述的嵌入式封装模块，其特征在于，所述嵌入式封装模块还包括封装框架，所述第一半导体器件和所述封装框架堆叠设置。
12.如权利要求1所述的嵌入式封装模块，其特征在于，所述嵌入式封装模块还包括：
至少一第二半导体器件，具有第一面和第二面，所述第二半导体器件的第一面上设置有至少两个定位凸起和至少一个焊盘，所述第二半导体器件的第二面连接于所述第一布线层；
第三封装层，形成于所述第一布线层远离所述第一半导体器件的一侧，并且覆盖所述第二半导体器件，所述第二半导体器件的所述定位凸起位于所述第三封装层，所述第三封装层上设置有至少一第三过孔，所述第三过孔的底部位于所述第二半导体器件的所述焊盘的区域内且接触所述第二半导体器件的所述焊盘；所述第三过孔与所述第二半导体器件的所述定位凸起在所述第二半导体器件的第一面的投影不重叠；
第三布线层，形成于所述第三封装层。
13.如权利要求1所述的嵌入式封装模块，其特征在于，所述嵌入式封装模块还包括：
第三半导体器件，所述第三半导体器件的第一面上设置有至少两个定位凸起和至少一焊盘，所述第一半导体器件的第二面和所述第三半导体器件的第二面通过一连接层连接；
第二封装层，形成于所述第三半导体器件的第一面及与所述第一面相邻的面，所述第三半导体器件的所述定位凸起位于所述第二封装层，所述第二封装层上设置有至少一第四过孔，所述第四过孔的底部位于所述第三半导体器件的所述焊盘的区域内且接触所述第三半导体器件的所述焊盘；所述第四过孔与所述第三半导体器件的所述定位凸起在所述第三半导体器件的第一面的投影不重叠；
第二布线层，位于所述第二封装层远离所述第一半导体器件的一侧，通过所述第四过孔和所述第三半导体器件的所述焊盘电性连接。
14.如权利要求1所述的嵌入式封装模块，其特征在于，所述定位凸起暴露于所述第一封装层，所述定位凸起和所述第一布线层电性连接。
15.如权利要求1所述的嵌入式封装模块，其特征在于，所述第一过孔是金属实心过孔。
16.如权利要求1所述的嵌入式封装模块，其特征在于，所述第一布线层的数量为至少一层，所述第一半导体器件的第二面的一侧设置有至少一层第四布线层，第一布线层和所述第四布线层的层数相同。
17.一种嵌入式封装模块的封装方法，其特征在于，所述方法包括：
提供第一半导体器件，所述第一半导体器件的第一面具有至少一焊盘；
在所述第一半导体器件的第一面上设置至少两个定位凸起，所述定位凸起的上表面高于所述焊盘的上表面；
将第一封装层压合，且覆盖所述第一半导体器件的第一面及与所述第一面相邻的面；
通过激光钻孔工艺，在所述第一封装层上加工至少一第一过孔，其中，激光钻孔位置确认的模式识别点为所述第一半导体器件第一面上的定位凸起，以使得所述第一过孔的底部位于所述焊盘的区域内且接触所述焊盘，且使得所述第一过孔与所述定位凸起在所述第一半导体器件的第一面的投影不重叠；
对所述第一过孔填充金属；
形成第一布线层，所述第一布线层位于所述第一封装层远离所述第一半导体器件的一侧，且所述第一布线层通过所述第一过孔和所述焊盘电性连接。
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