CN111524873B - Embedded packaging module and packaging method thereof - Google Patents

Embedded packaging module and packaging method thereof Download PDF

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Publication number
CN111524873B
CN111524873B CN201910105644.XA CN201910105644A CN111524873B CN 111524873 B CN111524873 B CN 111524873B CN 201910105644 A CN201910105644 A CN 201910105644A CN 111524873 B CN111524873 B CN 111524873B
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semiconductor device
positioning
layer
packaging
embedded
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CN111524873A (en
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王增胜
郭雪涛
鲁凯
李辉
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Delta Electronics Shanghai Co Ltd
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Delta Electronics Shanghai Co Ltd
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Priority to CN201910105644.XA priority Critical patent/CN111524873B/en
Priority to US16/730,024 priority patent/US11552039B2/en
Publication of CN111524873A publication Critical patent/CN111524873A/en
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    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/82007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
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    • H01L2224/82009—Pre-treatment of the connector or the bonding area
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    • H01L2224/82121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8213—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
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    • H01L2224/82136—Aligning involving guiding structures, e.g. spacers or supporting members
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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Abstract

The present disclosure relates to an embedded package module, which includes: the packaging structure comprises a first semiconductor device, a first packaging layer and a first wiring layer, wherein the first semiconductor device is provided with a first surface and a second surface, and the first surface of the first semiconductor device is provided with at least two positioning bulges and at least one bonding pad; the first packaging layer is formed on a first surface of the first semiconductor device and a surface adjacent to the first surface, the positioning protrusion is located on the first packaging layer, at least one first through hole is formed in the first packaging layer, and the bottom of the first through hole is located in the pad and is in contact with the pad; the first wiring layer is located on one side, away from the first semiconductor device, of the first packaging layer and is electrically connected with the bonding pad through the first through hole. The positioning bulge arranged on the first semiconductor device improves the position precision of the first via hole.

Description

Embedded packaging module and packaging method thereof
Technical Field
The disclosure relates to the technical field of chip packaging, in particular to an embedded packaging module and a packaging method thereof.
Background
With the development and progress of the technology, the application of the chip in various electronic products is more and more extensive, and the size of the chip is increased due to the increase of the power and the current of the chip, so that the packaging size of the chip is increased, and a severe test is brought to the packaging reliability of the chip. And various electronic products have higher and higher requirements on the integration level of chips, and simultaneously require the chips to have lower stacking height.
At present, in order to increase the reliability of the chip package and reduce the chip stacking height, the embedded package structure becomes a chip that is usually packaged by the embedded structure. However, the yield and reliability of the embedded structure package are low due to the influence of the process precision and the like during the packaging process.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
An object of the present disclosure is to provide an embedded package module and a packaging method thereof, which overcome one or more of the problems due to the limitations and disadvantages of the related art, at least to some extent.
According to an aspect of the present disclosure, there is provided an embedded package module, including:
the first semiconductor device is provided with a first surface and a second surface, and the first surface of the first semiconductor device is provided with at least two positioning bulges and at least one bonding pad;
the first packaging layer is formed on a first surface of the first semiconductor device and a surface adjacent to the first surface, the positioning protrusion is located on the first packaging layer, at least one first through hole is formed in the first packaging layer, and the bottom of the first through hole is located in the pad and is in contact with the pad;
and the first wiring layer is positioned on one side of the first packaging layer, which is far away from the first semiconductor device, and is electrically connected with the bonding pad through the first through hole.
According to an embodiment of the present disclosure, at least one of the at least two positioning protrusions is disposed on the pad.
According to an embodiment of the present disclosure, at least one of the at least two positioning protrusions is disposed on the pad, and the pad on which the positioning protrusion is disposed is further provided with at least one first via hole.
According to an embodiment of the present disclosure, a projection of the first via and the positioning protrusion on the first surface of the first semiconductor device does not overlap.
According to an embodiment of the present disclosure, the positioning protrusion is wrapped on the first package layer, the first package layer is further provided with at least one second via hole, at least a portion of the positioning protrusion is disposed on at least one of the pads, and the second via hole is at least partially overlapped with a projection of the positioning protrusion disposed on the pad, the projection contacting the first surface of the first semiconductor device.
According to an embodiment of the present disclosure, the second via is electrically connected to the first wiring layer.
According to an embodiment of the present disclosure, the embedded package module further includes a package frame having a receiving area, and the first semiconductor device is disposed in the receiving area.
According to an embodiment of the present disclosure, the number of the first semiconductor devices is plural, and the first semiconductor devices are all disposed in the accommodating area.
According to an embodiment of the present disclosure, the number of the first semiconductor devices is plural, the number of the accommodating regions is plural, and at least one first semiconductor device is disposed in each accommodating region.
According to an embodiment of the present disclosure, the package frame includes a plurality of metal blocks that are not connected to each other, and at least one of the first semiconductor devices is electrically connected to at least one of the metal blocks through the first via hole.
According to an embodiment of the present disclosure, the embedded package module further includes a package frame, and the first semiconductor device and the package frame are stacked.
According to an embodiment of the present disclosure, the embedded package module further includes:
the second semiconductor device is provided with a first surface and a second surface, the first surface of the second semiconductor device is provided with at least two positioning bulges and at least one bonding pad, and the second surface of the second semiconductor device is connected to the first wiring layer;
the third packaging layer is formed on one side, far away from the first semiconductor device, of the first wiring layer and covers the second semiconductor device, the positioning protrusion of the second semiconductor device is located on the third packaging layer, at least one third through hole is arranged on the third packaging layer, and the bottom of the third through hole is located in the area of the bonding pad of the second semiconductor device and contacts the bonding pad of the second semiconductor device; the third via hole is not overlapped with the projection of the positioning bulge of the second semiconductor device on the first surface of the second semiconductor device;
and the third wiring layer is formed on the third packaging layer.
According to an embodiment of the present disclosure, the embedded package module further includes:
the first surface of the third semiconductor device is provided with at least two positioning bulges and at least one bonding pad, and the second surface of the first semiconductor device is connected with the second surface of the third semiconductor device through a connecting layer;
the second packaging layer is formed on a first surface of the third semiconductor device and a surface adjacent to the first surface, the positioning protrusion of the third semiconductor device is located on the second packaging layer, at least one fourth through hole is formed in the second packaging layer, and the bottom of the fourth through hole is located in the area of the bonding pad of the third semiconductor device and contacts the bonding pad of the third semiconductor device; the fourth via hole is not overlapped with the projection of the positioning bulge of the third semiconductor device on the first surface of the third semiconductor device;
and the second wiring layer is positioned on one side of the second packaging layer, which is far away from the first semiconductor device, and is electrically connected with the bonding pad of the third semiconductor device through the fourth through hole.
According to an embodiment of the present disclosure, the positioning bump is exposed to the first package layer, and the positioning bump is electrically connected to the first wiring layer.
According to an embodiment of the present disclosure, the first via is a metal solid via.
According to an embodiment of the present disclosure, the number of the first wiring layers is at least one, at least one fourth wiring layer is disposed on one side of the second surface of the first semiconductor device, and the number of the first wiring layers is the same as that of the fourth wiring layers.
According to another aspect of the present disclosure, there is provided a packaging method of an embedded package module, the method including:
providing a first semiconductor device, wherein a first side of the first semiconductor device is provided with at least one bonding pad;
arranging at least two positioning bulges on the first surface of the first semiconductor device;
pressing a first packaging layer, and covering a first surface of the first semiconductor device and a surface adjacent to the first surface;
processing at least one first via hole on the first packaging layer through a laser drilling process, wherein a mode identification point confirmed by a laser drilling position is a positioning bump on the first side of the first semiconductor device, so that the bottom of the first via hole is positioned in the area of the bonding pad and contacts the bonding pad, and the projection of the first via hole and the projection of the positioning bump on the first side of the first semiconductor device are not overlapped;
filling metal into the first via hole;
and forming a first wiring layer, wherein the first wiring layer is positioned on one side of the first packaging layer far away from the first semiconductor device, and the first wiring layer is electrically connected with the bonding pad through the first through hole.
According to the embedded packaging module provided by the disclosure, the at least two positioning bulges are arranged on the first surface of the first semiconductor device and are used as positioning points during processing, so that the position precision of processing the first through hole on the first packaging layer is improved, and the requirement of current circulation is met through the first through hole; due to the improvement of the precision of the processing position of the via hole, the number of the via holes on the pad and the diameter of the via hole can be increased, the circulation capability and the heat dissipation capability of the current of the via hole are further improved, and meanwhile, the transverse flowing distance of the current on the pad of the chip can be reduced, so that the current loss inside the chip is reduced, and the reliability of packaging is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic structural diagram of a chip package structure provided in the related art.
Fig. 2 is a schematic structural diagram of a first embedded package module according to an exemplary embodiment of the present disclosure.
Fig. 3 is a schematic view of a positioning bump distribution of an embedded package module according to an exemplary embodiment of the disclosure.
Fig. 4 is a schematic view of another positioning bump distribution of an embedded package module according to an exemplary embodiment of the disclosure.
Fig. 5 is a schematic view illustrating another distribution of positioning bumps of an embedded package module according to an exemplary embodiment of the disclosure.
Fig. 6 is a schematic view of another positioning bump distribution of an embedded package module according to an exemplary embodiment of the disclosure.
Fig. 7 is a schematic view of another positioning bump distribution of an embedded package module according to an exemplary embodiment of the disclosure.
Fig. 8 is a schematic structural diagram of a second embedded package module according to an exemplary embodiment of the disclosure.
Fig. 9 is a schematic structural diagram of a third embedded package module according to an exemplary embodiment of the disclosure.
Fig. 10 is a schematic cross-sectional view of a fourth embedded package module according to an exemplary embodiment of the disclosure.
Fig. 11 is a schematic structural diagram of a fifth embedded package module according to an exemplary embodiment of the disclosure.
Fig. 12 is a schematic cross-sectional view of a sixth embedded package module according to an exemplary embodiment of the disclosure.
Fig. 13 is a schematic structural diagram of a seventh embedded package module according to an exemplary embodiment of the disclosure.
Fig. 14 is a schematic structural diagram of an eighth embedded package module according to an exemplary embodiment of the disclosure.
Fig. 15 is a schematic structural diagram of a ninth embedded package module according to an exemplary embodiment of the disclosure.
Fig. 16 is a schematic diagram of a positional relationship between a via and a pad according to an exemplary embodiment of the disclosure.
Fig. 17 is a schematic diagram of another via and pad position relationship provided in an exemplary embodiment of the present disclosure.
Fig. 18 is a schematic current flow diagram provided by an exemplary embodiment of the present disclosure.
Fig. 19 is a flowchart of an embedded package module packaging method provided for an exemplary embodiment of the present disclosure.
In the figure: 100. a first semiconductor device; 110. a pad; 120. positioning the projection; 200. a first encapsulation layer; 210. a first via hole; 220. a second via hole; 300. a first wiring layer; 400. a package frame; 410. an accommodating area; 420. a metal block; 500. a second semiconductor device; 510. a pad; 520. positioning the projection; 600. a third encapsulation layer; 610. a third via hole; 700. a third wiring layer; 800. a third semiconductor device; 810. a pad; 820. positioning the projection; 900. a second encapsulation layer; 910. a fourth via hole; 1000. a second wiring layer; 1100. and a fourth wiring layer.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.
As shown in fig. 1, in the chip package structure provided in the related art, a chip 001 is packaged in a frame 002, a via hole for connecting the chip 001 and an external circuit may be formed in a package layer by laser processing, a recognition point 003 of the laser processing is disposed on the frame, and the via hole is positioned and processed through the recognition point 003 on the frame, if the chip is mounted in the frame at a position deviated from an ideal position or the chip is deviated from the ideal position in the frame due to process accuracy, the position of the via hole on the chip may be deviated, so that the via hole does not correspond to a pad of the chip, and the process yield, the current capacity of the module, and the reliability are affected.
First, in the present exemplary embodiment, there is provided an embedded package module, as shown in fig. 2 and 3, including: a first semiconductor device 100, a first encapsulation layer 200, and a first wiring layer 300; the first semiconductor device 100 has a first side and a second side, and the first side of the first semiconductor device 100 is provided with at least two positioning bumps 120 and at least one pad 110; the first packaging layer 200 is formed on a first surface of the first semiconductor device 100 and a surface adjacent to the first surface, the positioning bump 120 is located on the first packaging layer 200, at least one first via hole 210 is arranged in the first packaging layer 200, and the bottom of the first via hole 210 is located in the pad 110 and is in contact with the pad 110; the first wiring layer 300 is located on a side of the first packaging layer 200 away from the first semiconductor device 100, and is electrically connected to the pad 110 through the first via 210.
The first via hole 210 may be formed in the first package layer 200 by laser processing, the positioning protrusion 120 may be used as a positioning point during laser processing, and the positioning protrusion 120 is located on the first semiconductor device 100, so that the problem of inaccurate laser processing positioning caused by problems such as process accuracy is avoided.
The semiconductor device in the embodiment of the present disclosure may be a device such as a chip, the first surface of the first semiconductor device 100 may be an electrode surface, the second surface may be a back surface opposite to the electrode surface, the positioning protrusion 120 is disposed on the electrode surface, the first encapsulation layer 200 is disposed on the electrode surface, the positioning protrusion 120 may be wrapped in the first encapsulation layer 200, or may be exposed to the first encapsulation layer 200, for example, the upper surface of the positioning protrusion 120 is flush with the upper surface of the first encapsulation layer 200.
According to the embedded package module provided by the embodiment of the disclosure, the at least two positioning protrusions 120 are arranged on the first surface of the first semiconductor device 100 as positioning points during processing, so that the accuracy of processing the first via hole 210 in the first package layer 200 is improved, and the requirement of current circulation is met through the first via hole 210; due to the improvement of the processing precision of the via holes, the number of the via holes on the bonding pad 110 and/or the diameters of the via holes can be increased, the current circulation capability and the heat dissipation capability of the via holes are further improved, and meanwhile, the transverse flowing distance of the current on the bonding pad of the chip can be reduced, so that the current loss inside the chip is reduced, and the packaging reliability is improved.
The following will describe the embedded package module provided by the embodiments of the present disclosure in detail:
in a possible embodiment of the present disclosure, at least one positioning bump 120 of the at least two positioning bumps 120 is disposed on the pad 110, and the first via 210 is not disposed on the pad 110 on which the positioning bump 120 is disposed. For example, as shown in fig. 4, two positioning bumps 120 are disposed on the same pad 110, and the pad 110 on which the positioning bumps 120 are disposed is not provided with the first via 210; alternatively, as shown in fig. 5, two positioning bumps 120 are respectively disposed on one pad 110, and the pad 110 on which the positioning bumps 120 are disposed is not provided with the first via 210.
In another possible embodiment of the present disclosure, at least one positioning protrusion 120 of the at least two positioning protrusions 120 is disposed on one of the pads 110, and at least one first via 210 is further disposed on the pad 110 on which the positioning protrusion 120 is disposed. For example, as shown in fig. 6, two positioning bumps 120 are respectively disposed on a pad 110, and at least one first via hole 210 is further disposed on one pad 110 on which the positioning bump 120 is disposed; or as shown in fig. 7, two positioning protrusions 120 are disposed on the same pad 110, and a first via 210 is further disposed on the pad 110; or as shown in fig. 3, two positioning protrusions 120 are respectively disposed on two pads 110, and first vias 210 are further disposed on the two pads 110. The positioning protrusion 120 and the first via hole 210 are simultaneously disposed on the surface of the first semiconductor device 100, so that the laser drilling position can be increased, and a large current conforming to the power module can be passed through.
Wherein the first via 210 does not overlap with the projection of the positioning bump 120 on the first surface of the first semiconductor device 100. That is, the first via hole 210 and the positioning protrusion 120 are independent of each other, but the disclosure is not limited thereto.
Of course, in practical applications, the positioning protrusion 120 may also be disposed on the first surface of the first semiconductor device 100 in a region other than the pad 110, which is not specifically limited in the embodiment of the present disclosure.
As shown in fig. 8, when the positioning bump 120 is wrapped on the first packaging layer 200, at least one second via 220 is further disposed on the first packaging layer 200, and a projection of the second via 220 contacting the positioning bump 120 on the first side of the first semiconductor device 100 at least partially overlaps. At least part of the positioning bump 120 is disposed on at least one of the pads 110, and the second via 220 contacts the positioning bump 120 disposed on the pad 110, and the projection of the second via on the first surface of the first semiconductor device at least partially overlaps. In practical applications, the second via holes 220 may be selectively disposed on part or all of the positioning protrusions 120 according to practical requirements.
By connecting the first semiconductor device 100 and the first wiring layer 300 through the positioning bump 120 and the second via 220, the utilization rate of the bonding pad 110 can be improved, and the method is particularly suitable for packaging a semiconductor device with a small size of the bonding pad 110.
It should be noted that all the vias described in the embodiments of the present disclosure may be solid metal vias, so as to reduce the resistance of the vias, thereby increasing the current flowing capability and reducing the energy consumption. Of course, in practical applications, the via material may also be other conductive materials, and the structure thereof may also be a non-solid structure, which is not specifically limited in this disclosure. The positioning bump 120 may be made of a conductive material, the positioning bump 120 is electrically connected to the pad 110, and the second via 220 may be electrically connected to the first wiring layer 300.
Further, the embedded package module further includes a package frame 400, and in an embodiment of the package frame 400 provided in the present disclosure, the package frame 400 has a receiving area 410, for example, a space formed by surrounding, a space formed by digging a groove, and the like. The first semiconductor device 100 is disposed in the accommodating region 410. In a feasible embodiment of the present disclosure, the package frame 400 may be a PCB, the accommodating area 410 is a blind hole or a through hole disposed on the PCB, and the cross section of the accommodating area 410 may be a rectangle, but in practical applications, the cross section of the accommodating area 410 may also be a circle or an irregular shape formed by a plurality of rectangles, and the embodiment of the present disclosure is not limited to this specifically. In another possible implementation manner of the present disclosure, the package frame 400 may be a lead frame, and has a receiving area 410, and a material of the receiving area 410 may be a conductive material or an insulating material, for example, the lead frame may include a plurality of conductive blocks, the plurality of conductive blocks surround the receiving area 410, and the plurality of conductive blocks may be independent from each other or connected end to end, which is not specifically limited in this disclosure.
As shown in fig. 9 and 10, the package frame 400 may include one or more receiving areas 410, and one or more semiconductor devices may be disposed in one receiving area 410. When one semiconductor device is disposed in the receiving region 410, a gap between the semiconductor device and the package frame 400 may be filled with an encapsulation material to fix the semiconductor device. When a plurality of semiconductor devices are disposed in the accommodating area 410, the plurality of semiconductor devices may be distributed in an array, and the gap between the semiconductor device and the package frame 400 and between adjacent semiconductor devices is filled with the packaging layer material to fix the semiconductor device. The plurality of receiving areas 410 may be distributed in an array within the package frame 400.
Further, as shown in fig. 12, the package frame 400 may further include a plurality of metal blocks 420 that are not connected to each other, and at least one of the first semiconductor devices 100 is electrically connected to at least one of the metal blocks 420 through the first via 210 and the first wiring layer 300. The plurality of metal blocks 420 are used as a pin array for fan-out of the semiconductor device electrode, so that the semiconductor device electrode can be led out nearby, a current loop is shortened, and loss is reduced.
As shown in fig. 11, another package frame 400 provided by the embodiment of the present disclosure may be a plate-shaped structure, the first semiconductor device 100 and the package frame 400 are stacked, a back surface of the first semiconductor device 100 contacts the package frame 400, the first package layer 200 encapsulates the first semiconductor device 100, and the first package layer 200 may be disposed on the package frame 400 outside a projection area of the first semiconductor device 100, where the first package layer 200 contacts the package frame 400.
Further, as shown in fig. 13, the embedded package module further includes: at least a second semiconductor device 500, a third package layer 600, and a third wiring layer 700; at least one second semiconductor device 500 having a first side and a second side, the first side of the second semiconductor device 500 having at least two positioning bumps 520 (only one positioning bump is shown) and at least one bonding pad 510 disposed thereon, the second side of the second semiconductor device 500 being connected to the first wiring layer 300; a third packaging layer 600 is formed on a side of the first wiring layer 300 far away from the first semiconductor device 100 and covers the second semiconductor device 500, the positioning bump 520 of the second semiconductor device 500 is located on the third packaging layer 600, at least one third via 610 is arranged on the third packaging layer 600, and the bottom of the third via 610 is located in the area of the pad 510 of the second semiconductor device 500 and contacts the pad 510 of the second semiconductor device 500; the third via 610 does not overlap with a projection of the positioning bump 520 of the second semiconductor device 500 on the first side of the second semiconductor device 500; a third wiring layer 700 is formed on the third package layer 600, and the third wiring layer 700 and the second semiconductor device 500 are electrically connected through a third via 610. The first wiring layer 300 and the third wiring layer 700 may be electrically connected to each other through a via provided in the third encapsulation layer 600.
The positioning bumps 520 on the second semiconductor device 500 may be covered by the third packaging layer 600, or may be exposed to the third packaging layer 600, for example, the upper surface thereof is flush with the upper surface of the third packaging layer 600. The second semiconductor device 500 and the first wiring layer 300 may be connected by soldering or adhesive bonding, and because in the soldering or adhesive bonding process, a positional accuracy deviation occurs in the second semiconductor device 500 with respect to the first semiconductor device 100, if the third via 610 in the third package layer 600 is processed, the via processing accuracy is relatively poor by using a positioning point on the package frame 400 or the first semiconductor device 100 to perform the via processing, and therefore, the positioning bump 520 is disposed on the second semiconductor device 500, and the positional accuracy of the third via 610 can be improved.
In the multilayer stacked structure shown in fig. 13, the positioning protrusion on the semiconductor device in the layer where the via hole is located is used as a processing identification point for the via hole of each layer, so that the accumulation of position errors in the stacked structure is avoided, and the accuracy of via hole processing is improved.
As shown in fig. 14, the embedded package module further includes: a third semiconductor device 800, a second package layer 900, and a second wiring layer 1000; a third semiconductor device 800 having a first side and a second side, the first side of the third semiconductor device 800 being provided with at least two positioning bumps 820 (only one is shown in the figure) and at least one pad 810, the second side of the first semiconductor device 100 and the second side of the third semiconductor device 800 being connected, for example, by a connection layer; a second packaging layer 900 is formed on a first surface and a surface adjacent to the first surface of the third semiconductor device 800, the positioning protrusion 820 of the third semiconductor device 800 is located on the second packaging layer 900, at least one fourth via 910 is disposed on the second packaging layer 900, and the bottom of the fourth via 910 is located in the region of the pad 810 of the third semiconductor device 800 and contacts the pad 810 of the third semiconductor device 800; the fourth via 910 does not overlap with a projection of the positioning bump 820 of the third semiconductor device 800 on the first side of the third semiconductor device 800; the second wiring layer 1000 is located on a side of the second packaging layer 900 far from the first semiconductor device 100, and is electrically connected to the pad 810 of the third semiconductor device 800 through the fourth via 910.
The positioning bumps 820 on the third semiconductor device 800 may be wrapped on the second packaging layer 900, or may be exposed to the second packaging layer 900, for example, the upper surface thereof is flush with the upper surface of the second packaging layer 900. The first semiconductor device 100 and the third semiconductor device 800 are arranged back to back, and the first semiconductor device 100 and the third semiconductor device 800 are connected by welding or adhesive bonding, because the position of the third semiconductor device 800 relative to the first semiconductor device 100 may be shifted in the welding or adhesive bonding process, if the positioning points on the package frame 400 or the first semiconductor device 100 are used for via hole processing, the precision is poor, and therefore the second positioning bump 820 is arranged on the third semiconductor device 800, and the position precision of the fourth via hole 910 can be improved.
As shown in fig. 15, the number of the first wiring layers 300 is at least one, at least one fourth wiring layer 1100 is disposed on one side of the second surface of the first semiconductor device 100, and the number of the first wiring layers 300 is the same as that of the fourth wiring layer 1100. The multilayer wiring structure can provide a more flexible wiring mode, the number of wiring layers on two sides of the semiconductor device is the same, and warping of the packaging module can be reduced. Compared with a single wiring layer structure, the multi-wiring layer structure increases the heat dissipation path of the embedded packaging module, and improves the heat dissipation capability and reliability of the embedded packaging module.
According to the embedded packaging module provided by the embodiment of the disclosure, the positioning bulge is arranged on the semiconductor device and is used as the identification point for the laser processing identification point to carry out the via hole processing, so that the position precision of the via hole is improved. As shown in fig. 16 and 17, D is the drill hole position deviation, D is the via diameter, and P is the pitch of the adjacent pads. By arranging the positioning bumps on the semiconductor device, the processing deviation of a lead frame, the surface mounting deviation of the semiconductor device and the deviation of an ABF (Ajinomoto Build-Up Film) pressing semiconductor device in the related technology, which are included by the position deviation of the drilling hole, are solved, and the position deviation of the drilling hole can be reduced from 30um to 5 um. The surface of the semiconductor device is simultaneously provided with the positioning bulges and the through holes, so that the laser drilling position can be improved, and the large-current through-flow conforming to the power module can be realized; the reduction of the laser drilling position deviation D is beneficial to improving the process yield, improving the through-current capacity, the heat dissipation capacity and the packaging reliability of the module.
The reduction of the drilling position deviation D can increase the diameter D of the through hole at the joint of the through hole and the pad of the semiconductor device and the number of the through holes on a single pad, thereby increasing the through-current capacity of the through hole of the pad and the heat dissipation capacity of a chip and further improving the reliability of packaging; the drilling deviation D is reduced, so that the distance P between two chip bonding pads can be reduced, and the packaging of the semiconductor device with small-spacing bonding pads is realized.
The current flow from the cell to the pad is shown in fig. 18, and an increase in the diameter d of the vias, an increase in the number of vias on a single pad, and a decrease in the pitch of the pads all reduce the lateral distance that current flows from the cell to the pad, thereby reducing the internal resistance of the semiconductor device.
In this exemplary embodiment, a method for packaging an embedded package module is first provided, as shown in fig. 19, the method includes the following steps:
step S110, providing a first semiconductor device 100, where a first surface of the first semiconductor device 100 has at least one pad 110;
step S120, providing at least two positioning bumps 120 on a first surface of the first semiconductor device 100;
step S130, pressing the first encapsulation layer 200, and covering the first surface of the first semiconductor device 100 and a surface adjacent to the first surface;
step S140, processing at least one first via hole 210 on the first package layer 200 by a laser drilling process, wherein a pattern recognition point confirmed by a laser drilling position is a positioning bump 120 on the first surface of the first semiconductor device 100, so that the bottom of the first via hole 210 is located in the area of the pad 110 and contacts the pad 110, and the projection of the first via hole 210 and the positioning bump 120 on the first surface of the first semiconductor device 100 do not overlap;
step S150, filling metal into the first via hole 210;
step S160, forming a first wiring layer 300, where the first wiring layer 300 is located on a side of the first encapsulation layer 200 away from the first semiconductor device 100, and the first wiring layer 300 is electrically connected to the pad 110 through the first via 210.
According to the packaging method of the embedded packaging module provided by the embodiment of the disclosure, the at least two positioning protrusions 120 are arranged on the first surface of the semiconductor device and are used as positioning points for processing the via holes, so that the precision of processing the corresponding via holes in the corresponding packaging layer is improved, and the current circulation requirement is realized through the processed via holes; due to the improvement of the processing precision of the via holes, the number of the via holes on the pad can be increased, the circulation capacity and the heat dissipation capacity of current on the pad are further improved, and the reliability of packaging is further improved.
In step S120, at least two positioning bumps 120 may be disposed on the first surface of the first semiconductor device 100 through a ball bonding process or a plating process, the at least two positioning bumps 120 may be disposed on the same bonding pad 110, or each positioning bump 120 is respectively disposed on one bonding pad 110, for example, three positioning bumps 120, one of which is disposed on one bonding pad 110, and the other two of which are disposed on the other bonding pad 110. Of course, in practical applications, the positioning bump 120 may also be disposed on the first surface of the semiconductor device in a region other than the pad 110, and the like, which is not specifically limited in this disclosure.
In step S130, the first encapsulation layer 200 may be pressed to cover the first surface of the first semiconductor device 100 and a surface adjacent to the first surface, and the first encapsulation layer 200 may be a plastic layer.
When the embedded package module further includes a package frame 400, before the step S120, the method may further include adhering an adhesive tape to an end surface of the package frame 400, placing the semiconductor device into the package frame 400, where a first surface of the semiconductor device is away from an end of the package frame 400 to which the adhesive tape is adhered; step S120 may further include laminating a plastic layer on the second surface of the semiconductor device.
In step S140, at least a first via hole 210 may be processed on the first packaging layer 200 through a laser drilling process, wherein a pattern recognition point confirmed by a laser drilling position is the positioning bump 120 on the first side of the first semiconductor device 100, so that the bottom of the first via hole 210 is located in the area of the pad 110 and contacts the pad 110, and the projection of the first via hole 210 and the positioning bump 120 on the first side of the first semiconductor device 100 does not overlap.
By using the positioning protrusion 120 as a pattern recognition point, the position accuracy of the first via hole 210 is improved, and the laser drilling position deviation D is reduced, which is helpful for improving the process yield, improving the through-current capability, the heat dissipation capability and the packaging reliability of the module.
In steps S150 and S160, the first via hole 210 may be filled and the first wiring layer 300 may be formed by a plating process, and the first via hole 210 and the first wiring layer 300 may be formed by one-step plating or may be formed by separate plating.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (17)

1. An embedded package module, comprising:
the first semiconductor device is provided with a first surface and a second surface, the first surface of the first semiconductor device is provided with at least two positioning bulges and at least one bonding pad, and the upper surfaces of the positioning bulges are higher than the upper surfaces of the bonding pads;
the first packaging layer is formed on a first surface of the first semiconductor device and a surface adjacent to the first surface, the positioning protrusion is located on the first packaging layer, at least one first through hole is formed in the first packaging layer, and the bottom of the first through hole is located in the pad and is in contact with the pad;
and the first wiring layer is positioned on one side of the first packaging layer, which is far away from the first semiconductor device, and is electrically connected with the bonding pad through the first through hole.
2. The embedded package module of claim 1, wherein at least one of the positioning bumps of the at least two positioning bumps is disposed on the pad.
3. The embedded package module of claim 2, wherein at least one of the at least two positioning bumps is disposed on the pad, and at least one of the first vias is further disposed on the pad on which the positioning bump is disposed.
4. The embedded package module of claim 1, wherein the first via does not overlap a projection of the positioning bump on the first side of the first semiconductor device.
5. The embedded package module of claim 1, wherein the positioning bump is coated on the first package layer, at least a second via is further disposed on the first package layer, at least a portion of the positioning bump is disposed on at least one of the pads, and a projection of the second via contacting the positioning bump disposed on the pad and on the first surface of the first semiconductor device at least partially overlaps.
6. The embedded package module of claim 5, wherein the second via is electrically connected to the first routing layer.
7. The embedded package module of claim 1, further comprising a package frame having a receiving area, the first semiconductor device being disposed in the receiving area.
8. The embedded package module of claim 7, wherein the number of the first semiconductor devices is plural and all disposed in the receiving area.
9. The embedded package module of claim 7, wherein the number of the first semiconductor devices is plural, the number of the receiving areas is plural, and at least one first semiconductor device is disposed in each receiving area.
10. The embedded package module of claim 7, wherein the package frame comprises a plurality of metal blocks that are not connected to each other, and at least one of the first semiconductor devices is electrically connected to at least one of the metal blocks through the first via.
11. The embedded package module of claim 1, further comprising a package frame, the first semiconductor device and the package frame being arranged in a stack.
12. The embedded packaging module of claim 1, wherein the embedded packaging module further comprises:
the second semiconductor device is provided with a first surface and a second surface, the first surface of the second semiconductor device is provided with at least two positioning bulges and at least one bonding pad, and the second surface of the second semiconductor device is connected to the first wiring layer;
the third packaging layer is formed on one side, far away from the first semiconductor device, of the first wiring layer and covers the second semiconductor device, the positioning protrusion of the second semiconductor device is located on the third packaging layer, at least one third through hole is arranged on the third packaging layer, and the bottom of the third through hole is located in the area of the bonding pad of the second semiconductor device and contacts the bonding pad of the second semiconductor device; the third via hole is not overlapped with the projection of the positioning bulge of the second semiconductor device on the first surface of the second semiconductor device;
and the third wiring layer is formed on the third packaging layer.
13. The embedded packaging module of claim 1, wherein the embedded packaging module further comprises:
the first surface of the third semiconductor device is provided with at least two positioning bulges and at least one bonding pad, and the second surface of the first semiconductor device is connected with the second surface of the third semiconductor device through a connecting layer;
the second packaging layer is formed on a first surface of the third semiconductor device and a surface adjacent to the first surface, the positioning protrusion of the third semiconductor device is located on the second packaging layer, at least one fourth through hole is formed in the second packaging layer, and the bottom of the fourth through hole is located in the area of the bonding pad of the third semiconductor device and contacts the bonding pad of the third semiconductor device; the fourth via hole is not overlapped with the projection of the positioning bulge of the third semiconductor device on the first surface of the third semiconductor device;
and the second wiring layer is positioned on one side of the second packaging layer, which is far away from the first semiconductor device, and is electrically connected with the bonding pad of the third semiconductor device through the fourth through hole.
14. The embedded package module of claim 1, wherein the positioning bump is exposed to the first package layer, the positioning bump being electrically connected to the first wiring layer.
15. The embedded package module of claim 1, wherein the first via is a solid metal via.
16. The embedded packaging module of claim 1, wherein the number of the first wiring layers is at least one, at least one fourth wiring layer is disposed on one side of the second surface of the first semiconductor device, and the number of the first wiring layers and the fourth wiring layers is the same.
17. A packaging method of an embedded packaging module is characterized by comprising the following steps:
providing a first semiconductor device, wherein a first side of the first semiconductor device is provided with at least one bonding pad;
arranging at least two positioning bulges on the first surface of the first semiconductor device, wherein the upper surfaces of the positioning bulges are higher than the upper surfaces of the bonding pads;
pressing a first packaging layer, and covering a first surface of the first semiconductor device and a surface adjacent to the first surface;
processing at least one first via hole on the first packaging layer through a laser drilling process, wherein a mode identification point confirmed by a laser drilling position is a positioning bump on the first side of the first semiconductor device, so that the bottom of the first via hole is positioned in the area of the bonding pad and contacts the bonding pad, and the projection of the first via hole and the projection of the positioning bump on the first side of the first semiconductor device are not overlapped;
filling metal into the first via hole;
and forming a first wiring layer, wherein the first wiring layer is positioned on one side of the first packaging layer far away from the first semiconductor device, and the first wiring layer is electrically connected with the bonding pad through the first through hole.
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