CN111448656B - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN111448656B
CN111448656B CN201980006159.5A CN201980006159A CN111448656B CN 111448656 B CN111448656 B CN 111448656B CN 201980006159 A CN201980006159 A CN 201980006159A CN 111448656 B CN111448656 B CN 111448656B
Authority
CN
China
Prior art keywords
semiconductor device
semiconductor
semiconductor chip
insulating film
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201980006159.5A
Other languages
English (en)
Other versions
CN111448656A (zh
Inventor
山田教文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of CN111448656A publication Critical patent/CN111448656A/zh
Application granted granted Critical
Publication of CN111448656B publication Critical patent/CN111448656B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04034—Bonding areas specifically adapted for strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/2912—Antimony [Sb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37012—Cross-sectional shape
    • H01L2224/37013—Cross-sectional shape being non uniform along the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40105—Connecting bonding areas at different heights
    • H01L2224/40106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/4013—Connecting within a semiconductor or solid-state body, i.e. fly strap, bridge strap
    • H01L2224/40132—Connecting within a semiconductor or solid-state body, i.e. fly strap, bridge strap with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40227—Connecting the strap to a bond pad of the item
    • H01L2224/40229—Connecting the strap to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404—Connecting portions
    • H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
    • H01L2224/40499—Material of the auxiliary connecting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/84399—Material
    • H01L2224/844—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/84401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/84411—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/84399—Material
    • H01L2224/844—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/84417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/8442—Antimony [Sb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/84399—Material
    • H01L2224/844—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/84438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/84447—Copper [Cu] as principal constituent

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

半导体装置包括：半导体芯片(30)，其包含半导体基板(29)、半导体基板(29)的上表面的上表面电极(31‑1、31‑2)、选择性地覆盖上表面电极(31‑1、31‑2)的上表面的端部的绝缘膜(34)以及覆盖上表面电极(31‑1、31‑2)的上表面的在绝缘膜(34)的开口部暴露的部分的镀层(33‑1、33‑2)；金属布线板(60)，其包含位于绝缘膜(34)的上方和镀层(33‑1、33‑2)的上方的接合部(61)，并自接合部(61)的下表面向上方设有槽部(66‑1)；以及软钎料部(25)，其填满槽部(66‑1)，将接合部(61)的下表面与镀层(33‑1、33‑2)接合，在俯视时，绝缘膜(34)与镀层(33‑1、33‑2)之间的边界线AR、AL配置于槽部(66‑1)的内侧，软钎料部(25)在边界线AR、AL上的厚度厚于在镀层(33‑1、33‑2)上的厚度。

Description

半导体装置
技术领域
本发明涉及一种能够作为功率半导体模块使用的半导体装置。
背景技术
在功率半导体模块中，公知有在具有主电极和分割主电极的绝缘膜的半导体芯片使用软钎料接合金属布线板的情况。例如，专利文献1公开有一种利用软钎料连接半导体芯片的电极部和作为金属片的框架的半导体装置。专利文献2公开有一种将形成为波形的引线的与波谷相当的部分同半导体基板表面的电极接合并使与波峰相当的部分位于壳体的表面附近的电力用半导体装置。
专利文献3中公开有一种利用借助凸块与半导体芯片的电极接合的接合构件和散热板夹着半导体芯片的半导体装置。专利文献4中公开有一种与发射极连接的构件在与保护膜相对的位置具有狭缝的半导体装置。专利文献5公开有一种为了防止栅极-发射极之间的短路故障而除栅电极的布线的保护膜之外还包括配置在栅电极的布线与软钎料之间的绝缘层的半导体装置。
在这样的半导体模块中，在实施温度循环试验时，有时会由于金属布线板、软钎料而引起主电极产生裂纹。
现有技术文献
专利文献
专利文献1：日本特开2006-216736号公报
专利文献2：日本特开2006-190728号公报
专利文献3：日本特开2000-349207号公报
专利文献4：日本特开2012-191012号公报
专利文献5：日本特开2011-66377号公报
发明内容
发明要解决的问题
鉴于上述问题点，本发明的目的在于提供一种能够抑制主电极产生裂纹并提高结构上的可靠性的半导体装置。
用于解决问题的方案
为了达成上述目的，本发明的一技术方案的主旨为一种半导体装置，该半导体装置包括：(a)半导体芯片，其包含具有上表面的半导体基板、配置于半导体基板的上表面的上表面电极、选择性地覆盖上表面电极的上表面的端部的绝缘膜以及覆盖上表面电极的上表面的在绝缘膜的开口部暴露的部分的镀层；(b)金属布线板，其包含位于绝缘膜的上方和镀层的上方的接合部并自接合部的下表面朝向上方设有槽部；以及(c)软钎料部，其填满槽部，将接合部的下表面与镀层接合。本发明的一技术方案的半导体装置的绝缘膜与镀层之间的边界线在俯视时配置于槽部的内侧，软钎料部在边界线上的厚度厚于在镀层上的厚度。
发明的效果
根据本发明，能够提供一种能够抑制主电极产生裂纹并提高结构上的可靠性的半导体装置。
附图说明
图1是说明本发明的实施方式的半导体装置的外观的立体图。
图2是说明本发明的实施方式的半导体装置的内部构造的立体图，其中，省略了冷却器、壳体以及密封树脂的图示。
图3是说明本发明的实施方式的半导体装置的层叠基板、半导体芯片以及金属布线板的俯视图。
图4是从图3的IV-IV方向观察的剖视图。
图5是说明本发明的实施方式的半导体装置的金属布线板的立体图。
图6是说明本发明的实施方式的半导体装置的半导体芯片和金属布线板的配置的俯视图。
图7是从图6的VII-VII方向观察的剖视图。
图8是表示与不具有槽部的金属布线板接合的上表面电极的塑性应变振幅的等值线图。
图9是表示与具有宽度为0.8mm的槽部的金属布线板接合的上表面电极的塑性应变振幅的等值线图。
图10是表示与具有宽度为1.3mm的槽部的金属布线板接合的上表面电极的塑性应变振幅的等值线图。
图11是表示与具有宽度为2.0mm的槽部的金属布线板接合的上表面电极的塑性应变振幅的等值线图。
图12是表示绝缘膜和槽部之间的距离与上表面电极的塑性应变振幅的最大值的关系的图。
具体实施方式
以下参照附图说明本发明的实施方式。在附图的记载中，对相同或类似的部分标注相同或类似的附图标记，并省略重复的说明。但是，附图是示意性的，厚度与平面尺寸的关系、各层的厚度的比率等存在与实际不同的情况。另外，在附图相互之间也可能包含尺寸的关系、比率不同的部分。另外，以下所示的实施方式是例示用于将本发明的技术思想具体化的装置、方法的，本发明的技术思想并不将构成部件的材质、形状、构造、配置等特别限定为下述的材质、形状、构造、配置等。
另外，以下说明中的上下等方向的定义仅是为了方便说明的定义，并不用于限定本发明的技术思想。例如，当然，若将对象旋转90°进行观察，则上下变换为左右进行读取，若将对象旋转180°进行观察，则上下颠倒过来进行读取。
(半导体装置)
如图1所示，本发明的实施方式的半导体装置100包括半导体芯片30和金属布线板60。半导体装置100可以包含冷却器10、层叠基板11、壳体20以及密封树脂21。半导体芯片30为具有如下功能的元件，即：利用形成于半导体基板29(参照图7)的含有pn结的活性区域控制主电流的流动。冷却器10的上表面与层叠基板11的下表面直接或间接地接触。在壳体20的内部填充有用于密封层叠基板11的上表面、半导体芯片30以及金属布线板60等的密封树脂21。实施方式的半导体装置100例如为使用作为功率半导体的半导体芯片30将输入的电力转换为规定的电力的电力用半导体装置(功率器件)。在实施方式中，为了容易理解，对包括一个层叠基板11、一个半导体芯片30以及一个金属布线板60的半导体装置100进行说明。半导体装置100可以包括多个层叠基板、多个半导体芯片以及多个金属布线板等。另外，对用于与外部连接的端子、布线以及信号处理电路等省略图示和说明。
冷却器10使因主电流流入活性区域导致半导体芯片30等产生的热量经由层叠基板11向外部放出。冷却器10为例如由铝(Al)等导热率较高的材料形成的大致呈长方体状的散热器。为了使冷却器10的表面积增大以提高散热性能，冷却器10可以具有多个散热片。该情况下，能够将散热片之间设为制冷剂的流路。制冷剂例如可以是乙二醇水溶液、水等液体，也可以是空气那样的气体。另外，还能够采用像氟利昂那样可相变的制冷剂。
壳体20例如具有矩形的框形状，以隔着密封树脂21包围层叠基板11、半导体芯片30、金属布线板60等的方式设置在冷却器10的上表面。壳体20可以由金属等导电性材料形成，也可以由树脂等绝缘材料形成。作为密封树脂21，例如能够采用环氧树脂、马来酰亚胺树脂等绝缘性能和成形性良好的树脂。能够利用与这些树脂混合的填料的量，来调整密封树脂21的线膨胀系数、杨氏模量。
如图2～图4所示，层叠基板11包括绝缘基板13、与绝缘基板13的下表面接合的金属板12以及与绝缘基板13的上表面接合的电路图案层(14、15、16)。层叠基板11例如能够采用在陶瓷基板的表面直接接合铜而成的DCB基板、利用活性金属钎焊法在陶瓷基板的表面配置金属而成的AMB基板等。层叠基板11利用软钎料部22与冷却器10的上表面接合，与冷却器10热连接。作为软钎料部22，例如能够采用锡(Sn)-锑(Sb)系或Sn-Sb-银(Ag)系的高强度软钎料。层叠基板11可以以其主表面与X-Y面平行的方式配置。
如图2～图4所示，电路图案层(14、15、16)具有第1电路图案层14、第2电路图案层15以及多个第3电路图案层16。在第1电路图案层14的上表面搭载半导体芯片30，在第2电路图案层15的上表面接合金属布线板60。电路图案层(14、15、16)与构成半导体芯片30的半导体元件电连接，并与构成半导体芯片30的半导体元件之间传递电力和电信号等。电路图案层(14、15、16)可以包含形成于绝缘基板13的上表面的金属布线、焊盘等，也可以包含信号处理电路等。
如图7所示，半导体芯片30包含半导体基板29、配置于半导体基板29的上表面的上表面电极31-1等、将上表面电极31-1等的端部选择性地覆盖的绝缘膜34等以及覆盖上表面电极31-1的在绝缘膜34等的开口部暴露的部分等的镀层33-1等。包括上表面电极31-1等和镀层33-1等的第1主电极被形成为网格状的绝缘膜34等分割开。
半导体基板29具有上表面和与上表面相对的下表面。半导体基板29为例如由硅(Si)、碳化硅(SiC)、氮化镓(GaN)等半导体材料形成的半导体片。半导体芯片30的厚度例如为50μm～450μm左右，半导体芯片30的形状例如为一边具有5mm～15mm左右的长度的矩形形状等。形成于半导体基板29并构成半导体芯片30的半导体元件包含绝缘栅双极型晶体管(IGBT)、功率MOSFET等、纵向型半导体元件。半导体元件可以包含双极结型晶体管(BJT)、场效应晶体管(FET)、静电感应晶体管(SIT)、门极可关断(GTO)晶闸管、静电感应(SI)晶闸管等。而且，除这些半导体开关元件以外，还可以包含肖特基势垒二极管等二极管。除此之外，构成半导体芯片30的半导体元件还可以包含将IGBT和续流二极管设于一个芯片而成的反向阻断IGBT(RB-IGBT)、反向导通IGBT(RC-IGBT)。
作为半导体芯片30，例如，例示了在半导体基板29的上表面配置多个第1主电极、在下表面配置第2主电极的纵向型结构的元件。在构成半导体芯片30的半导体元件为IGBT、BJT的情况下，第1主电极是指发射极和集电极中的任一电极，第2主电极是指另一电极。在IGBT的情况下，控制电极是指栅电极，在BJT的情况下，控制电极是指基极。在FET、SIT等的情况下，第1主电极是指源电极和漏电极中的任一电极，第2主电极是指另一电极，控制电极是指栅电极。在GTO晶闸管等晶闸管的情况下，第1主电极是指阳极电极和阴极电极中的任一电极，第2主电极是指另一电极，控制电极是指栅电极。
如图4所示，半导体芯片30借助软钎料部23与第1电路图案层14的上表面接合。半导体芯片30可以以其主表面与X-Y面平行的方式配置。半导体芯片30的第2主电极与第1电路图案层14电连接，并且半导体芯片30隔着层叠基板11与冷却器10热连接。半导体芯片30借助软钎料部25与金属布线板60接合。软钎料部23的厚度例如为0.05mm～0.4mm，优选为0.1mm～0.2mm。软钎料部25在半导体芯片30所包含的镀层33-1～33-6(参照图3)的上表面上的厚度为0.05mm～0.4mm，优选为0.05mm～0.3mm，更期望为0.1mm～0.2mm。作为软钎料部23、25，例如能够采用Sn-Sb系、Sn-铜(Cu)系的软钎料。
如图3所示，在半导体芯片30配置有分别构成第1主电极的多个镀层33-1～33-6和多个电极焊盘39。多个镀层33-1～33-6的图案之间配置有多个栅极流道(gate runner)36-1～36-3。镀层33-1～33-6的形状在俯视时均可以呈矩形。在此，“栅极流道36-1～36-3”为控制构成半导体芯片30的半导体元件的主电流的控制电极的布线。以包围多个镀层33-1～33-6的图案的配置的方式设有保护环35的图案。此外，为了使附图简单化，图4中省略了镀层33-1～33-6、保护环35、多个栅极流道36-1～36-3、多个电极焊盘39等的图示。此外，在本说明书中，“俯视”是指从与半导体基板29(参照图7)的上表面垂直的方向(Z轴的正方向)观察的情况。
在半导体芯片30的上表面，如图3所示，两条栅极流道36-1、36-2沿着互相平行的方向(Y轴方向)延伸。而且，一条栅极流道36-3沿着与栅极流道36-1、36-2正交的方向(X轴方向)延伸。六个镀层33-1～33-6利用三条栅极流道36-1～36-3配置成互相分开的2×3矩阵状。保护环35沿着半导体芯片30的四条边包围镀层33-1～33-6。电极焊盘39作为平面图案互相分开地配置在保护环35内。
如图2～图4所示，金属布线板60为例如由Cu、Cu合金、Al、Al合金等形成的引线框。金属布线板60具有例如0.5mm～1.5mm左右的厚度。金属布线板60由第1接合部61、与第1接合部61连续的第1立起部62以及与第1立起部62连续的连接部63形成为第1弯曲形状(日文：クランク形状)。第1接合部61的下表面借助软钎料部25与半导体芯片30的上表面接合。金属布线板60还由连接部63、与连接部63连续的第2立起部64以及与第2立起部64连续的第2接合部65形成为第2弯曲形状。第2接合部65的下表面借助软钎料部24与第2电路图案层15的上表面接合。第1接合部61的与镀层33-1～33-6的上表面相对的面包含实质上与半导体芯片30的上表面平行的面。第2接合部65的下表面实质上与第2电路图案层15的上表面平行地相对。作为软钎料部24，例如能够采用Sn-Cu系、Sn-Sb系等的软钎料。
第1立起部62在第1接合部61的靠连接部63侧的端部沿着自构成半导体芯片30的上表面的平面朝向上方的方向、例如直角方向延伸，与第1接合部61形成为大致L字形。第2立起部64在第2接合部65的靠连接部63侧的端部沿着自构成第2电路图案层15的上表面的平面朝向上方的方向、例如直角方向延伸，与第2接合部65形成为大致L字形。在实施方式中，第1立起部62和第2立起部64沿着与半导体芯片30的上表面和第2电路图案层15的上表面垂直的方向(Z轴方向)延伸。金属布线板60例如使用压力机等以具有第1接合部61、第1立起部62、连接部63、第2立起部64以及第2接合部65的方式适当地以90°弯曲加工而成。
第1接合部61与第1立起部62所成的角和第2立起部64与第2接合部65所成的角分别可以从45°以上且135°以下的范围内选择，优选从80°以上且100°以下的范围内选择，实质上可以为90°。另外，连接部63的主表面可以实质上与第1接合部61的主表面和第2接合部65的主表面平行。第1接合部61的主表面、连接部63的主表面以及第2接合部65的主表面可以相对于半导体芯片30的主表面、第1电路图案层14的主表面以及第2电路图案层15的主表面略微倾斜地配置。
半导体芯片30的第1主电极经由金属布线板60与第2电路图案层15电连接。即，第1接合部61与半导体芯片30的第1主电极连接，第2接合部65与第2电路图案层15连接。
如图5所示，第1接合部61在与半导体芯片30的第1主电极接合的接合面(下表面)具有三个槽部66-1～66-3。三个槽部66-1～66-3的位置以与图3所示的三条栅极流道36-1～36-3分别对应的方式设置。由图6可知，在俯视时，槽部66-1～66-3的图案以将栅极流道36-1～36-3的图案包含在内的方式排列。即，栅极流道36-1～36-3位于槽部66-1～66-3各自的中央部的位置，收纳于槽部66-1～66-3各自的内侧。如图5所示，槽部66-1～66-3分别自第1接合部61的接合面朝向相反侧的背面凹陷。由此，第1接合部61在槽部66-1～66-3处的厚度薄于在其他部位处的厚度。
如图6所示，在第1接合部61的接合面，两个槽部66-1、66-2沿着互相平行的方向(Y轴方向)延伸。而且，一个槽部66-3沿着与槽部66-1、66-2正交的方向(X轴方向)延伸。结果是，如图5所示，在第1接合部61的接合面，以形成2×3矩阵的方式呈岛状分离开的台地部67-1～67-6以台面状突出。即，第1接合部61的接合面的利用槽部66-1～66-3分割开的六个区域相当于六个具有平坦的上表面的台地部67-1～67-6。第1接合部61在台地部67-1～67-6处的厚度厚于在其他部位处的厚度。
如图6所示，槽部66-1～66-3的宽度D大于栅极流道36-1～36-3的宽度d。例如图7所示，槽部66-1的侧面以越去向第1接合部61的背面侧而宽度D越小的方式倾斜，与槽部66-1的平行于背面的顶部的面连结。虽省略图示，但同样地，槽部66-2、66-3的侧面也以越去向第1接合部61的背面而宽度D越小的方式倾斜，与槽部66-2、66-3的平行于背面的顶部的面连结。如图6所示，台地部67-1～67-6作为平面图案位于镀层33-1～33-6各自的中央部的位置，收纳于镀层33-1～33-6各自的内侧。
如图7所示，半导体芯片30具有将配置于上表面的上表面电极31-1和配置于上表面电极31-1的上表面的镀层33-1包含在内的第1主电极的一区域。半导体芯片30还具有将配置于上表面的上表面电极31-2和配置于上表面电极31-2的上表面的镀层33-2包含在内的第1主电极的另一区域。上表面电极31-1、31-2例如由Al、Al-Si等金属、合金形成。镀层33-1、33-2由含有镍(Ni)等的金属、合金形成。在图7中，仅示出了与镀层33-1和镀层33-2对应的两个第1主电极。关于图6所示的另外的四个镀层33-3～33-6，当然也与图7相同，分别以具有上表面电极的构造构成第1主电极的区域。此外，以下在统称全部的上表面电极的情况下，总括起来表示为“上表面电极”。半导体芯片30具有配置于半导体基板29的下表面的下表面电极28。
另外，实施方式的半导体装置的“栅极流道36-1”定义为将配置于半导体芯片30的上表面的布线层32和覆盖布线层32的绝缘膜34包含在内的构造。布线层32例如由金属、多晶硅等导电性材料形成。布线层32例如为将构成半导体芯片30的半导体元件的控制电极与电极焊盘39之间电连接的布线的图案。绝缘膜34使布线层32与镀层33-1～33-6、上表面电极31-1、31-2及软钎料部25绝缘。虽然图7中省略图示，但其他的栅极流道36-2～36-3也同样地定位为将分别配置于半导体芯片30的上表面的多个布线层和分别覆盖布线层的绝缘膜包含在内的构造。保护环35和形成栅极流道36-1～36-3的表面的绝缘膜例如可以由聚酰亚胺等连续的绝缘膜构成。此外，电极焊盘39也可以用于温度检测用电极等。栅极流道36-1～36-3可以配置为在俯视时呈网格状。
如图7所示，绝缘膜34选择性地覆盖上表面电极31-1、31-2各自的上表面的端部，镀层33-1、33-2覆盖上表面电极31-1、31-2的上表面各自在绝缘膜34的开口部(窗部)暴露的部分，并与绝缘膜34接触。因此，在上表面电极31-1、31-2的上表面共存有三种材料，形成有构成边界的区域。在上表面电极31-1、31-2的上表面成对地存在右侧边界线AR和左侧边界线AL。在右侧边界线AR处，上表面电极31-1的上表面、镀层33-1的端部以及绝缘膜34的端部这三者的物理性质不同的三种材料呈线状共存。在左侧边界线AL处，上表面电极31-2的上表面、镀层33-2的端部以及绝缘膜34的端部这三者的物理性质不同的三种材料呈线状共存。在图7的剖视图的图示中，右侧边界线AR和左侧边界线AL表示为点，但实质上是沿着与图7的剖视图的纸面垂直的方向延伸的线。沿着与纸面垂直的方向延伸的右侧边界线AR和左侧边界线AL的形状在图8～图11的平面图案中由虚线表示。边界线AR、AL沿着绝缘膜34的开口部的内侧划分形成。边界线AR、AL可以具有宽度，线宽可以沿着延伸方向变化，另外也可以沿着延伸方向起伏。
在右侧边界线AR的区域中，在上表面电极31-1上的位于绝缘膜34的端部与镀层33-1之间的部位容易产生间隙(空隙)，软钎料部25能够进入右侧边界线AR处的间隙而与上表面电极31-1的上表面的暴露部位接触。同样地，在左侧边界线AL的区域中，在绝缘膜34的端部与镀层33-2的端部之间容易产生间隙，软钎料部25能够进入左侧边界线AL处的间隙而与上表面电极31-2的上表面的暴露部位接触。如上所述，层叠基板11、半导体芯片30以及金属布线板60利用密封树脂21密封。因而，在对半导体芯片30实施温度循环试验时，由于随着温度变化产生的伸缩，图2～图6所示的第1立起部62推压或拉伸软钎料部25、镀层33-1、33-2以及上表面电极31-1、31-2。此时，上表面电极31-1、31-2在边界线AR、AL处的塑性应变振幅大于在其他部位处的塑性应变振幅，而可能在上表面电极31-1、31-2产生裂纹。特别是，第1立起部62侧的栅极流道36-2处的振幅具有变大的倾向。而且，还可能以在上表面电极31-1、31-2产生的裂纹为起点而在半导体芯片30也产生裂纹。
相对于此，如图7所示，在实施方式的半导体装置100中，形成一对边界线AR、AL的、绝缘膜34与镀层33-1、33-2之间的边界位于槽部66-1的内侧。如图6所示，在俯视时，栅极流道36-1所包含的绝缘膜34(参照图7)与镀层33-1、33-2之间的边界线AR、AL(参照图7)与栅极流道36-1的缘部的位置大致一致，配置于槽部66-1的内侧。如图7所示，由于软钎料部25以填满槽部66-1的方式形成，因此，位于右侧边界线AR与左侧边界线AL之间的区域的绝缘膜34的正上方的软钎料部25的厚度T1厚于镀层33-1、33-2的正上方的软钎料部25的厚度T2。因此，上表面电极31-1、31-2的相对于自金属布线板60承受的力而产生的应力由于槽部66-1内的软钎料部25而得到缓和，从而能够降低塑性应变振幅，因此能够提高半导体装置100的可靠性。图7中未图示的另外四个镀层33-3～33-6也同样如此。槽部66-1的相对于台地部67-1、67-2的主表面而言的深度D1在Z轴方向上为0.2mm～0.8mm，优选为0.4mm～0.6mm。
图8～图11是表示仅使槽部66-1～66-3的宽度D变化来模拟实施方式的半导体装置的上表面电极的最大剪切塑性应变振幅(本说明书中，还简称作塑性应变振幅)的结果的等值线图。使用有限元法分析软件ADINA(注册商标，商品名称)进行模拟。在图8～图11中，以11个级别的浓度表示0～1.8％的范围内的塑性应变振幅，浓度越大则表示塑性应变振幅越大。此外，图中的虚线表示栅极流道36-1～36-3的缘部、即表示一对边界线AR、AL各自的位置。在图8～图11中，在由虚线包围了两条边或三条边的矩形的内部的区域等存在上表面电极，但未图示。
在模拟中，将上表面电极的材料设为Al-Si，并将厚度设为5μm，将镀层33-1～33-6的材料设为Ni，并将厚度设为4.5μm。另外，将软钎料部25的材料设为Sn-0.7Cu，并将厚度设为100μm，从而将0.2％屈服强度设定得较低。金属布线板60的材料设为Cu(具体而言C1020-1/2H、线膨胀系数为16.7×10-6/℃)，并将厚度设为1.0mm，槽部66-1～66-3的深度D1设为0.5mm。将绝缘膜34的宽度d设为260μm。在以上的条件下，用1秒钟的时间将半导体芯片30的温度从40℃加热到175℃之后，用9秒钟的时间冷却到40℃，算出此时的应变的差将其作为塑性应变振幅。
图8是模拟在槽部66-1～66-3的宽度D为0、即在第1接合部61的接合面(下表面)未设置槽部66-1～66-3的情况下的上表面电极的塑性应变振幅的结果。由图8可知，上表面电极的塑性应变振幅沿着在图8的中央部以上侧的两个顶部被实施了倒角的矩形(半圆柱形)示出的第1接合部61的接合面的轮廓变得较大。在俯视时，在第1立起部62与夹着栅极流道36-2的区域之间，塑性应变振幅相对地变大。特别是，在图8的半圆柱形的轮廓中，在右下方由单点划线的圆表示的夹着栅极流道36-2的区域的塑性应变振幅变大，其值最大约为1.55％。在栅极流道36-2与第1立起部62之间，塑性应变振幅连续地变化，并在第1立起部62侧具有第2峰值，其值约为1.29％。
图9是模拟在槽部66-1～66-3的宽度D为0.8mm的情况下的上表面电极的塑性应变振幅的结果。与图8相同，塑性应变振幅沿着第1接合部61的接合面的轮廓变得较大。在图9所示的半圆柱形的轮廓中，右下方的由单点划线的圆包围起来的区域的塑性应变振幅最大，其值最大约为1.74％。在本例子中，也是，在栅极流道36-2与第1立起部62之间，塑性应变振幅连续地变化，并在第1立起部62侧具有第2峰值，其值约为1.23％。
图10是模拟在槽部66-1～66-3的宽度D为1.3mm的情况下的上表面电极的塑性应变振幅的结果。与图8和图9相同，塑性应变振幅沿着第1接合部61的接合面的轮廓变得较大。在图10所示的半圆柱形的轮廓中，右下方的由单点划线的圆包围起来的区域的塑性应变振幅最大，其值最大约为1.54％。在本例子中，也是，在栅极流道36-2与第1立起部62之间，塑性应变振幅连续地变化，并在第1立起部62侧具有第2峰值，其值约为1.16％。
图11是模拟在槽部66-1～66-3的宽度D为2.0mm的情况下的上表面电极的塑性应变振幅的结果。与图8、图9以及图10相同，塑性应变振幅沿着第1接合部61的接合面的轮廓变得较大。在图11所示的半圆柱形的轮廓中，右下方的由单点划线的圆包围起来的区域的塑性应变振幅最大，其值最大约为1.29％。在本例子中，也是，在栅极流道36-2与第1立起部62之间，塑性应变振幅连续地变化，并在第1立起部62侧具有第2峰值，其值约为1.07％。
图12是表示图8～图11的各情况下的塑性应变振幅的图表。横轴表示绝缘膜34的宽度方向上的端部和槽部66-1～66-3的宽度方向上的端部之间的距离，纵轴表示塑性应变振幅。圆形标记(〇)表示夹着栅极流道36-2的区域的最大(第1峰值)的振幅，方形标记(□)表示靠第1立起部62侧的第2峰值的振幅。将图8的未设置槽部66-1～66-3的情况下的数据绘制为距离(横轴)为0mm。塑性应变振幅在夹着栅极流道36-2的区域的、特别是包含绝缘膜34与镀层33-2、33-3之间的边界线的区域具有最大值。
如此，确认的是，槽部66-1～66-3的宽度D越大且绝缘膜34与槽部66-1～66-3之间的距离越大，则上表面电极的塑性应变振幅的最大值越小。并且，确认的是，对于靠第1立起部62侧的塑性应变振幅，也是，设有槽部66-1～66-3且槽部66-1～66-3的宽度D越大，则靠第1立起部62侧的塑性应变振幅就越小。
在图7的剖视图中，绝缘膜34的宽度方向上的缘部为沿着绝缘膜34的延伸方向的缘部，与一对边界线AR、AL各自的位置大致一致。以下，有时由AR、AL表示绝缘膜34的缘部的位置。槽部66-1～66-3的宽度方向上的端部是指与图7所示的槽部66-1的构造的缘部BR、BL相对应的沿着槽部66-1～66-3的延伸方向的缘部。图12的横轴的“距离”表示在图7所示的槽部66-1的构造中被定义的绝缘膜34的右侧的缘部和槽部66-1的右侧的缘部BR之间的在与半导体芯片30的主表面平行的方向(X轴方向)上的距离CR。同样地，“距离”表示绝缘膜34的左侧的缘部和槽部66-1的左侧的缘部BL之间的在与半导体芯片30的主表面平行的方向上的距离CL。以下在总括起来定义全部槽部66-1～66-3的缘部的情况下，统称为“缘部B”。即，图12的横轴的距离表示在图6所示的平面图案中绝缘膜34的缘部与槽部66-1～66-3的缘部B之间的最短距离C＝CR、CL。
图12中的点a1表示图9的情况、即金属布线板60具有宽度为0.8mm的槽部66-1～66-3的情况下的距离C＝CR、CL(0.27mm，参照图7)和上表面电极的塑性应变振幅的最大值。点a2表示图10的情况、即金属布线板60具有宽度为1.3mm的槽部66-1～66-3的情况下的距离C(0.52mm)和上表面电极的塑性应变振幅的最大值。点a3表示图11的情况、即金属布线板60具有宽度为2.0mm的槽部66-1～66-3的情况下的距离C(0.87mm)和上表面电极的塑性应变振幅的最大值。此外，线e表示图8的情况、即金属布线板60不具有槽部66-1～66-3的情况下的上表面电极的塑性应变振幅的最大值。
通常，塑性应变振幅ΔεP遵循由式(1)表示的Manson-Coffin法则：
ΔεP×Nf b＝c…(1)
其中，Nf为疲劳寿命，b、c为材料的常数。根据式(1)，为了延长疲劳寿命，需要减小塑性应变振幅。
如图12所示，可以预想到的是，在距离C大致为0.5mm以下时，与金属布线板60不具有槽部66-1～66-3的情况相比，塑性应变振幅的最大值增大。对此，推定是以下这样的机理。由图8～图11可看出沿着第1接合部61的接合面的轮廓的部位的塑性应变振幅变大。由此，根据槽部66-1～66-3的形成，槽部66-1～66-3的缘部BL、BR也能够看作是第1接合部61的接合面的轮廓，其正下方的塑形应变变大。因而，在边界线AL与缘部BL之间的距离和边界线AR与缘部BR之间的距离较近的情况下，相比不具有槽部66-1～66-3的情况而言，边界线AL、AR处的塑性应变振幅变大。这被推定为图12中与距离C为0mm的情况相比点a1的情况下的塑性应变振幅变大的机理。另一方面可知，上表面电极的塑性应变振幅与软钎料部25的厚度成反比地变化。因此，通过以距离C成为0.5mm以上的方式配置金属布线板60，能够确保一对边界线AR、AL各自的附近处的软钎料部25的厚度。并且，能够充分地确保距离C，因而缘部BL、BR的影响较小。其结果，能够降低上表面电极的塑性应变振幅。此外，距离C的上限例如能够设为确保台地部67-1～67-6与镀层33-1～33-6接合所需要的面积的程度。
图12所示的特性能够根据软钎料部25的组成而变化。然而，如上所述，上表面电极的塑性应变振幅与软钎料部25的厚度成反比地变化。能够将软钎料部25的厚度视为绝缘膜34的缘部与槽部66-1～66-3的缘部B之间的距离C。因此，可以预想到的是，即使软钎料部25的组成发生变化，图12所示的塑性应变振幅相对于距离的特性也是大致上下移动。因而认为，通过以缘部B与绝缘膜34之间的距离C成为0.5mm以上的方式配置槽部66-1～66-3，能够降低上表面电极的塑性应变振幅。
根据本发明的实施方式的半导体装置，在从上表面电极的上表面方向观察的平面图案中，一对边界线AR、AL各自的延伸位置包含在槽部66-1～66-3的区域内。在此，如已说明那样，边界线AR、AL分别为绝缘膜34的缘部和对应的镀层33-1～33-6的端部在上表面电极的上表面上共存的三重边界线。因此，如图7所示，软钎料部25在被一对边界线AR、AL夹着的区域的正上方的厚度T1厚于在镀层33-1～33-6的中央部的正上方的厚度T2。因此，上表面电极31-1的相对于自金属布线板60承受的力而产生的应力由于槽部66-1内的软钎料部25而得到缓和。因而，能够降低上表面电极31-1的塑性应变振幅，能够延长半导体装置的寿命。
此外，在保护环35上的绝缘膜的端部与镀层33-1～33-6的端部之间的边界，也同样地在上表面电极的上表面存在边界线，在该边界线，物理性质不同的三种材料、即上表面电极的上表面的材料、保护环35上的绝缘膜的端部的材料和镀层33-1～33-6的端部的材料以线状共存。因此，在第1接合部61位于保护环35上的绝缘膜的端部与镀层33-1～33-6的端部之间的边界线上的情况下，也可以在第1接合部61的下表面设置槽部，以能够确保边界线上的软钎料部25的厚度。
(其他的实施方式)
如上述那样记载了本发明的实施方式，但不应理解为构成本公开的一部分的论述及附图是限制本发明的。根据该公开，本领域技术人员能够清楚各种各样的代替实施方式、实施例以及运用技术。
例如，也可以是，槽部66-1～66-3除了与栅极流道36-1～36-3对应地设置以外，还额外地设置。槽部66-1～66-3至少与一对边界线AR、AL的延伸位置对应地设置即可，尺寸、配置以及数量根据一对边界线AR、AL的平面图案适当地决定即可。
此外，当然也包括任意地应用了上述的实施方式和各变形例中说明的各结构的结构等、本发明在此未记载的各种各样的实施方式等。因而，根据上述说明，本发明的技术范围仅由适当的权利要求书的发明特定事项决定。
附图标记说明
10、冷却器；11、层叠基板；13、绝缘基板；14、第1电路图案层；15、第2电路图案层；16、第3电路图案层；20、壳体；21、密封树脂；22～25、软钎料部；28、下表面电极；29、半导体基板；30、半导体芯片；31-1、31-2、上表面电极；32、布线层；33-1～33-6、镀层；34、绝缘膜；35、保护环；36-1～36-3、栅极流道；39、电极焊盘；60、金属布线板；61、第1接合部；62、第1立起部；63、连接部；64、第2立起部；65、第2接合部；66-1～66-3、槽部；67-1～67-6、台地部；100、半导体装置。

Claims (7)

1.一种半导体装置，其中，
该半导体装置包括：
半导体芯片，其包含具有上表面的半导体基板、配置于所述半导体基板的上表面的上表面电极、选择性地覆盖所述上表面电极的上表面的端部的绝缘膜以及覆盖所述上表面电极的上表面的在所述绝缘膜的开口部暴露的部分的镀层；
金属布线板，其包含位于所述绝缘膜的上方和所述镀层的上方的接合部，并自所述接合部的下表面朝向所述上方设有槽部；以及
软钎料部，其填满所述槽部，将所述接合部的下表面与所述镀层接合，在俯视时，所述绝缘膜与所述镀层之间的边界线配置于所述槽部的内侧，所述软钎料部在所述边界线上的厚度厚于在所述镀层上的厚度。
2.根据权利要求1所述的半导体装置，其中，
所述金属布线板以所述槽部的缘部与所述绝缘膜之间的距离为0.5mm以上的方式配置。
3.根据权利要求1或2所述的半导体装置，其中，
该半导体装置还包括布线层，该布线层与所述上表面电极分开地配置于所述半导体芯片的上表面，
所述绝缘膜覆盖所述布线层，
所述槽部被设为在俯视时将所述布线层的位置包含在内。
4.根据权利要求3所述的半导体装置，其中，
所述布线层为控制电极的布线层，该控制电极对构成所述半导体芯片的半导体元件的主电流进行控制。
5.根据权利要求1或2所述的半导体装置，其中，
该半导体装置还包括：
绝缘基板，其用于搭载所述半导体芯片；以及
密封树脂，其至少密封所述半导体芯片、所述金属布线板、所述软钎料部以及所述绝缘基板。
6.根据权利要求3所述的半导体装置，其中，
该半导体装置还包括：
绝缘基板，其用于搭载所述半导体芯片；以及
密封树脂，其至少密封所述半导体芯片、所述金属布线板、所述软钎料部以及所述绝缘基板。
7.根据权利要求4所述的半导体装置，其中，
该半导体装置还包括：
绝缘基板，其用于搭载所述半导体芯片；以及
密封树脂，其至少密封所述半导体芯片、所述金属布线板、所述软钎料部以及所述绝缘基板。
CN201980006159.5A 2018-06-18 2019-05-08 半导体装置 Active CN111448656B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2018115327 2018-06-18
JP2018-115327 2018-06-18
PCT/JP2019/018426 WO2019244492A1 (ja) 2018-06-18 2019-05-08 半導体装置

Publications (2)

Publication Number Publication Date
CN111448656A CN111448656A (zh) 2020-07-24
CN111448656B true CN111448656B (zh) 2023-08-11

Family

ID=68983551

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980006159.5A Active CN111448656B (zh) 2018-06-18 2019-05-08 半导体装置

Country Status (5)

Country Link
US (1) US11094638B2 (zh)
JP (1) JP7014298B2 (zh)
CN (1) CN111448656B (zh)
DE (1) DE112019000184T5 (zh)
WO (1) WO2019244492A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7119399B2 (ja) * 2018-02-06 2022-08-17 株式会社デンソー 半導体装置
JP7306248B2 (ja) * 2019-12-09 2023-07-11 株式会社デンソー 半導体モジュール
US11894280B2 (en) 2020-12-09 2024-02-06 Fuji Electric Co., Ltd. Semiconductor module
JP2022178755A (ja) 2021-05-21 2022-12-02 富士電機株式会社 半導体モジュール
JP2023045874A (ja) 2021-09-22 2023-04-03 株式会社東芝 半導体装置
KR102663070B1 (ko) * 2021-09-28 2024-05-03 전남대학교산학협력단 예취부 자세 제어장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006237632A (ja) * 2006-04-21 2006-09-07 Oki Electric Ind Co Ltd 半導体装置
CN103443916A (zh) * 2011-03-09 2013-12-11 日立化成株式会社 半导体元件搭载用封装基板的制造方法、半导体元件搭载用封装基板以及半导体封装
JP2014027324A (ja) * 2013-11-08 2014-02-06 Okutekku:Kk 半導体装置及び半導体装置の製造方法
CN104170092A (zh) * 2012-05-15 2014-11-26 富士电机株式会社 半导体装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4023032B2 (ja) 1999-06-02 2007-12-19 株式会社デンソー 半導体装置の実装構造及び実装方法
JP3439417B2 (ja) * 2000-03-23 2003-08-25 Ｎｅｃエレクトロニクス株式会社 半導体パッケージ用接続導体、半導体パッケージ、及び半導体パッケージの組立方法
US6841862B2 (en) * 2000-06-30 2005-01-11 Nec Corporation Semiconductor package board using a metal base
JP2006190728A (ja) 2005-01-04 2006-07-20 Mitsubishi Electric Corp 電力用半導体装置
JP4565634B2 (ja) 2005-02-03 2010-10-20 パナソニック株式会社 半導体装置およびその製造方法
US20090108436A1 (en) * 2007-10-31 2009-04-30 Toshio Fujii Semiconductor package
JP5107839B2 (ja) * 2008-09-10 2012-12-26 ルネサスエレクトロニクス株式会社 半導体装置
JP2011066371A (ja) 2009-08-18 2011-03-31 Denso Corp 半導体装置およびその製造方法
DE102010038933A1 (de) 2009-08-18 2011-02-24 Denso Corporation, Kariya-City Halbleitervorrichtung mit Halbleiterchip und Metallplatte und Verfahren zu deren Fertigung
US8987878B2 (en) * 2010-10-29 2015-03-24 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
JP5598386B2 (ja) 2011-03-10 2014-10-01 株式会社デンソー 半導体装置
JP6097013B2 (ja) * 2012-02-29 2017-03-15 ローム株式会社 パワーモジュール半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006237632A (ja) * 2006-04-21 2006-09-07 Oki Electric Ind Co Ltd 半導体装置
CN103443916A (zh) * 2011-03-09 2013-12-11 日立化成株式会社 半导体元件搭载用封装基板的制造方法、半导体元件搭载用封装基板以及半导体封装
CN104170092A (zh) * 2012-05-15 2014-11-26 富士电机株式会社 半导体装置
JP2014027324A (ja) * 2013-11-08 2014-02-06 Okutekku:Kk 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
WO2019244492A1 (ja) 2019-12-26
DE112019000184T5 (de) 2020-09-03
JPWO2019244492A1 (ja) 2020-12-17
US20200294925A1 (en) 2020-09-17
US11094638B2 (en) 2021-08-17
CN111448656A (zh) 2020-07-24
JP7014298B2 (ja) 2022-02-01

Similar Documents

Publication Publication Date Title
CN111448656B (zh) 半导体装置
US9059334B2 (en) Power semiconductor module and method of manufacturing the same
US9905494B2 (en) Semiconductor device
US11056475B2 (en) Semiconductor module
CN108735692B (zh) 半导体装置
US11133271B2 (en) Semiconductor device
JP2022179649A (ja) 半導体装置及びその製造方法
US11195775B2 (en) Semiconductor module, semiconductor device, and manufacturing method of semiconductor module
US20230187311A1 (en) Semiconductor device and manufacturing method thereof
GB2485087A (en) Power electronic package
JP2017054842A (ja) 配線基板、半導体装置、及び半導体パッケージ
JP7322654B2 (ja) 半導体モジュール
CN110504255B (zh) 反向导通型半导体装置
JPWO2020149225A1 (ja) 半導体装置
JP2017054855A (ja) 半導体装置、及び半導体パッケージ
WO2023154646A1 (en) Semiconductor package with creepage extension structures
US11984386B2 (en) Semiconductor device
US11127714B2 (en) Printed board and semiconductor device
KR101626534B1 (ko) 반도체 패키지 및 그 제조 방법
GB2444293A (en) Double substrate power electronics package
KR20220044502A (ko) 반도체 장치
US20220406690A1 (en) Semiconductor device
US11996347B2 (en) Semiconductor device
US20230282563A1 (en) Semiconductor device
US20240321675A1 (en) Semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant