CN111433897A - 半导体整流器 - Google Patents

半导体整流器 Download PDF

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Publication number
CN111433897A
CN111433897A CN201880079373.9A CN201880079373A CN111433897A CN 111433897 A CN111433897 A CN 111433897A CN 201880079373 A CN201880079373 A CN 201880079373A CN 111433897 A CN111433897 A CN 111433897A
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China
Prior art keywords
semiconductor rectifier
electrode
transistor
diode
semiconductor
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CN201880079373.9A
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山口敦司
柏木淳一
森山洋平
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Rohm Co Ltd
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Rohm Co Ltd
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Publication of CN111433897A publication Critical patent/CN111433897A/zh
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    • H01L23/49531—Additional leads the additional leads being a wiring board
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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Abstract

通过本发明的一方案提供的半导体整流器具备晶体管以及二极管。上述晶体管具有源电极、漏电极以及门电极。上述二极管具有阳电极以及阴电极。上述阳电极与上述门电极导通，上述阴电极与上述源电极导通。

Description

半导体整流器
技术领域
本发明涉及半导体整流器。
背景技术
作为半导体整流器的一方式的肖特基势垒二极管具有Si半导体层、肖特基电极以及欧姆电极。
发明内容
通过本发明的一方案提供的半导体整流器具备晶体管以及二极管。上述晶体管具有源电极、漏电极以及门电极。上述二极管具有阳电极以及阴电极。上述阳电极与上述门电极导通，上述阴电极与上述源电极导通。
附图说明
图1是表示本发明的第一实施方式的半导体整流器的俯视图。
图2是沿图1的II-II线的剖视图。
图3是沿图1的III-III线的剖视图。
图4是表示本发明的第一实施方式的半导体整流器的电路图。
图5是表示本发明的第一实施方式的半导体整流器的电压电流特性的图表。
图6是表示本发明的第一实施方式的半导体整流器的逆回复特性的图表。
图7是表示本发明的第一实施方式的半导体整流器的第一变形例的俯视图。
图8是表示本发明的第一实施方式的半导体整流器的第二变形例的俯视图。
图9是沿图8的IX-IX线的剖视图。
图10是表示本发明的第一实施方式的半导体整流器的第三变形例的俯视图。
图11是表示本发明的第二实施方式的半导体整流器的俯视图。
图12是表示本发明的第二实施方式的半导体整流器的电路图。
图13是表示本发明的第三实施方式的半导体整流器的俯视图。
图14是表示本发明的第三实施方式的半导体整流器的电路图。
图15是表示本发明的第三实施方式的半导体整流器的第一变形例的俯视图。
图16是表示本发明的第三实施方式的半导体整流器的第一变形例的电路图。
图17是表示本发明的第一实施方式的半导体整流器的逆回复特性的图表。
图18是表示本发明的第一实施方式的半导体整流器的二极管电压的图表。
图19是表示本发明的第三实施方式的半导体整流器的逆回复特性的图表。
图20是表示本发明的第三实施方式的半导体整流器的二极管电压的图表。
图21是表示本发明的第四实施方式的半导体整流器的俯视图。
图22是沿图21的XXII-XXII线的剖视图。
图23是表示本发明的第四实施方式的半导体整流器的第一变形例的俯视图。
图24是表示本发明的第四实施方式的半导体整流器的第二变形例的俯视图。
图25是沿图24的XXV-XXV线的剖视图。
图26是表示本发明的第五实施方式的半导体整流器的俯视图。
图27是表示本发明的第五实施方式的半导体整流器的电路图。
图28是表示本发明的第六实施方式的半导体整流器的俯视图。
图29是沿图28的XXIX-XXIX线的剖视图。
图30是表示本发明的第七实施方式的半导体整流器的俯视图。
图31是沿图30的XXXI-XXXI线的剖视图。
具体实施方式
以下，参照附图，具体地说明本发明的优选实施方式。
＜第一实施方式＞
图1～图4表示本发明的第一实施方式的半导体整流器。本实施方式的半导体整流器A1具备晶体管1、二极管2、引线框3以及密封树脂6。
图1是表示半导体整流器A1的俯视图。图2是沿图1的II-II线的剖视图。图3是沿图1的III-III线的剖视图。图4是表示半导体整流器A1的电路图。
晶体管1例如是正常接通型(偏转型)晶体管，具有元件主体10、源电极11S、漏电极11D以及门电极11G。
元件主体10是包含半导体层的元件，在本实施方式中，包含GaN半导体层。在该情况下，晶体管1例如是GaN-MOSFET、GaN-HEMT等。源电极11S、漏电极11D以及门电极11G设置于元件主体10的上面，全部位于元件主体10的相同侧。
源电极11S、漏电极11D以及门电极11G由金属形成，例如通过电镀形成。从适当地进行金属丝的连接、焊接接合的观点出发，源电极11S、漏电极11D以及门电极11G的表层优选由Au构成。另外，源电极11S、漏电极11D以及门电极11G中被表层覆盖的部分例如由Cu、Ni等金属形成。
二极管2具有元件主体20、阳电极21A以及阴电极21C。二极管2例如是元件主体20含有Si半导体层的Si肖特基势垒二极管。二极管2的阈值电压优选为0.8V以下。
引线框3支撑晶体管1以及二极管2，构成向晶体管1以及二极管2的导通路径。在本实施方式中，引线框3具有岛部30、阳极端子31A以及阴极端子31C。另外，在引线框3上设置有金属层32以及绝缘层33。
引线框3的材质并未特别限定，例如使用由Cu、Ni等的金属形成的金属板材料通过进行冲压加工与折弯加工等而形成。
岛部30是支撑晶体管1以及二极管2的部分。在图示的示例中，岛部30是具有沿x方向以及y方向的四边的俯视矩形形状，但岛部30的形状并未特别限定。
另外，在本实施方式中，在岛部30上设置金属层32。金属层32是由例如从Al、Cu、Ni等中适当地选择的金属或合金形成的层。在图示的示例中，金属层32通过绝缘层33被固定于岛部30。绝缘层33由绝缘材料形成，例如能适当地采用树脂、陶瓷。另外，金属层32的z方向视角尺寸比岛部30的z方向视角尺寸小。金属层32的形成方法并未特别限定，既可以通过利用电镀等的方法形成在绝缘层33上，也可以通过绝缘层33将预先形成的金属层32接合在岛部30上。
在图示的示例中，晶体管1通过接合层19被接合在金属层32上。另外，二极管2的阴电极21C通过接合层29接合于金属层32。本示例的情况下，接合层19既可以具有绝缘性，也可以具有导电性。接合层29由导电性材料形成，例如是焊锡。由此，二极管2的阴电极21C与金属层32导通。
阳极端子31A是成为半导体整流器A1的端子且被阳极连接的端子。阳极端子31A从岛部30离开。
阴极端子31C是成为半导体整流器A1的端子且被阴极连接的端子。在本例中，阴极端子31C连接于岛部30。
在图示的示例中，半导体整流器A1具有多个阳极金属丝4A、门极金属丝4G、多个源极金属丝4S以及多个漏极金属丝4D。多个阳极金属丝4A连接于阳极端子31A和二极管2的阳电极21A。门极金属丝4G连接于二极管2的阳电极21A与晶体管1的门电极11G。多个源极金属丝4S连接于金属层32与晶体管1的源电极11S。多个漏极金属丝4D连接于晶体管1的漏电极11D与岛部30。
多个阳极金属丝4A、门极金属丝4G、多个源极金属丝4S以及多个漏极金属丝4D例如由Au、铝、Cu等金属构成。在以下，举例说明多个阳极金属丝4A、门极金属丝4G、多个源极金属丝4S以及多个漏极金属丝4D由Au形成的情况，各自的根数根据各自的材质而增减。
根据以上所述的结构，半导体整流器A1构成图4所示的电路。二极管2的阳电极21A通过门极金属丝4G与门电极11G导通。二极管2的阴极电机21C通过金属层32以及多个源极金属丝4S与源电极11S导通。
密封树脂6是用于保护晶体管1、二极管2、引线框3的一部分、多个阳极金属丝4A、门极金属丝4G、多个源极金属丝4S以及多个漏极金属丝4D的结构，例如由环氧树脂等的绝缘树脂构成。在图示的示例中，密封树脂6使岛部30的背面露出。另外，阳极端子31A以及阴极端子31C从密封树脂6的侧面向相同的方向突出。
其次，关于半导体整流器A1的作用进行说明。
根据本实施方式，通过使用晶体管1，例如与由单体二极管构成的半导体整流器相比，能够提高耐压。另外，图5表示施加于阳极端子31A以及阴极端子31C之间的电压与电流的关系，作为与半导体整流器A1的比较例，表示由Si-FRD(快速恢复二极管)单体形成的半导体整流器与由SiC-SBD(肖特基势垒二极管)单体形成的半导体整流器的电压以及电流的关系。如该图所示，预定的电流开始流经半导体整流器A1的阈值电压为比由Si-FRD单体形成的半导体整流器以及由SiC-SBD单体形成的半导体整流器的任一个的阈值电压低的值。另外，图6表示半导体整流器A1、作为比较例的由Si-FRD单体形成的半导体整流器以及由SiC-SBD单体形成的半导体整流器的逆回复特性。在从接通状态向断开状态切换时，若着眼于作为电流在逆方向中流过的时间的逆回复时间，则半导体整流器A1的逆回复时间与由SiC-SBD单体形成的半导体整流器的逆回复时间为相同的程度，明显短于由Si-FRD单体形成的半导体整流器的逆回复时间。如以上，根据半导体整流器A1，能够实现耐压的提高、阈值电压的降低以及逆回复时间的缩短。
图7～图31表示本发明的变形例以及其他实施方式。并且，在这些图中，在与上述实施方式相同或类似的元件中标注与上述实施方式相同的符号。
＜第一实施方式第一变形例＞
图7表示半导体整流器A1的第一变形例。本变形例的半导体整流器A11的引线框3的结构与上述半导体整流器A1不同。在本变形例中，在岛部30上未形成上述的金属层32以及绝缘层33。晶体管1的元件主体10通过接合层19接合于岛部30，二极管2的阴电极21C通过接合层29接合于岛部30。由此，岛部30与阴电极21C为相同电位。与之对应，阴极端子31C从岛部30离开。多个漏极金属丝4D连接于晶体管1的漏电极11D与阴极端子31C。岛部30既可以从密封树脂6中露出一部分，也可以全部被密封树脂6覆盖。
根据这样的变形例也能够实现耐压的提高、阈值电压的减低以及逆回复时间的缩短。另外，由于不需要金属层32以及绝缘层33，能够实现成本降低。
＜第一实施方式第二变形例＞
图8以及图9表示半导体整流器A1的第二变形例。本变形例的半导体整流器A12的二极管2的安装结构与上述示例不同。在本变形例中，二极管2的阴电极21C通过接合层29接合于晶体管1的源电极11S。由此，成为晶体管1与二极管2层叠的安装结构。
根据这样的变形例，也能够实现耐压的提高、阈值电压的降低以及逆回复时间的缩短。另外，二极管2的阴电极21C与晶体管1的源电极11S的导通路径仅通过接合层29构成，不含有上述示例中的源极金属丝4S。由此，能够实现到达源电极11S的导通路径的低电阻化。另外，有利于z向视角中的半导体整流器A12的小型化。
＜第一实施方式第三变形例＞
图10表示半导体整流器A1的第三变形例。本变形例的半导体整流器A13的晶体管1以及二极管2的安装结构与半导体整流器A12类似，引线框3的结构与半导体整流器A12不同。在本变形例中，一体地形成岛部30与阴极端子31C。多个漏极金属丝4D连接于漏电极11D与岛部30。
通过这样的变形例也能够实现耐压的提高、阈值电压的降低以及逆回复时间的缩短。另外，可使多个漏极金属丝4D的长度短于半导体整流器A12中的多个漏极金属丝4D的长度。由此，能够实现漏电极11D与阴极端子31C的导通路径的低电阻化。
＜第二实施方式＞
图11以及图12表示本发明的第二实施方式的半导体整流器。本实施方式的半导体整流器A12除了晶体管1以及二极管2还具备第一电阻器51。第一电阻器51介于阳极端子31A与晶体管1的门电极11G的导通路径中。并且，第一电阻器51可以与晶体管1以及二极管2的任一个一体地形成。
在图示的示例中，金属层32被分割为第一区域321、第二区域322以及第三区域323这三个区域。在第一区域321中接合晶体管1以及二极管2。在第二区域322以及第三区域323中分别接合第一电阻器51的电极。另外，在二极管2的阳电极21A与第二区域322中连接金属丝41。门极金属丝4G连接于第三区域323与门电极11G。
通过这样的实施方式也能够实现耐压的提高、阈值电压的减低以及逆回复时间的缩短。另外，通过具备第一电阻器51，只要多种地设定第一电阻器51的电阻值便能够多样地设定半导体整流器A2的动作特性。
＜第三实施方式＞
图13以及图14表示本发明的第三实施方式的半导体整流器。本实施方式的半导体整流器A3除了晶体管1以及二极管2还具备电容器55。电容器55相对于二极管2并联地连接。并且，电容器55可以与晶体管1以及二极管2的任一个一体地形成。
在图示的示例中，金属层32具有第一区域321以及第二区域322。在第一区域321中接合晶体管1、二极管2以及电容器55中的一个电极。在第二区域322中接合电容器55的另一电极。在阳极端子31A与第二区域322中连接多个金属丝41。
通过这样的实施方式也能够实现耐压的提高、阈值电压的降低以及逆回复时间的缩短。另外，如后述，通过具备电容器55而能够提高半导体整流器A3的特性。
＜第三实施方式第一变形例＞
图15以及图16表示本发明的第三实施方式的半导体整流器的第一变形例。本变形例的半导体整流器A31具备第二电阻器52。第二电阻器52相对于电容器55串联地连接，包含于电容器55与源电极11S的导通路径中。并且，第二电阻器52可以与晶体管1以及二极管2的任一个一体地形成。
在图示的示例中，金属层32具有第一区域321、第二区域322、第三区域323以及第四区域324。在第一区域321中接合晶体管1以及二极管2。在第二区域322中接合电容器55的一个电极。在第三区域323中接合电容器55的另一电极与第二电阻器52的一个电极。在第四区域324中接合第二电阻器52的另一电极。
在阳极端子31A与第二区域322中连接多个金属丝41。另外，在第四区域324与第一区域321中连接多个金属丝42。
通过这样的实施方式也能够实现耐压的提高、阈值电压的降低以及逆回复时间的缩短。
在说明半导体整流器A3以及半导体整流器A31的特性之前，关于上述半导体整流器A1的特性参照图17以及图18进行说明。在二极管2中，根据元件主体20、阳电极21A以及阴电极21C的材质、这些的连接形式而固有静电容量。表示将该二极管2的静电容量Cdi设定为300pF、840pF、1200pF的情况下的逆回复特性的图表是图17，表示二极管2的内部中的电压的图表是图18。图17以及图18是模拟实验结果。如图17所示，静电容量Cdi越小越能够缩短逆回复时间。另一方面，如图18所示，存在静电容量Cdi越小而二极管2的电压越大的这种背离现象。使用于二极管2的二极管存在耐压越低而上升电压越小的倾向。该上升电压是决定半导体整流器A1的上升电压的主要原因。因此，为了在半导体整流器A1中较低地抑制上升电压而实现高耐压，需要较低地抑制二极管2中产生的电压、且提高晶体管1的分压。为了提高晶体管1的分压，晶体管1的漏电极11D以及源电极11S之间的静电容量Cds、门电极11G以及源电极11S之间的静电容量Cgs以及二极管2的静电容量Cdi优选满足2Cds≦Cdi+Cgs的关系。
其次，参照图19以及图20，关于半导体整流器A1、半导体整流器A3以及半导体整流器A31的特性进行说明。图19表示逆回复特性，图20表示二极管2的电压。这些图中所示的图表是半导体整流器A1、半导体整流器A3以及半导体整流器A31各自的静电容量Cdi为300pF、半导体整流器A3以及半导体整流器A31的电容器55的静电容量Cxd为470pF、半导体整流器A31的第二电阻器52的电阻值R2为100Ω的条件下的模拟实验结果。
如图19所示，半导体整流器A3的逆回复时间明显比半导体整流器A1的逆回复时间长。这意味着若仅付加电容器55就会产生逆回复时间的延长。另一方面，半导体整流器A31的逆回复时间与半导体整流器A1的逆回复时间几乎相等，明显比半导体整流器A3的逆回复时间短。这意味着不仅是电容器55，通过还付加与电容器55串联连接的第二电阻器52，从而能够实现逆回复时间的缩短。
另外，如图20所示，相对于半导体整流器A1的二极管2的电压与时间一起显著地增加，半导体整流器A3的电压明显低。另外，半导体整流器A31的电压比半导体整流器A3的电压更低。这意味着通过付加电容器55而能够有效地降低二极管2的分压。从这样的观点出发，晶体管1的漏电极11D以及源电极11S之间的静电容量Cds、门电极11G以及源电极11S之间的静电容量Cgs、二极管2的静电容量Cdi以及电容器55的静电容量Cxd优选满足2Cds≦Cdi+Cgs+Cxd的关系。
＜第四实施方式＞
图21以及图22表示本发明的第四实施方式的半导体整流器。本实施方式的半导体整流器A4的晶体管1的结构与上述的实施方式不同。本实施方式的晶体管1是元件主体10包含SiC半导体层、所谓的纵型晶体管。源电极11S以及门电极11G位于元件主体10的上面，晶体管1的漏电极11D位于与源电极11S以及门电极11G相反侧的下面。漏电极11D通过接合层19接合于金属层32。接合层19由导电性材料形成，例如为焊锡。
岛部30与阴极端子31C一体地形成。多个金属丝41连接于金属层32与岛部30。由此，晶体管1的漏电极11D与阴极端子31C通过接合层19、金属层32、多个金属丝41以及岛部30导通。
通过这样的实施方式也能够实现耐压的提高、阈值电压的降低以及逆回复时间的缩短。另外，半导体整流器A4适于谋求z向视角中的小型化。
＜第四实施方式第一变形例＞
图23表示半导体整流器A4的第一变形例。在本变形例的半导体整流器A41中，金属层32以及绝缘层33的结构与上述半导体整流器A4不同。在本变形例中，金属层32以及绝缘层33在z向视角中与二极管2重合，且与晶体管1不重合。
二极管2的阴电极21C通过接合层29导通接合于金属层32。多个源极金属丝4S连接于金属层32与晶体管1的源电极11S。晶体管1的漏电极11D通过接合于19导通接合于岛部30。
通过这样的实施方式也能够实现耐压的提高、阈值电压的减低以及逆回复时间的缩短。另外，漏电极11D与阴极端子31C仅通过接合层19以及岛部30进行导通。由此，能够实现漏电极11D与阴极端子31C的导通路径的低电阻化。
＜第四实施方式第二变形例＞
图24以及图25表示半导体整流器A4的第二变形例。本变形例的半导体整流器A42为晶体管1与二极管2层叠的安装结构。即，二极管2的阴电极21C通过接合层29导通接合于晶体管1的源电极11S。另外，晶体管1的漏电极11D通过接合层19导通接合于岛部30。
通过这样的实施方式也能够实现耐压的提高、阈值电压的降低以及逆回复时间的缩短。还能够实现阴电极21C与源电极11S之间的导通路径的低电阻化、以及漏电极11D与阴极端子31C之间的导通路径的低电阻化。
＜第五实施方式＞
图26以及图27表示本发明的第五实施方式的半导体整流器。本实施方式的半导体整流器A5具备两个晶体管1以及两个二极管2。
两个晶体管1均通过接合层19接合于岛部30。各二极管2的阴电极21C通过接合层29导通接合于各晶体管1的源电极11S。
引线框3具有阴极端子31C与两个阳极端子31A。阴极端子31C兼作岛部30。两个阳极端子31A相对于阴极端子31C(岛部30)在y方向上离开。在各阳极端子31A与各二极管2的阳电极21A上分别连接多个阳极金属丝4A。在各晶体管1的漏电极11D与岛部30上分别连接多个漏极金属丝4D。即，两个晶体管1的漏电极11D彼此相互导通。
另外，在图示的示例中，晶体管1、二极管2、阳极端子31A、多个阳极金属丝4A、门极金属丝4G以及多个漏极金属丝4D的配置为夹持半导体整流器A5的x方向中心线对称的配置。
通过本实施方式也能够实现耐压的提高、阈值电压的降低以及逆回复时间的缩短。另外，可分别使用仅使用一个阳极端子31A以及阴极端子31C的方式、使用两个阳极端子31A以及阴极端子31C的方式。由此，在根据应流经电路中的电流的大小的分开使用、控制不同的系统的电流等的用途中能够使用半导体整流器A5。
＜第六实施方式＞
图28表示基于本发明的第六实施方式的半导体整流器。本实施方式的半导体整流器A6作为所谓的面安装型的半导体整流器而构成。
在本实施方式中，引线框3具有兼作岛部30的阴极端子31C与阳极端子31A。阳极端子31A以及阴极端子31C都是z向视角矩形形状，在y方向上相互离开。
晶体管1安装于岛部30(阴极端子31C)。二极管2层叠于晶体管1上而安装，阴电极21C通过接合层29导通接合于源电极11S。多个漏极金属丝4D连接于漏电极11D与阴极端子31C。多个阳极金属丝4A连接于阳极端子31A与阳电极21A。
通过本实施方式也能够实现耐压的提高、阈值电压的降低以及逆回复时间的缩短。另外，半导体整流器A6例如能够通过使用反射炉的安装方法安装于电路基板等(省略图示)。
＜第七实施方式＞
图30以及图31表示本发明的第七实施方式的半导体整流器。本实施方式的半导体整流器A7的晶体管1与二极管2通过所谓的单片结构相互一体地形成，共有相同的半导体基板15。半导体基板15例如由Si形成。在半导体基板15的两侧形成二极管2的阳电极21A以及阴电极21C。元件主体10层叠在半导体基板15上。晶体管1、二极管2以及引线框3的导通方式与半导体整流器A1相同。
通过本实施方式也能够实现耐压的提高、阈值电压的降低以及逆回复时间的缩短。另外，半导体整流器A1适于小型化。
本发明的半导体整流器并未限于上述实施方式。本发明的半导体整流器的各部分的具体结构可多种地自由设计变更。
本发明包括以下付记的实施方式。
[付记1]
一种半导体整流器，其特征在于，
具备：
具有源电极、漏电极以及门电极的晶体管；
二极管，其具有阳电极以及阴电极，上述阳电极与上述门电极导通，上述阴电极与上述源电极导通。
[付记2]
根据付记1所述的半导体整流器，其特征在于，
上述晶体管是正常导通型。
[付记3]
根据付记1或2所述的半导体整流器，其特征在于，
具备介于上述阳电极与上述门电极的导通路径中的第一电阻器。
[付记4]
根据付记3所述的半导体整流器，其特征在于，
上述第一电阻器与上述晶体管以及上述二极管的至少任一个一体地形成。
[付记5]
根据付记1至4任一项所述的半导体整流器，其特征在于，
具备相对于上述二极管并联地连接的电容器。
[付记6]
根据付记5所述的半导体整流器，其特征在于，
具备相对于上述电容器串联地连接的第二电阻器。
[付记7]
根据付记6所述的半导体整流器，其特征在于，
上述第二电阻器与上述晶体管以及上述二极管的至少任一个一体地形成。
[付记8]
根据付记1至7任一项所述的半导体整流器，其特征在于，
上述晶体管具有GaN半导体层或SiC半导体层。
[付记9]
根据付记1至8任一项所述的半导体整流器，其特征在于，
上述二极管是Si肖特基势垒二极管。
[付记10]
根据付记1至9任一项所述的半导体整流器，其特征在于，
上述晶体管的耐压比上述二极管的耐压高。
[付记11]
根据付记1至10任一项所述的半导体整流器，其特征在于，
上述晶体管与二极管共有相同的半导体基板。
[付记12]
根据付记1至11任一项所述的半导体整流器，其特征在于，
上述二极管的阈值电压为0.8V以下。
[付记13]
根据付记1至12任一项所述的半导体整流器，其特征在于，
上述晶体管的上述漏电极以及上述源电极间的静电容量Cds、上述门电极以及上述源电极间的静电容量Cgs以及上述二极管的静电容量Cdi满足以下的关系：
2Cds≦Cdi+Cgs。
[付记14]
根据付记5至7任一项所述的半导体整流器，其特征在于，
上述晶体管的上述漏电极以及上述源电极间的静电容量Cds、上述门电极以及上述源电极间的静电容量Cgs、上述二极管的静电容量Cdi以及上述电容器的静电容量Cxd满足以下关系：
2Cds≦Cdi+Cgs+Cxd。
[付记15]
根据付记1至14任一项所述的半导体整流器，其特征在于，
上述晶体管具有GaN半导体层，并且上述源电极、上述漏电极以及上述门电极位于相同侧。
[付记16]
根据付记1至14任一项所述的半导体整流器，其特征在于，
上述晶体管具有SiC半导体层，并且上述源电极以及上述门电极与上述漏电极位于相互相反侧。
[付记17]
根据付记1至16任一项所述的半导体整流器，其特征在于，
在上述晶体管的上述源电极上导通接合有上述晶体管的上述阴电极。

Claims (17)

1.一种半导体整流器，其特征在于，
具备：
具有源电极、漏电极以及门电极的晶体管；以及
二极管，其具有阳电极以及阴电极，上述阳电极与上述门电极导通，上述阴电极与上述源电极导通。
2.根据权利要求1所述的半导体整流器，其特征在于，
上述晶体管是正常导通型。
3.根据权利要求1或2所述的半导体整流器，其特征在于，
具备介于上述阳电极与上述门电极的导通路径中的第一电阻器。
4.根据权利要求3所述的半导体整流器，其特征在于，
上述第一电阻器与上述晶体管以及上述二极管的至少任一个一体地形成。
5.根据权利要求1至4任一项所述的半导体整流器，其特征在于，
具备相对于上述二极管并联地连接的电容器。
6.根据权利要求5所述的半导体整流器，其特征在于，
具备相对于上述电容器串联地连接的第二电阻器。
7.根据权利要求6所述的半导体整流器，其特征在于，
上述第二电阻器与上述晶体管以及上述二极管的至少任一个一体地形成。
8.根据权利要求1至7任一项所述的半导体整流器，其特征在于，
上述晶体管具有GaN半导体层或SiC半导体层。
9.根据权利要求1至8任一项所述的半导体整流器，其特征在于，
上述二极管是Si肖特基势垒二极管。
10.根据权利要求1至9任一项所述的半导体整流器，其特征在于，
上述晶体管的耐压比上述二极管的耐压高。
11.根据权利要求1至10任一项所述的半导体整流器，其特征在于，
上述晶体管与上述二极管共有相同的半导体基板。
12.根据权利要求1至11任一项所述的半导体整流器，其特征在于，
上述二极管的阈值电压为0.8V以下。
13.根据权利要求1至12任一项所述的半导体整流器，其特征在于，
上述晶体管的上述漏电极以及上述源电极之间的静电容量Cds、上述门电极以及上述源电极之间的静电容量Cgs以及上述二极管的静电容量Cdi满足以下关系：
2Cds≦Cdi+Cgs。
14.根据权利要求5至7任一项所述的半导体整流器，其特征在于，
上述晶体管的上述漏电极以及上述源电极之间的静电容量Cds、上述门电极以及上述源电极之间的静电容量Cgs、上述二极管的静电容量Cdi以及上述电容器的静电容量Cxd满足以下关系：
2Cds≦Cdi+Cgs+Cxd。
15.根据权利要求1至14任一项所述的半导体整流器，其特征在于，
上述晶体管具有GaN半导体层，并且上述源电极、上述漏电极以及上述门电极位于相同侧。
16.根据权利要求1至14任一项所述的半导体整流器，其特征在于，
上述晶体管具有SiC半导体层，并且上述源电极以及上述门电极与上述漏电极位于相互相反侧。
17.根据权利要求1至16任一项所述的半导体整流器，其特征在于，
在上述晶体管的上述源电极上导通接合有上述晶体管的上述阴电极。
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