CN116438648A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN116438648A
CN116438648A CN202180067519.XA CN202180067519A CN116438648A CN 116438648 A CN116438648 A CN 116438648A CN 202180067519 A CN202180067519 A CN 202180067519A CN 116438648 A CN116438648 A CN 116438648A
Authority
CN
China
Prior art keywords
semiconductor device
electrode
lead
island
control element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202180067519.XA
Other languages
English (en)
Inventor
西山雄人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of CN116438648A publication Critical patent/CN116438648A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H01L2224/06164—Random array, i.e. array with no symmetry covering only portions of the surface to be connected
    • H01L2224/06165—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48108—Connecting bonding areas at different heights the connector not being orthogonal to a side surface of the semiconductor or solid-state body, e.g. fanned-out connectors, radial layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49112—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种半导体装置，具有：开关元件、控制所述开关元件的控制元件、搭载有所述开关元件和所述控制元件的岛引线、以及多根端子引线。所述开关元件具有第一电极、第二电极以及第三电极，所述第一电极和所述第二电极相对于所述第三电极位于厚度方向的一侧。所述岛引线具有：支承所述开关元件和所述控制元件且朝向所述厚度方向的一侧的主面。所述多根端子引线分别与所述第二电极和所述控制元件中的某一个导通。所述岛引线与所述多根端子引线分离。

Description

半导体装置
技术领域
本公开涉及一种半导体装置。
背景技术
在专利文献1中，公开了具有作为开关元件的MOSFET的半导体装置。在该文献所公开的半导体装置中，是用于使开关元件动作的多根引线从树脂部向一个方向露出的结构。
现有技术文献
专利文献
专利文献1：日本特开2017-5165号公报
发明内容
发明要解决的课题
作为开关元件开关对象的电压越高，引线间的电位差越大。此时，就要求扩大相邻引线间的距离，导致了半导体装置的大型化。
本发明是鉴于上述情况而完成的，其一个课题在于提供一种能够实现高电压化和小型化的半导体装置。
用于解决课题的手段
由本公开提供的半导体装置具有：开关元件；控制元件，其控制所述开关元件；岛引线，其搭载有所述开关元件和所述控制元件；多根端子引线；以及树脂部，其覆盖所述岛引线的一部分、所述多根端子引线各自的一部分、所述开关元件和所述控制元件。所述开关元件具有第一电极、第二电极和第三电极，所述第一电极和所述第二电极相对于所述第三电极位于厚度方向的一侧。所述岛引线具有：支承所述开关元件和所述控制元件且朝向所述厚度方向的一侧的主面以及朝向所述厚度方向的另一侧的背面。所述多根端子引线分别与所述第二电极和所述控制元件中的某一个导通。所述岛引线与所述多根端子引线分离。
发明效果
根据上述结构，能够实现半导体装置的高电压化和小型化。
本公开的其他特征以及优点通过参照附图在以下进行的详细说明而变得更加明确。
附图说明
图1是表示第一实施方式的半导体装置的俯视图。
图2是表示第一实施方式的半导体装置的主要部分俯视图。
图3是表示第一实施方式的半导体装置的仰视图。
图4是表示第一实施方式的半导体装置的主视图。
图5是表示第一实施方式的半导体装置的后视图。
图6是表示第一实施方式的半导体装置的右侧视图。
图7是沿着图2的VII-VII线的剖视图。
图8是沿着图2的VIII-VIII线的剖视图。
图9是沿着图2的IX-IX线的剖视图。
图10是表示第二实施方式的半导体装置的主要部分俯视图。
图11是沿着图10的XI-XI线的剖视图。
图12是沿着图10的XII-XII线的剖视图。
具体实施方式
以下，参照附图对本公开的优选实施方式进行具体说明。
本公开中的“第一”、“第二”、“第三”等用语仅用作标签，并不意图对这些对象物附加排序。
图1～图9表示本公开的第一实施方式的半导体装置。本实施方式的半导体装置A1具有：岛引线2、多根端子引线3、开关元件4、控制元件5、绝缘层7、树脂部6以及多根导线8。半导体装置A1的用途没有特别限定，可用作发挥各种电力转换等功能的半导体装置。作为半导体装置A1的用途的一例，例如面向工业设备的AC/DC转换器。例如，将1200V左右的交流电转换为5V左右的直流电的AC/DC转换器。
图1是表示半导体装置A1的俯视图。图2是表示半导体装置A1的主要部分俯视图。图3是表示半导体装置A1的仰视图。图4是表示半导体装置A1的主视图。图5是表示半导体装置A1的后视图。图6是表示半导体装置A1的右侧视图。图7是沿着图2的VII-VII线的剖视图。图8是沿着图2的VIII-VIII线的剖视图。图9是沿着图2的IX-IX线的剖视图。在这些图中，z方向是“厚度方向”的一例，x方向是“第一方向”的一例，y方向是“第二方向”的一例。
岛引线2支承开关元件4和控制元件5。本实施方式的岛引线2具有：主面21、背面22、贯通孔23、厚壁部24、薄壁部25以及突出部26。岛引线2的材质没有特别限定，可适当使用金属等导电性材料。作为岛引线2的材质的一例，列举Cu、Fe、Ni、它们的合金。另外，可以在岛引线2的表面的适当部位适当设置Ag镀层等。此外，岛引线2可以是不具有贯通孔23、厚壁部24、薄壁部25以及突出部26中某一个的结构。岛引线2(厚壁部24)的z方向尺寸没有任何限定，例如为0.9mm～1.5mm左右，例如为1.3mm左右。
主面21是朝向z方向的一侧(图9中的上侧)的面。背面22是朝向z方向的另一侧(在图9中为下侧)的面，并从树脂部6露出。背面22在将半导体装置A1安装于电路基板等时，用作导通连接的安装部分。厚壁部24是具有主面21和背面22的各一部分的部分，在图示的例子中为矩形状。薄壁部25从厚壁部24沿与z方向成直角的方向延展。薄壁部25具有主面21的一部分，z方向的尺寸比厚壁部24薄。厚壁部24位于比背面22靠z方向一侧的位置，由树脂部6从z方向另一侧覆盖厚壁部24。
贯通孔23沿z方向贯通厚壁部24。贯通孔23的形状没有任何限定，在图示的例子中，是以x方向为长轴方向的大致椭圆形状。在贯通孔23中填充有树脂部6的一部分。突出部26从厚壁部24向y方向的一侧(图2)的图中上侧突出。突出部26从树脂部6向y方向一侧突出。在图示的例子中，突出部26的x方向尺寸比厚壁部24的x方向尺寸大。
多根端子引线3分别与后述的开关元件4的第二电极42和控制元件5中的某一个导通，并分别与岛引线2分离。多根端子引线3的根数没有任何限定。多根端子引线3的材质没有特别限定，可适当使用金属等导电性材料。作为多根端子引线3的材质的一例，列举Cu、Fe、Ni、它们的合金。另外，可以在多根端子引线3的表面的适当部位适当设置Ag镀层等。在本实施方式中，多根端子引线3包含7根端子引线31、32、33、34、35、36、37。端子引线31、32、33、34、35、36、37从x方向的一侧(图2中的图中左侧)朝向x方向的另一侧(图2中的图中右侧)依次配置。端子引线31、32、33、34、35、36、37的排列间距没有任何限定，在图示的例子中，在x方向上以大致相等的间距排列。端子引线3(端子引线31、32、33、34、35、36、37)具有键合部301、安装部302、第一连结部303以及第二连结部304，端子引线3是整体弯曲的棒状部件。
键合部(bonding)301相对于岛引线2沿y方向另一侧(图2、图7、图8中的下侧)分离，且沿z方向一侧(图7、图8中的左侧)分离。键合部301是键合导线8的部分。在图示的例子中，键合部301是x方向尺寸比第一连结部303稍大的形状。另外，优选对键合部301实施镀Ag等。在本实施方式中，如图7和图8所示，岛引线2(主面21)与键合部301的z方向的距离Dz比岛引线2(薄壁部25)与键合部301的y方向的距离Dy大。在图示的例子中，键合部301位于比开关元件4和控制元件5靠z方向一侧的位置。键合部301的z方向尺寸没有任何限定，例如为0.5mm左右。距离Dy例如为0.5mm左右，比岛引线2(厚壁部24)的厚度小。距离Dz例如为1.3mm左右。
安装部302从树脂部6向y方向另一侧露出。安装部302的z方向上的位置是沿着y方向观察时与岛引线2重叠的位置。在图示的例子中，安装部302的z方向的另一侧的面设定为在z方向上与岛引线2的主面21大致相同。安装部302在将半导体装置A1安装于电路基板等时，与岛引线2的背面22一起用作导通连接的安装部分。这样，半导体装置A1构成为面安装型的半导体装置。
第一连结部303与键合部301相连，沿y方向的另一侧延伸。第一连结部303具有被树脂部6覆盖的部分和从树脂部6突出的部分。第二连结部304是将第一连结部303与安装部302连结的部分。第二连结部304是沿着z方向延伸、或者在相对于z方向稍微倾斜的方向上延伸的形状。
开关元件4是对输入电流进行开关的元件，没有任何限定。在本实施方式中，开关元件4是具有以SiC为主材料的半导体部的SiC-MOSFET。SiC-MOSFET例如与具有以Si为主材料的半导体层的Si-MOSFET相比，具有低损耗这样的优点。在本实施方式中，开关元件4具有：半导体部40、第一电极41、第二电极42以及第三电极43。若列举开关元件4的大小的一例，则x方向尺寸为0.8mm～1.2mm左右，y方向尺寸为1.0mm～1.5mm左右。
开关元件4搭载在岛引线2的厚壁部24的主面21。在图示的例子中，开关元件4搭载于厚壁部24的y方向另一侧且x方向一侧。另外，开关元件4相对于贯通孔23位于y方向另一侧。半导体部40是以SiC为主材料的半导体层。第一电极41设置在半导体部40的z方向一侧。第一电极41通过导线8与控制元件5连接。第二电极42设置在半导体部40的z方向一侧。第二电极42配置成相对于第一电极41沿y方向的另一侧分离。第二电极42通过多根导线8与端子引线31以及端子引线32连接。第三电极43设置在半导体部40的z方向另一侧。在本实施方式中，第三电极43通过导电性接合层49与岛引线2的厚壁部24的主面21导通接合。导电性接合层49例如是焊料、Ag膏。
控制元件5是用于控制开关元件4的开关动作的集成电路元件。控制元件5具有元件主体50和多个电极焊盘51。元件主体50是形成有集成电路的部分，在z方向观察时为矩形状。多个电极焊盘51沿着元件主体50的四边设置。若列举控制元件5的大小的一例，则x方向尺寸为1.2mm～1.6mm左右，y方向尺寸为0.8mm～1.2mm左右。
控制元件5支承于岛引线2的厚壁部24的主面21。控制元件5配置成相对于开关元件4沿x方向的另一侧分离。开关元件4和控制元件5配置于沿着x方向观察时相互重叠的位置。控制元件5的搭载方法没有任何限定。
在本实施方式中，绝缘层7设置在控制元件5与岛引线2的主面21之间。绝缘层7是能够使与开关元件4的第三电极43为相同电位的裸片键合部11与控制元件5适当地绝缘的层。绝缘层7的具体结构没有任何限定，在本实施方式中，如图8和图9所示，其具有固体层71、接合层72和接合层73。
固体层71由发挥适当的绝缘性的材质构成，例如由以氧化铝为代表的陶瓷、Si等绝缘材料构成。接合层72是将控制元件5与固体层71接合的层。接合层73是将固体层71与岛引线2的主面21接合的层。接合层72和接合层73没有特别限定，在本实施方式中，使用绝缘性的接合材料。如图2所示，在本实施方式中，沿着z方向观察时，绝缘层7比控制元件5大，从控制元件5向x方向两侧及y方向两侧延展。
树脂部6覆盖岛引线2的一部分、多根端子引线3各自的一部分、开关元件4、控制元件5、绝缘层7以及多根导线8。树脂部6的材质没有特别限定，例如由混入有填料的黑色的环氧树脂构成。树脂部6的z方向尺寸没有任何限定，例如为4.0mm～5.0mm左右，例如为4.4mm左右。
如图1～图9所示，树脂部6具有：树脂主面61、树脂背面62、树脂端面63、树脂端面64以及一对树脂侧面65。
树脂主面61是朝向z方向一侧的面。在本实施方式中，树脂主面61是相对于z方向成直角的面，在z方向上观察时为大致矩形状。树脂背面62是朝向z方向一侧的面。在本实施方式中，树脂主面61是相对于z方向成直角的面。在本实施方式中，岛引线2的背面22从树脂背面62露出。
树脂端面63是位于y方向的另一侧的面。在图示的例子中，树脂端面63具有相对于z方向稍微倾斜的多个区域。在本实施方式中，多根端子引线3(第一连结部303)从树脂端面63突出。树脂端面64是位于y方向的一侧的面。在图示的例子中，树脂端面64具有相对于z方向稍微倾斜的多个区域和沿着z方向的区域。在本实施方式中，岛引线2的突出部26从树脂端面64突出。
一对树脂侧面65是位于x方向两侧的面。在图示的例子中，树脂侧面65是相对于z方向稍微倾斜的平面。
本实施方式的树脂部6的一部分填充于贯通孔23。另外，树脂背面62与岛引线2的背面22大致齐平。树脂部6从z方向另一侧覆盖岛引线2的薄壁部25。
多根导线8用于使多根端子引线3、开关元件4以及控制元件5彼此适当导通。导线8的材质没有任何限定，是由Au、Al、Cu等构成的金属线状部件。在本实施方式中，如图2所示，多根导线8包含第一导线81、82、第二导线83、84、85、86、87、88以及第三导线89。本例的第一导线81、82、第二导线83、84、85、86、87、88及第三导线89是由毛细管(capillary)形成的类型的导线。
第一导线81与开关元件4的第二电极42和端子引线31的键合部301连接。在本实施方式中，设置2根第一导线81。此外，第一导线81的根数没有任何限定，可以是1根，也可以是3根以上。成为开关对象的电流流过第二电极42，因此，具有多根第一导线81的结构有利于低电阻化。如图7所示，第一导线81的与第二电极42连接的部分为第一键合部(firstbonding)，与键合部301连接的部分为第二键合部(second bonding)。
第一导线82与开关元件4的第二电极42和端子引线32的键合部301连接。第一导线82的与第二电极42连接的部分为第一键合部，与键合部301连接的部分为第二键合部。
第二导线83与控制元件5的电极焊盘51和端子引线32的键合部301连接。第二导线83的与电极焊盘51连接的部分为第一键合部，与键合部301连接的部分为第二键合部。
第二导线84与控制元件5的电极焊盘51和端子引线33的键合部301连接。第二导线84的与电极焊盘51连接的部分为第一键合部，与键合部301连接的部分为第二键合部。
第二导线85与控制元件5的电极焊盘51和端子引线34的键合部301连接。第二导线85的与电极焊盘51连接的部分为第一键合部，与键合部301连接的部分为第二键合部。
第二导线86与控制元件5的电极焊盘51和端子引线35的键合部301连接。第二导线86的与电极焊盘51连接的部分为第一键合部，与键合部301连接的部分为第二键合部。
第二导线87与控制元件5的电极焊盘51和端子引线36的键合部301连接。第二导线87的与电极焊盘51连接的部分为第一键合部，与键合部301连接的部分为第二键合部。
第二导线88与控制元件5的电极焊盘51和端子引线37的键合部301连接。第二导线88的与电极焊盘51连接的部分为第一键合部，与键合部301连接的部分为第二键合部。
第三导线89与开关元件4的第一电极41和控制元件5的电极焊盘51连接。第三导线89的与电极焊盘51连接的部分为第一键合部，与第一电极41连接的部分为第二键合部。
接着，对半导体装置A1的作用效果进行说明。
根据本实施方式，开关元件4的第三电极43与岛引线2导通接合。岛引线2与多根端子引线31彼此分离。因此，在对岛引线2施加了1700V左右的高电压时，能够使岛引线2与多根端子引线3更可靠地绝缘。另外，将多根端子引线3之间与岛引线2的电位差作为基准时，彼此的电位差显著小。因此，不需要过度增大多根端子引线3的排列间距(图2中的x方向的排列间距)。因此，能够实现半导体装置A1的高电压化和小型化。
控制元件5隔着绝缘层7而与岛引线2绝缘。由此，不论对岛引线2的电压的施加状态如何，都能够使控制元件5更适当地进行动作。
岛引线2的背面22从树脂部6的树脂背面62露出。如果是这样的结构，则例如与端子引线3的安装部302的面积相比，可以使背面22的面积为大面积。这有利于低电阻化和对来自开关元件4的热进行散热。
开关元件4和控制元件5沿x方向分离地排列配置。由此，能够避免多根端子引线3的键合部301与开关元件4和控制元件5中某一个的距离变得极长。
如图7及图8所示，键合部301与岛引线2的主面21的x方向的距离Dz比键合部301与岛引线2(薄壁部25)的距离大。由此，不会过于扩大岛引线2与键合部301的距离，而使键合部301沿y方向与岛引线2过度地分离。由此，能够缩小半导体装置A1的y方向尺寸。
背面22与多根端子引线3的安装部302在z方向上位于大致相同的位置，由此，能够使用这些部位对半导体装置A1进行面安装。
岛引线2具有贯通孔23、薄壁部25，由此，能够抑制岛引线2从树脂部6脱落。
图10～图12表示本公开的其他实施方式。此外，在这些图中，对与上述实施方式相同或类似的要素标注与上述实施方式相同的符号。
图10～图12是表示第二实施方式的半导体装置的仰视图。本实施方式的半导体装置A2的绝缘层7的结构与上述的实施方式不同。
在本实施方式中，绝缘层7仅由接合层72构成。接合层72与上述的实施方式同样地由绝缘性的接合材料构成。本实施方式的绝缘层7的厚度(z方向尺寸)没有任何限定，优选比半导体装置A1的绝缘层7厚。
根据本实施方式，也能够实现半导体装置A2的高电压化和小型化。另外，不是绝缘层7从控制元件5大幅延展的结构。由此，适合缩小A2的沿着z方向观察的大小。
本公开的半导体装置不限于上述的实施方式。本公开的半导体装置的各个部分的具体结构可以自由地进行各种设计变更。以下的附记所记载的结构包含于本公开的实施方式。
附记1.
一种半导体装置，具有：
开关元件；
控制元件，其控制所述开关元件；
岛引线，其搭载有所述开关元件和所述控制元件；
多根端子引线；以及
树脂部，其覆盖所述岛引线的一部分、所述多根端子引线各自的一部分、所述开关元件和所述控制元件，
所述开关元件具有第一电极、第二电极及第三电极，所述第一电极和所述第二电极相对于所述第三电极位于厚度方向的一侧，
所述岛引线具有：支承所述开关元件和所述控制元件且朝向所述厚度方向的一侧的主面以及朝向所述厚度方向的另一侧的背面，
所述多根端子引线分别与所述第二电极和所述控制元件中的某一个导通，
所述岛引线与所述多根端子引线分离。
附记2.
根据附记1所述的半导体装置，其中，
所述第三电极与所述岛引线的所述主面导通接合。
附记3.
根据附记2所述的半导体装置，其中，
所述半导体装置还具有：绝缘层，其介于所述控制元件与所述岛引线的所述主面之间。
附记4.
根据附记3所述的半导体装置，其中，
所述岛引线的所述背面从所述树脂部露出。
附记5.
根据附记4所述的半导体装置，其中，
所述开关元件和所述控制元件配置成沿与所述厚度方向成直角的第一方向彼此分离。
附记6.
根据附记5所述的半导体装置，其中，
所述多根端子引线从所述树脂部向第二方向突出，该第二方向与所述厚度方向以及所述第一方向成直角。
附记7.
根据附记6所述的半导体装置，其中，
在沿着所述厚度方向观察时，所述岛引线与所述多根端子引线沿所述第二方向彼此分离。
附记8.
根据附记7所述的半导体装置，其中，
所述端子引线具有：键合部，其被所述树脂部覆盖且相对于所述岛引线位于所述厚度方向的一侧。
附记9.
根据附记8所述的半导体装置，其中，
所述键合部与所述岛引线在所述厚度方向上的距离比所述键合部与所述岛引线在所述第二方向上的距离大。
附记10.
根据附记8或9所述的半导体装置，其中，
所述端子引线具有：安装部，其从所述树脂部露出且在所述厚度方向上的位置为沿着所述第二方向观察时与所述岛引线重叠的位置。
附记11.
根据附记10所述的半导体装置，其中，
所述多根端子引线配置成在所述第一方向上等间距。
附记12.
根据附记8～11中任一项所述的半导体装置，其中，
所述半导体装置还具有：第一导线，其与所述第二电极和所述多根端子引线的所述键合部连接。
附记13.
根据附记12所述的半导体装置，其中，
所述半导体装置还具有：第二导线，其与所述控制元件和所述多根端子引线的所述键合部连接。
附记14.
根据附记13所述的半导体装置，其中，
所述半导体装置还具有：第三导线，其与所述第一电极和所述控制元件连接。
附记15.
根据附记1～14中任一项所述的半导体装置，其中，
所述岛引线具有：贯通孔，其沿所述厚度方向贯通，
在所述贯通孔中填充有所述树脂部的一部分。
附记16.
根据附记1～15中任一项所述的半导体装置，其中，
所述开关元件具有以SiC为主成分的半导体部。
附记17.
根据附记1～16中任一项所述的半导体装置，其中，
所述第一电极是栅极电极，所述第二电极是源极电极，所述第三电极是漏极电极。
符号说明
A1、A2：半导体装置 2：岛引线
3：端子引线 4：开关元件
5：控制元件 6：树脂部
7：绝缘层 8：导线
11：裸片键合部 21：主面
22：背面 23：贯通孔
24：厚壁部 25：薄壁部
26：突出部
31、32、33、34、35、36、37：端子引线
40：半导体部 41：第一电极
42：第二电极 43：第三电极
49：导电性接合层 50：元件主体
51：电极焊盘 61：树脂主面
62：树脂背面 63：树脂端面
64：树脂端面 65：树脂侧面
71：固体层 72、73：接合层
81、82：第一导线
83、84、85、86、87、88：第二导线
89：第三导线 301：键合部
302：安装部 303：第一连结部
304：第二连结部 Dy、Dz：距离。

Claims (17)

1.一种半导体装置，其特征在于，具有：
开关元件；
控制元件，其控制所述开关元件；
岛引线，其搭载有所述开关元件和所述控制元件；
多根端子引线；以及
树脂部，其覆盖所述岛引线的一部分、所述多根端子引线各自的一部分、所述开关元件和所述控制元件，
所述开关元件具有第一电极、第二电极和第三电极，所述第一电极和所述第二电极相对于所述第三电极位于厚度方向的一侧，
所述岛引线具有：支承所述开关元件和所述控制元件且朝向所述厚度方向的一侧的主面以及朝向所述厚度方向的另一侧的背面，
所述多根端子引线分别与所述第二电极和所述控制元件中的某一个导通，
所述岛引线与所述多根端子引线分离。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第三电极与所述岛引线的所述主面导通接合。
3.根据权利要求2所述的半导体装置，其特征在于，
所述半导体装置还具有：绝缘层，其介于所述控制元件与所述岛引线的所述主面之间。
4.根据权利要求3所述的半导体装置，其特征在于，
所述岛引线的所述背面从所述树脂部露出。
5.根据权利要求4所述的半导体装置，其特征在于，
所述开关元件和所述控制元件配置成沿与所述厚度方向成直角的第一方向彼此分离。
6.根据权利要求5所述的半导体装置，其特征在于，
所述多根端子引线从所述树脂部向第二方向突出，该第二方向与所述厚度方向以及所述第一方向成直角。
7.根据权利要求6所述的半导体装置，其特征在于，
沿着所述厚度方向观察时，所述岛引线与所述多根端子引线沿所述第二方向彼此分离。
8.根据权利要求7所述的半导体装置，其特征在于，
所述端子引线具有：键合部，其被所述树脂部覆盖且相对于所述岛引线位于所述厚度方向的一侧。
9.根据权利要求8所述的半导体装置，其特征在于，
所述键合部与所述岛引线在所述厚度方向上的距离比所述键合部与所述岛引线在所述第二方向上的距离大。
10.根据权利要求8或9所述的半导体装置，其特征在于，
所述端子引线具有：安装部，其从所述树脂部露出且在所述厚度方向上的位置为沿着所述第二方向观察时与所述岛引线重叠的位置。
11.根据权利要求10所述的半导体装置，其特征在于，
所述多根端子引线配置成在所述第一方向上等间距。
12.根据权利要求8～11中任一项所述的半导体装置，其特征在于，
所述半导体装置还具有：第一导线，其与所述第二电极和所述多根端子引线的所述键合部连接。
13.根据权利要求12所述的半导体装置，其特征在于，
所述半导体装置还具有：第二导线，其与所述控制元件和所述多根端子引线的所述键合部连接。
14.根据权利要求13所述的半导体装置，其特征在于，
所述半导体装置还具有：第三导线，其与所述第一电极和所述控制元件连接。
15.根据权利要求1～14中任一项所述的半导体装置，其特征在于，
所述岛引线具有：贯通孔，其沿所述厚度方向贯通，
在所述贯通孔中填充有所述树脂部的一部分。
16.根据权利要求1～15中任一项所述的半导体装置，其特征在于，
所述开关元件具有以SiC为主成分的半导体部。
17.根据权利要求1～16中任一项所述的半导体装置，其特征在于，
所述第一电极是栅极电极，所述第二电极是源极电极，所述第三电极是漏极电极。
CN202180067519.XA 2020-10-02 2021-09-03 半导体装置 Pending CN116438648A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020167588 2020-10-02
JP2020-167588 2020-10-02
PCT/JP2021/032447 WO2022070768A1 (ja) 2020-10-02 2021-09-03 半導体装置

Publications (1)

Publication Number Publication Date
CN116438648A true CN116438648A (zh) 2023-07-14

Family

ID=80950213

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202180067519.XA Pending CN116438648A (zh) 2020-10-02 2021-09-03 半导体装置

Country Status (5)

Country Link
US (1) US20230369185A1 (zh)
JP (1) JPWO2022070768A1 (zh)
CN (1) CN116438648A (zh)
DE (1) DE112021004644T5 (zh)
WO (1) WO2022070768A1 (zh)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2704342B2 (ja) * 1992-04-03 1998-01-26 シャープ株式会社 半導体装置およびその製造方法
JP2563171Y2 (ja) * 1992-06-26 1998-02-18 シャープ株式会社 樹脂封止型半導体装置
JP3989417B2 (ja) * 2003-07-28 2007-10-10 シャープ株式会社 電源用デバイス
JP2008171876A (ja) * 2007-01-09 2008-07-24 Sharp Corp 半導体装置
JP6520437B2 (ja) 2015-06-12 2019-05-29 富士電機株式会社 半導体装置

Also Published As

Publication number Publication date
US20230369185A1 (en) 2023-11-16
DE112021004644T5 (de) 2023-06-29
JPWO2022070768A1 (zh) 2022-04-07
WO2022070768A1 (ja) 2022-04-07

Similar Documents

Publication Publication Date Title
US9659912B2 (en) Low-inductance circuit arrangement comprising load current collecting conductor track
US7615854B2 (en) Semiconductor package that includes stacked semiconductor die
EP2889902B1 (en) Electric power semiconductor device
JP7137558B2 (ja) 半導体装置
US20230207440A1 (en) Semiconductor device
US11942449B2 (en) Semiconductor arrangement and method for producing the same
US20200388605A1 (en) Semiconductor Substrate and Semiconductor Arrangement
US20230197584A1 (en) Mounting structure for semiconductor module
CN116438648A (zh) 半导体装置
US11538725B2 (en) Semiconductor module arrangement
US20230110154A1 (en) Semiconductor device
CN111584422B (zh) 半导体装置及其制造方法
EP3736854A1 (en) Power semiconductor module arrangement
US10957636B2 (en) Semiconductor device
US9362221B2 (en) Surface mountable power components
US20230170286A1 (en) Terminal Element or Bus Bar, and Power Semiconductor Module Arrangement Comprising a Terminal Element or Bus Bar
US20230411274A1 (en) Semiconductor device
EP4113605A1 (en) Power semiconductor module arrangement
US20240030080A1 (en) Semiconductor device
US20220102264A1 (en) Semiconductor device
CN112805829B (zh) 半导体装置
CN109994445B (zh) 半导体元件和半导体装置
CN116762168A (zh) 半导体器件
CN116325151A (zh) 电接触装置、功率半导体模块、用于制造电接触装置的方法和用于制造功率半导体模块的方法
CN115315763A (zh) 检流电阻器以及电流检测装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination