CN111430239A - GaN device based on surface treatment and oxidation process and preparation method thereof - Google Patents

GaN device based on surface treatment and oxidation process and preparation method thereof Download PDF

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CN111430239A
CN111430239A CN202010539755.4A CN202010539755A CN111430239A CN 111430239 A CN111430239 A CN 111430239A CN 202010539755 A CN202010539755 A CN 202010539755A CN 111430239 A CN111430239 A CN 111430239A
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layer
epitaxial structure
forming
ohmic electrode
gan
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CN111430239B (en
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马飞
冯光建
蔡永清
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Zhejiang Jimaike Microelectronics Co Ltd
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Zhejiang Jimaike Microelectronics Co Ltd
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02241—III-V semiconductor
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

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Abstract

The invention provides a GaN device based on surface treatment and oxidation process and a preparation method thereof, wherein the preparation method comprises the steps of providing a semiconductor substrate, forming an epitaxial structure, forming a device isolation structure, forming a source electrode ohmic electrode and a drain electrode ohmic electrode, and forming a natural oxide layer and forming a gate oxide contact layer by in-situ deposition.

Description

GaN device based on surface treatment and oxidation process and preparation method thereof
Technical Field
The invention belongs to the field of semiconductor power electronic devices, and particularly relates to a GaN device based on surface treatment and oxidation processes and a preparation method thereof.
Background
Nowadays, human production and life are not free from electric power, and with the improvement of energy-saving consciousness of people, power semiconductor devices with high conversion efficiency become hot spots of domestic and foreign research. The power semiconductor device is widely applied to household appliances, power converters, industrial control and the like, and different power semiconductor devices are adopted under different rated voltages and currents. High Electron Mobility Transistors (HEMTs) are hot spots developed at home and abroad, have made breakthroughs in many fields, and have a wide application prospect particularly in the aspects of High temperature, High power, High frequency and the like.
GaN transistors are used for their excellent material properties, such as: wide band gap, large critical electric field, high electron mobility, high saturation velocity and high density two-dimensional electron gas (2 DEG) caused by spontaneous and piezoelectric polarization effects, and has good application in the fields of power switches and radio frequency. However, device (e.g., AlGaN/GaN heterojunction field effect transistors, HFETs) power performance is limited by the schottky gate structure, which suffers from high gate structure leakage, drain electrode current breakdown, and poor long-term stability. Replacing the schottky gate structure with a Metal Oxide Semiconductor (MOS) structure may inhibit gate structure leakage. Surface passivation techniques using various dielectrics improve current collapse by reducing the density of surface states. There are still several challenges to be solved. In particular, dielectric materials are optimized, such as to reduce leakage current, eliminate current collapse, reduce capacitance-voltage (CV) hysteresis, and the like.
Therefore, how to provide a GaN device based on surface treatment and oxidation process and a method for manufacturing the same are necessary to solve the above problems in the prior art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a GaN device based on surface treatment and oxidation process and a method for manufacturing the same, which are used to solve the problems of the prior art, such as gate dielectric material performance to be optimized and leakage current.
To achieve the above and other related objects, the present invention provides a method for fabricating a GaN device based on surface treatment, the method comprising:
providing a semiconductor substrate;
forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a GaN channel layer;
forming a plurality of device isolation structures which are arranged at intervals in the epitaxial structure, wherein the bottom of each device isolation structure is lower than two-dimensional electron gas formed in the GaN channel layer, and a device area is defined between every two adjacent device isolation structures;
forming a source ohmic electrode and a drain ohmic electrode on the epitaxial structure of the device region;
forming a natural oxide layer on the epitaxial structure around the source electrode ohmic electrode and the drain electrode ohmic electrode of the device region;
and carrying out in-situ deposition on the natural oxide layer to form a gate oxide dielectric layer.
Optionally, the method further includes, after forming the gate oxide dielectric layer: and forming a grid metal electrode on the grid oxide dielectric layer between the source ohmic electrode and the drain ohmic electrode.
Optionally, the epitaxial structure further includes a transition layer, a buffer layer, and a barrier layer, wherein the transition layer, the buffer layer, the GaN channel layer, and the barrier layer are sequentially disposed from bottom to top.
Optionally, the method for forming the device isolation structure includes: forming a plurality of isolation grooves arranged at intervals in the epitaxial structure, wherein the isolation grooves form the device isolation structure, or forming a plurality of ion implantation areas arranged at intervals in the epitaxial structure through ion implantation, wherein the ion implantation areas form the device isolation structure, or firstly performing ion implantation to form an ion implantation area and then etching the ion implantation area to form an etching groove and a residual implantation area, and the etching groove and the residual implantation area form the device isolation structure.
Optionally, when the isolation trench is formed, etching the epitaxial structure by using a chlorine-based atmosphere to form the isolation trench; when the ion implantation region is formed, the ion implantation is performed using N ions or He ions.
Optionally, the method for forming the native oxide layer includes: and placing the structure obtained in the last step in a process chamber, introducing ozone into the process chamber, and forming the natural oxidation layer based on the surface treatment of the ozone.
Optionally, before placing the structure obtained in the previous step into the process chamber, the method further comprises: firstly, a first cleaning agent is adopted to carry out ultrasonic cleaning on the upper surface of the epitaxial structure, and then a second cleaning agent is adopted to carry out surface treatment on the structure subjected to ultrasonic cleaning, wherein the first cleaning agent comprises acetone, methanol and isopropanol, and the second cleaning agent comprises hydrochloric acid and hydrofluoric acid.
Optionally, the gate oxide dielectric layer is formed in an atomic layer deposition chamber based on an atomic layer deposition process, and the native oxide layer is formed based on the atomic layer deposition chamber.
Optionally, the oxygen source forming the gate oxide dielectric layer comprises ozone.
The invention also provides a GaN device based on the surface treatment and oxidation process, which is preferably prepared by the preparation method of the GaN device based on the surface treatment and oxidation process, of the invention, and of course, can also be prepared by other preparation methods, wherein the GaN device comprises:
a semiconductor substrate;
an epitaxial structure formed on the semiconductor substrate, the epitaxial structure including a GaN channel layer;
the device isolation structures are arranged at intervals and formed in the epitaxial structure, the bottoms of the device isolation structures are lower than two-dimensional electron gas formed in the GaN channel layer, and a device area is defined between every two adjacent device isolation structures;
a source ohmic electrode and a drain ohmic electrode formed on the epitaxial structure of the device region;
the natural oxidation layer is formed on the epitaxial structure around the source electrode ohmic electrode and the drain electrode ohmic electrode of the device area;
and the gate oxide dielectric layer is formed on the natural oxide layer through in-situ deposition.
Optionally, the GaN device further includes a gate metal electrode formed on the gate oxide dielectric layer between the source ohmic electrode and the drain ohmic electrode.
Optionally, the epitaxial structure further includes a transition layer, a buffer layer, and a barrier layer, wherein the transition layer, the buffer layer, the GaN channel layer, and the barrier layer are sequentially disposed from bottom to top.
Optionally, the natural oxide layer and the gate oxide dielectric layer are formed based on the same atomic layer deposition chamber.
Optionally, the oxygen source forming the gate oxide dielectric layer comprises ozone; the native oxide layer is formed based on ozone treatment.
As described above, according to the GaN device based on the surface treatment and oxidation process and the preparation method thereof, the natural oxide layer is formed on the surface of the epitaxial structure and can be used as a passivation layer, meanwhile, the surface of the epitaxial structure is cleaned, and the residual photoresist layer, unnecessary carbon and organic matters in the process can be effectively removed.
Drawings
FIG. 1 is a flow chart of the fabrication process of GaN device based on surface treatment and oxidation process.
FIG. 2 is a schematic structural diagram of a semiconductor substrate provided in the fabrication of a GaN device according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram illustrating the formation of an epitaxial structure in the fabrication of a GaN device in an embodiment of the present invention.
FIG. 4 is a schematic diagram of a device isolation structure formed in the fabrication of a GaN device according to an embodiment of the invention.
Fig. 5 is a schematic diagram illustrating the formation of an ion implantation region during the formation of another device isolation structure in the fabrication of a GaN device according to an embodiment of the present invention.
Fig. 6 is a schematic diagram showing the formation of an etched trench by etching after the formation of the ion implantation region.
Fig. 7 is a schematic diagram illustrating the formation of source and drain ohmic electrodes in the fabrication of a GaN device according to an embodiment of the present invention.
FIG. 8 is a schematic structural diagram illustrating the formation of a native oxide layer in the fabrication of a GaN device according to an embodiment of the invention.
FIG. 9 is a schematic structural diagram illustrating the formation of a gate oxide dielectric layer in the fabrication of a GaN device according to an embodiment of the invention.
Fig. 10 is a schematic structural diagram illustrating the formation of a gate metal electrode in the fabrication of a GaN device in accordance with an embodiment of the present invention.
Description of the element reference numerals
The manufacturing method comprises the following steps of 100 semiconductor structures, 101 epitaxial structures, 101a device isolation structures, 101b ion injection regions, 101c etched grooves, 101d residual injection regions, 102 transition layers, 103 buffer layers, 104GaN channel layers, 104a two-dimensional electron gas, 105 barrier layers, 106 source ohmic electrodes, 107 drain ohmic electrodes, 108 natural oxide layers, 109 gate oxide dielectric layers, 110 gate metal electrodes and S1-S6.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, number and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for manufacturing a GaN device based on surface treatment, the method comprising the steps of:
s1: providing a semiconductor substrate;
s2: forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a GaN channel layer;
s3: forming a plurality of device isolation structures which are arranged at intervals in the epitaxial structure, wherein the bottom of each device isolation structure is lower than two-dimensional electron gas formed in the GaN channel layer, and a device area is defined between every two adjacent device isolation structures;
s4: forming a source ohmic electrode and a drain ohmic electrode on the epitaxial structure of the device region;
s5: forming a natural oxide layer on the epitaxial structure around the source electrode ohmic electrode and the drain electrode ohmic electrode of the device region;
s6: and carrying out in-situ deposition on the natural oxide layer to form a gate oxide dielectric layer.
The method for manufacturing the semiconductor device structure of the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the manufacturing sequence of the semiconductor device structure of the present invention, and the skilled person can change the sequence according to the actual process steps, and fig. 1 shows only the manufacturing steps of the semiconductor device structure in one example.
As shown in S1 in fig. 1 and fig. 2, step S1 is performed to provide the semiconductor substrate 100. The semiconductor substrate 100 may include a sapphire substrate, a SiC substrate, a Si substrate, a GaN substrate, and the like as substrates, in other embodiments, the semiconductor substrate 100 may also be a substrate including other element semiconductors or compound semiconductors, and in addition, the semiconductor substrate 100 may also be a stacked structure.
As shown in S2 of fig. 1 and fig. 3, step S2 is performed to form an epitaxial structure 101 on the semiconductor substrate 100, where the epitaxial structure 101 includes a GaN channel layer 104. In an example, the epitaxial structure 101 further comprises a transition layer 102, a buffer layer 103, and a barrier layer 105, wherein the transition layer 102 is formed on the semiconductor substrate 100, the transition layer 102 including, but not limited to, an AlGaN layer; the buffer layer 103 is formed on the transition layer 102, and the buffer layer 103 includes but is not limited to a GaN layer, which may be a high-resistance GaN layer; the GaN channel layer 104 is formed on the buffer layer 103; the barrier layer 105 is formed on the GaN channel layer 104. In this example, the epitaxial structure 101 sequentially includes AlGaN/GaN/AlGaN material layers corresponding to the above layers from bottom to top. The invention has no requirement on the epitaxial wafer, and can also be the GaN device epitaxial wafer directly purchased, and the surface treatment and the oxidation process provided by the invention can be carried out.
As shown in S3 of fig. 1 and fig. 4, step S3 is performed to form a plurality of device isolation structures 101a spaced apart from each other in the epitaxial structure 101, where the bottoms of the device isolation structures 101a are lower than the two-dimensional electron gas (2 DEG) 104a formed in the GaN channel layer 104, so as to achieve electrical isolation, and a device region is defined between adjacent device isolation structures 101 a. In one example, the depth of the device isolation structure 101a is between 200 nm and 500nm, such as 250nm and 300 nm. After the material layers of the GaN device are formed, a person skilled in the art can know the specific position of the two-dimensional electron gas in the GaN channel layer, and generally thinks approximately that the two-dimensional electron gas is formed on the surface (near surface) of the GaN channel. In one example, the position of the two-dimensional electron gas is shown with reference to FIG. 4.
As an example, the device electrical isolation is performed by using ion implantation or chlorine-based ICP or RIE etching, wherein the method for forming the device isolation structure may be to form a plurality of isolation trenches arranged at intervals in the epitaxial structure, the isolation trenches constitute the device isolation structure 101a, as shown in fig. 4, and optionally, ICP etching is used to etch a part of the epitaxial structure 101 by using a chlorine-based atmosphere to form isolation trenches, and the chlorine-based atmosphere may be SiCl4/Cl2, such as etching a barrier layer (AlGaN)/GaN channel layer by using a chlorine-based atmosphere to form device mesa isolation. In addition, the method for forming the device isolation structure may further include forming a plurality of ion implantation regions (not shown in the figure) arranged at intervals in the epitaxial structure 101 through ion implantation, where the ion implantation regions form the device isolation structure, and the ion implantation may block communication between the device and the device by implanting N or He ions, and the size of the ion implantation region may be selected according to actual requirements. In another example, the method for forming the device isolation structure may further include performing ion implantation to form an ion implantation region 101b, and then etching the ion implantation region 101b to form an etched trench 101c and a remaining implantation region 101d, where the etched trench 101c and the remaining implantation region 101d form the device isolation structure 101a, as shown in fig. 5. By the double isolation mode, the isolation effect is good, and the exposed edge of the formed etched trench 101c is isolated by ion implantation, so that the edge leakage is inhibited.
Wherein the bottom of the device isolation structure 101a is lower than the two-dimensional electron gas 104a formed in the GaN channel layer 104 to form electrical isolation. In an example, the device isolation structure 101a stops on the lower surface of the GaN channel layer 104 through the barrier layer 105 and the GaN channel layer 104, or the device isolation structure 101a continues to extend downward, e.g., may extend downward into the buffer layer 103. The region between the adjacent device isolation structures 101a forms a device region, functional parts of devices can be prepared on the part of the epitaxial structure, the device isolation structures 101a can isolate two-dimensional electron gas, and the effect of device isolation is achieved, namely when a plurality of devices are manufactured on one wafer, electrical isolation is performed by using mesa isolation.
As shown in S4 of fig. 1 and fig. 7, step S4 is performed to form a source ohmic electrode 106 and a drain ohmic electrode 107 on the epitaxial structure 101 in the device region. In an example, the source ohmic electrode 106 and the drain ohmic electrode 107 may be defined by using a photolithography process, a photoresist layer may be formed on the epitaxial structure 101, an electrode opening may be formed by using the photolithography process, an area where the electrode needs to be formed is exposed, then a metal stack layer may be deposited on the entire surface, the metal stack layer may be a Ti/Al/Ni/Au stack layer, the thickness of each material layer may be 20 nm/100 nm/20 nm/100 nm, and the photoresist and the metal stack layer covering the photoresist layer may be removed by a lift-off process, so that only the metal stack layer in the electrode opening is left, thereby forming the source ohmic electrode 106 and the drain ohmic electrode 107.
In one example, the step of performing a high temperature anneal is further included after forming the source ohmic electrode 106 and the drain ohmic electrode 107, for example, the anneal temperature may be 800 ℃ to 900 ℃ and the anneal time may be 25s to 35s, in this example, 850 ℃ for 30 s, to form a good ohmic contact.
As shown in S5 of fig. 1 and fig. 8, step S5 is performed to form a native oxide layer 108 on the epitaxial structure 101 around the source ohmic electrode 106 and the drain ohmic electrode 107 of the device region, in one example, the native oxide layer 108 has a thickness between 1 nm and 5nm, such as 1.5nm, 2nm, or 3 nm. in one example, ozone (O3) is used to perform a surface treatment on the surface of the epitaxial structure 101 to form the native oxide layer 108, such as the structure is sent to an a L D device, an O3 gas source is introduced into the a L D device, i.e., an O3 gas source is introduced into a process chamber of a L D to form the native oxide layer 108, the upper surface of the epitaxial structure is treated with ozone to perform a clean passivation on the surface of the epitaxial structure, which can effectively remove residual photoresist in the surface of AlGaN, and carbon (C) and organic contaminants inevitably introduced during the process to provide a clean surface for other process steps.
As an example, before the structure obtained in the previous step is placed in a process chamber to form the native oxide layer 108, the method further includes the steps of performing ultrasonic cleaning on the upper surface of the epitaxial structure 101 by using a first cleaning agent, and then performing surface treatment on the ultrasonically cleaned structure by using a second cleaning agent, wherein the first cleaning agent optionally includes acetone, methanol and isopropanol, and the second cleaning agent includes hydrochloric acid and hydrofluoric acid, that is, before the gate oxide dielectric layer is deposited, performing ultrasonic cleaning on an AlGaN/GaN substrate (such as the surface of the epitaxial structure, for example, an AlGaN barrier layer) by using acetone, methanol and isopropanol, then performing cleaning by using wet HCl and HF, to remove surface impurities and an oxide layer, and finally sending the cleaned surface to an a L D device, wherein an O3 gas source is introduced into the a L D device, and performing further cleaning and passivation treatment on the epitaxial surface by using O3, and performing double treatment.
As shown in S6 of fig. 1 and fig. 9, step S6 is performed to form a gate oxide dielectric layer 109 on the native oxide layer 108 by in-situ deposition, which means that two different materials are grown back and forth in a same chamber without taking out the chamber to expose air and then feeding the other chamber to grow another material after one material is grown, in one example, the gate oxide dielectric layer is formed in an atomic layer deposition chamber based on an atomic layer deposition process, and the native oxide layer is formed based on the atomic layer deposition chamber, that is, the native oxide layer 108 and the gate oxide dielectric layer 109 are formed in a processing chamber based on a same a L D equipment, wherein the in-situ gate oxide dielectric layer growth is performed based on the same processing chamber as an a L D chamber, the in-situ dielectric growth method avoids the risk of surface contamination of the device surface exposed to air, and is beneficial to the quality of the gate oxide dielectric layer, optionally, the material of the gate oxide dielectric layer 109 includes but is not limited to HfO2 or Al2O3, which may be deposited with a thickness of 3515 nm or 3520 nm at 150-3515-3525-L a gate oxide dielectric layer deposition system using an a 565635D system.
As an example, the oxygen source used to form the gate oxide dielectric layer 109 may include ozone, the oxygen source is selected to be O3, instead of H2O as an oxygen source in conventional processes, A L D chemistry using O3 as an oxygen source gas reduces hydroxyl impurities (OH-) and residual hydrogen (H), thereby reducing oxide bulk and interface traps.
In addition, as shown in fig. 10, after the gate oxide dielectric layer 109 is formed, a step of forming a gate metal electrode 110 on the gate oxide dielectric layer 109 between the source ohmic electrode 106 and the drain ohmic electrode 107 is further included. In this example, the native oxide layer 108 and the gate oxide dielectric layer 109 are formed after the source ohmic electrode 106 and the drain ohmic electrode 107 are formed, and then the gate metal electrode 110 is formed, so as to facilitate formation of an effective ohmic contact between the source ohmic electrode 106 and the drain ohmic electrode 107, in an example, the ohmic contact has a high temperature annealing requirement, so the gate oxide dielectric layer 109 is prepared after the ohmic contact is completed, because a high-k gate oxide, such as Al2O3 or HfO2, cannot withstand a high temperature, otherwise, the gate oxide is crystallized, so that a leakage channel is formed, and gate leakage is caused. In one example, the gate electrode may be defined by photolithography and a metal electrode, such as Ni/Au, may be deposited to form the gate metal electrode 110, so as to complete the device fabrication.
In addition, as shown in fig. 9 and 10 and in combination with fig. 1 to 8, the present invention further provides a GaN device based on surface treatment, where the GaN device based on surface treatment is preferably prepared by using the method for preparing a GaN device based on surface treatment of the present invention, and of course, other preparation methods may also be used, and relevant structural features and beneficial effects may be referred to the description in the preparation method, and are not repeated herein, where the GaN device includes:
a semiconductor substrate 100;
an epitaxial structure 101 formed on the semiconductor substrate 100, the epitaxial structure 101 including a GaN channel layer 104;
a plurality of device isolation structures 101a arranged at intervals and formed in the epitaxial structure 101, wherein the bottoms of the device isolation structures 101a are lower than the two-dimensional electron gas 104a formed in the GaN channel layer 104, and a device region is defined between adjacent device isolation structures;
a source ohmic electrode 106 and a drain ohmic electrode 107 formed on the epitaxial structure 101 of the device region;
a native oxide layer 108 formed on the epitaxial structure 101 around the source ohmic electrode 106 and the drain ohmic electrode 107 in the device region;
and a gate oxide dielectric layer 109 formed on the native oxide layer 108 by in-situ deposition.
As an example, the GaN device further includes a gate metal electrode 110, wherein the gate metal electrode 110 is formed on the gate oxide dielectric layer 109 between the source ohmic electrode 106 and the drain ohmic electrode 107.
As an example, the epitaxial structure 101 further includes a transition layer 102, a buffer layer 103, and a barrier layer 105, wherein the transition layer 102, the buffer layer 103, the GaN channel layer 104, and the barrier layer 105 are sequentially disposed from bottom to top.
As an example, the native oxide layer 108 and the gate oxide dielectric layer 109 are formed on the same atomic layer deposition chamber.
As an example, the oxygen source forming the gate oxide dielectric layer 109 includes ozone.
As an example, the native oxide layer 108 is formed based on ozone treatment.
In summary, the GaN device based on surface treatment and oxidation process and the preparation method thereof of the present invention form a natural oxide layer on the surface of the epitaxial structure, which can be used as a passivation layer, and simultaneously clean the surface of the epitaxial structure, thereby effectively removing the residual photoresist layer and unnecessary carbon and organic matters in the process, and the like, and the formation of the gate oxide dielectric layer by in-situ deposition can avoid the risk of surface contamination caused by the exposure of the surface of the device to the air, and is beneficial to the film forming quality of the gate oxide dielectric layer.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (13)

1. A preparation method of a GaN device based on surface treatment and oxidation technology is characterized by comprising the following steps:
providing a semiconductor substrate;
forming an epitaxial structure on the semiconductor substrate, wherein the epitaxial structure comprises a GaN channel layer;
forming a plurality of device isolation structures which are arranged at intervals in the epitaxial structure, wherein the bottom of each device isolation structure is lower than two-dimensional electron gas formed in the GaN channel layer, and a device area is defined between every two adjacent device isolation structures;
forming a source ohmic electrode and a drain ohmic electrode on the epitaxial structure of the device region;
forming a natural oxide layer on the epitaxial structure around the source electrode ohmic electrode and the drain electrode ohmic electrode of the device region;
and carrying out in-situ deposition on the natural oxide layer to form a gate oxide dielectric layer.
2. The method of claim 1, further comprising the step of, after forming the gate oxide dielectric layer: and forming a grid metal electrode on the grid oxide dielectric layer between the source ohmic electrode and the drain ohmic electrode.
3. The method of claim 1, wherein the epitaxial structure further comprises a transition layer, a buffer layer, and a barrier layer, wherein the transition layer, the buffer layer, the GaN channel layer, and the barrier layer are sequentially disposed from bottom to top.
4. The method of claim 1, wherein the step of forming the device isolation structure comprises: forming a plurality of isolation grooves arranged at intervals in the epitaxial structure, wherein the isolation grooves form the device isolation structure, or forming a plurality of ion implantation areas arranged at intervals in the epitaxial structure through ion implantation, wherein the ion implantation areas form the device isolation structure, or firstly performing ion implantation to form the ion implantation areas, then etching the ion implantation areas to form an etching groove and a residual implantation area, and the etching groove and the residual implantation area form the device isolation structure.
5. The method of claim 4, wherein the isolation trench is formed by etching the epitaxial structure in a chlorine-based atmosphere when the isolation trench is formed; when the ion implantation region is formed, the ion implantation is performed using N ions or He ions.
6. The method of claim 1, wherein the step of forming the native oxide layer comprises: and placing the structure obtained in the last step in a process chamber, introducing ozone into the process chamber, and forming the natural oxidation layer based on the surface treatment of the ozone.
7. The method of claim 6, wherein the step of placing the structure obtained in the previous step in a process chamber further comprises: firstly, a first cleaning agent is adopted to carry out ultrasonic cleaning on the upper surface of the epitaxial structure, and then a second cleaning agent is adopted to carry out surface treatment on the structure subjected to ultrasonic cleaning, wherein the first cleaning agent comprises acetone, methanol and isopropanol, and the second cleaning agent comprises hydrochloric acid and hydrofluoric acid.
8. The method of any one of claims 1-7, wherein the gate oxide dielectric layer is formed in an atomic layer deposition chamber based on an atomic layer deposition process, and the native oxide layer is formed in the atomic layer deposition chamber based on the atomic layer deposition process.
9. The method of claim 8, wherein an oxygen source for forming the gate oxide dielectric layer comprises ozone.
10. A GaN device based on surface treatment and oxidation process, the GaN device comprising:
a semiconductor substrate;
an epitaxial structure formed on the semiconductor substrate, the epitaxial structure including a GaN channel layer;
the device isolation structures are arranged at intervals and formed in the epitaxial structure, the bottoms of the device isolation structures are lower than two-dimensional electron gas formed in the GaN channel layer, and a device area is defined between every two adjacent device isolation structures;
a source ohmic electrode and a drain ohmic electrode formed on the epitaxial structure of the device region;
the natural oxidation layer is formed on the epitaxial structure around the source electrode ohmic electrode and the drain electrode ohmic electrode of the device area; and
and the gate oxide dielectric layer is formed on the natural oxide layer through in-situ deposition.
11. The surface treatment and oxidation process-based GaN device of claim 10, further comprising a gate metal electrode formed on the gate oxide dielectric layer between the source ohmic electrode and the drain ohmic electrode; the epitaxial structure further comprises a transition layer, a buffer layer and a barrier layer, wherein the transition layer, the buffer layer, the GaN channel layer and the barrier layer are sequentially arranged from bottom to top.
12. The surface treatment and oxidation process-based GaN device according to claim 10 or 11, wherein the natural oxide layer and the gate oxide dielectric layer are formed based on the same atomic layer deposition chamber.
13. The surface treatment and oxidation process-based GaN device of claim 12, wherein the oxygen source forming the gate oxide dielectric layer comprises ozone; the native oxide layer is formed based on ozone treatment.
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