CN111403426A - 一种降低扩散暗电流的cmos图像传感器像素结构 - Google Patents
一种降低扩散暗电流的cmos图像传感器像素结构 Download PDFInfo
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Abstract
一种降低扩散暗电流的CMOS图像传感器像素结构,主要由光电二极管PPD、传输栅TG、浮空扩散节点FD、以及深N_abs层组成;STI为浅沟槽隔离,其作用是将相邻两个像素进行电学隔离,防止串扰现象;该像素结构采用多加一次高能量的N型掺杂注入,可以在外延层中性区形成新的耗尽区,使得中性区的大多数电荷被新形成的耗尽区收集,从而有效的降低中性区扩散暗电流,进一步提高了图像传感器的动态范围和信噪比,大大提高了成像质量。
Description
技术领域
本发明涉及CMOS图像传感器领域,尤其涉及一种降低扩散暗电流的CMOS图像传感器像素结构。
背景技术
钳位光电二极管(pinned photodiode,PPD)最初被用在CCD图像传感器中,二十多年后才被用于CMOS图像传感器。图1是基于PPD的4T像素结构。4T像素由PPD、传输管(Transfer Gate, TG)、复位管(Reset, RST)、源级跟随器(Source Follower, SF)行选通管(Selector Transistor, SEL)以及浮空扩散节点(Floating Diffusion, FD)组成。当光入射到半导体表面时,其中一部分入射光被反射,而其余则被半导体吸收。当进入半导体内部的光子能量不低于半导体材料禁带宽度时,那么半导体材料便有一定概率吸收这份能量,从而产生电子-空穴对,即光生载流子。光照积分完成后,传输管导通,光生电荷在电场的作用下由光电二极管区域转移至浮空扩散节点,即完成电荷-电压信息的转换过程,最后通过行选通管以及列级读出电路,逐行读出存储在浮空扩散节点的光信号。
暗电流是指CMOS图像传感器在无光照的条件下所输出的信号值,是一种非理想因素,暗电流会积分成为暗电荷并被存储于像素电荷存储节点(无论是暗光条件还是光照条件时都存在)。暗电流水平通常与像素工艺流程紧密联系,如下图2所示,为PPD中的主要暗电流来源,包括:耗尽区产生暗电流、表面产生暗电流、STI暗电流、TG沟道区暗电流、中性区扩散暗电流。
像素外延层中,除耗尽层外的部分均为中性区,其中的自由电子由于热运动作用,使得靠近PPD耗尽区的中性区中的自由电子有一定概率被PPD收集,从而形成暗电流。本专利针对像素中存在中性区扩散暗电流的问题,提出一种在中性区形成耗尽层的方法,使得中性区的大多数电荷被新形成的耗尽区收集,从而降低了像素的中性区扩散暗电流。
发明内容
针对现有技术存在的问题,本发明一种降低扩散暗电流的CMOS图像传感器像素结构,采用多加一次高能量的N型掺杂注入,可以在外延层中性区形成新的耗尽区,使得中性区的大多数电荷被新形成的耗尽区收集,从而有效的降低中性区扩散暗电流,进一步提高了图像传感器的动态范围和信噪比,大大提高了成像质量。
一种降低扩散暗电流的CMOS图像传感器像素结构,如图3所示。该像素结构主要由光电二极管PPD、传输栅TG、浮空扩散节点FD、以及深N_abs层组成;STI为浅沟槽隔离,其作用是将相邻两个像素进行电学隔离,防止串扰现象;用CMOS工艺制造图像传感器的像素时,首先进行栅前的P+钳位层离子注入,然后进行高能量N型离子的注入,形成位于PPD下方的N_abs吸收层,进而进行栅的形成,最后利用自对准技术进行栅后PPD区域N-型掺杂的离子注入以及FD节点的N+型离子注入,最后形成的具有高能量N_abs层的像素结构如图3所示。此结构通过在PPD耗尽区1的下方注入一层N型掺杂,从而与外延层形成耗尽区2,尤其需要注意的是耗尽区1和耗尽区2应该分离开,故N_abs层的形成,其离子注入能量较大。
当光照射到PPD区域时,半导体材料中价带的电子吸收光子的能量,从价带越过禁带到达导带,从而形成光生电子-空穴对,即光生载流子,在耗尽区电场的作用下,光生电子被收集在PPD区域,而光生空穴被衬底吸收。与此同时,由PPD形成的耗尽区下方的中性区内的少数载流子-电子会以热运动作用或者扩散的作用到达PPD区域,形成与光信号无关的暗电流,降低图像传感器的信噪比。故本发明提出的结构,即与传统的4T有源像素相比,在中性区内多引入一次高能量的N型离子注入,可以与中性区的P型半导体形成新的耗尽区,从而中性区内的电子会在电场的作用下被收集到新形成的耗尽区内,减少了进入PPD区域形成信号电荷的暗电子,降低中性区扩散暗电流,提高传感器的成像质量。
附图说明
图1是4T像素基本结构图;
图2是像素暗电流来源分布图;
图3是有深N-abs层的二维像素设计图。
具体实施方式
以下根据附图和实施例对本发明进行详细说明,但是本发明的保护范围不限于此。
本发明通过在栅形成前引入N型高能离子注入的N_abs层,在原PPD区域下方的中性区增加一个耗尽区2,从而在电场的作用下收集来自中性区的扩散暗电荷,等效降低了PPD耗尽区1对中性区扩散暗电荷的收集,有效的降低了像素的暗电流,提高图像传感器的成像质量。
本发明提出的降低中性扩散区暗电流的CMOS图像传感器像素结构,适用于短波长大感光面积的像素,PPD耗尽区1与外延层接触面积大,中性扩散区中的暗电荷数量较多,故中性区扩散暗电流对整个像素总的暗电流贡献较大,采用本专利所提出的像素结构,可以有效降低中性区的扩散暗电荷。例如,对于10um×10um的大像素来说,采用1e15/cm2的B离子掺杂形成的P型外延层,PPD的掩埋N层用一次N型离子注入完成,采用As离子注入,注入剂量为3.0e12/cm2,注入能量为100KeV,注入角度tilt为7°,PPD与P型外延层形成的耗尽区1的深度可达1um;深N_abs层采用P离子注入,注入剂量为5e11/cm2,注入能量为1200KeV,注入角度tilt为7°,N_abs层与外延层形成的耗尽区深度范围大约为2um-2.8um之间。按照以上工艺条件形成的耗尽区1和耗尽区2在空间上未交叠,可以很好的降低像素中性区扩散暗电流,进而提高图像传感器的动态范围和信噪比。
采用以上像素结构可以实现基于PPD结构上的结构优化,用以在保证大感光面积的基础上,同时实现较低中性区扩散暗电流的像素单元设计。
Claims (1)
1.一种降低扩散暗电流的CMOS图像传感器像素结构,其特征在于:主要由光电二极管PPD、传输栅TG、浮空扩散节点FD、以及深N_abs层组成;STI为浅沟槽隔离,其作用是将相邻两个像素进行电学隔离,防止串扰现象;用CMOS工艺制造图像传感器的像素时,首先进行栅前的P+钳位层离子注入,然后进行高能量N型离子的注入,形成位于PPD下方的N_abs吸收层,进而进行栅的形成,最后利用自对准技术进行栅后PPD区域N-型掺杂的离子注入以及FD节点的N+型离子注入,最后形成的具有高能量N_abs层的像素结构;此结构通过在PPD耗尽区1的下方注入一层N型掺杂,从而与外延层形成耗尽区2,耗尽区1和耗尽区2应该分离开,故N_abs层的形成,其离子注入能量较大。
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CN114335045A (zh) * | 2022-03-10 | 2022-04-12 | 合肥晶合集成电路股份有限公司 | 一种降低cmos图像传感器暗电流的方法 |
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US4242695A (en) * | 1978-01-27 | 1980-12-30 | Hitachi, Ltd. | Low dark current photo-semiconductor device |
CN101171828A (zh) * | 2005-05-04 | 2008-04-30 | 美光科技公司 | 4t cmos成像器像素中的暗电流和溢出抑制方法和设备 |
US20120286144A1 (en) * | 2010-11-12 | 2012-11-15 | Namlab Gmbh | Photodiode, photodiode array and method of operation |
CN105870004A (zh) * | 2016-04-07 | 2016-08-17 | 上海华力微电子有限公司 | 消除cmos图像传感器浅沟槽隔离诱导暗电流的方法 |
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US4242695A (en) * | 1978-01-27 | 1980-12-30 | Hitachi, Ltd. | Low dark current photo-semiconductor device |
CN101171828A (zh) * | 2005-05-04 | 2008-04-30 | 美光科技公司 | 4t cmos成像器像素中的暗电流和溢出抑制方法和设备 |
US20120286144A1 (en) * | 2010-11-12 | 2012-11-15 | Namlab Gmbh | Photodiode, photodiode array and method of operation |
CN105870004A (zh) * | 2016-04-07 | 2016-08-17 | 上海华力微电子有限公司 | 消除cmos图像传感器浅沟槽隔离诱导暗电流的方法 |
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CN114335045A (zh) * | 2022-03-10 | 2022-04-12 | 合肥晶合集成电路股份有限公司 | 一种降低cmos图像传感器暗电流的方法 |
CN114335045B (zh) * | 2022-03-10 | 2022-06-03 | 合肥晶合集成电路股份有限公司 | 一种降低cmos图像传感器暗电流的方法 |
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