CN111295766A - 高电压隔离结构及方法 - Google Patents

高电压隔离结构及方法 Download PDF

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CN111295766A
CN111295766A CN201880070134.7A CN201880070134A CN111295766A CN 111295766 A CN111295766 A CN 111295766A CN 201880070134 A CN201880070134 A CN 201880070134A CN 111295766 A CN111295766 A CN 111295766A
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dielectric
plate
capacitor
high voltage
conductive
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托马斯·戴尔·博尼菲尔德
卡纳安·桑达拉潘迪安
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Texas Instruments Inc
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Abstract

所描述的实例包含一种具有高电压电容器(101)的微电子装置(100)，其包含：高电压节点(130)；低电压节点(111)；第一电介质(104)，其安置于所述低电压节点(111)与所述高电压节点(130)之间；第一导电板(120)，其安置于所述第一电介质(104)与所述高电压节点(130)之间；及第二电介质(123)，其安置于所述第一导电板(120)与所述高电压节点(130)之间。

Description

高电压隔离结构及方法
背景技术
高电压隔离电容器的额定电压受高电场限制，所述高电场在形成高电压电容器金属的金属的底部边缘处出现。为了防止电介质击穿，高电压电容器可相对于给定操作电压电平的要求加大尺寸。然而，尺寸加大的电容器或其它高电压组件占用过多微电子装置区域。
发明内容
所描述的实例提供具有高电压组件的微电子装置，其包含：高电压节点；低电压节点；第一电介质，其安置于所述高电压节点与所述低电压节点之间；第一导电板，其在所述第一电介质与所述高电压节点之间；及第二电介质，其安置于所述第一导电板与所述高电压节点之间。
所描述的另一实例提供一种电容器，其包含：导电第一电容器板，其安置于衬底上方；第一电介质，其安置于所述导电下板之上；及导电第一浮动板，其安置于所述第一电介质之上。所述第一浮动板与所述第一电容器板电隔离。所述电容器还包含：第二电介质，其安置于所述第一浮动板之上；及导电第二电容器板，其安置于所述第二电介质之上，其中所述第二电容器板与所述第一浮动板电隔离。
另外实例提供一种形成微电子装置的方法，所述方法包含：在衬底上方形成导电第一电容器板；在所述导电下板之上形成第一电介质；在所述第一电介质之上形成导电第一浮动板；在所述第一浮动板之上形成第二电介质；及在所述第二电介质之上形成导电第二电容器板。
附图说明
图1是包含具有高电压与低电压之间的浮动板、上电容器板及下电容器板的高电压电容器的实例微电子装置的局部截面侧视图。
图2是具有说明展示高电压电容器板的拐角处的高电场强度的等势线的高电压电容器的另一微电子装置的局部截面侧视图。
图3是随图2的高电压电容器板下方的电容器电介质中的横向距离而变化的电场强度的曲线图。
图4是展示包含具有高电压与低电压之间的浮动板、上电容器板及下电容器板的高电压电容器的另一实例微电子装置的局部截面侧视图，其说明等势线。
图5是随图4的高电压电容器板下方的电容器电介质中的横向距离而变化的电场强度的曲线图。
图6是展示包含具有高电压与低电压之间的浮动板、上电容器板及下电容器板的高电压电容器的另一实例微电子装置的局部截面侧视图，其说明等势线。
图7是随图6的高电压电容器板下方的电容器电介质中的横向距离而变化的电场强度的曲线图。
图8是展示包含具有高电压与低电压之间的多个浮动板、上电容器及下电容器板的高电压电容器的又另一实例微电子装置的局部截面侧视图，其说明等势线。
具体实施方式
在图中，相似参考数字指代全文的相似元件，且各种特征不一定是按比例绘制。
图1展示包含高电压组件101的微电子装置100。在一个实例中，高电压组件101是与一或多个额外组件一起形成于集成电路(IC)装置中的垂直高电压电容器。在一些实例中，电容器101是独立组件或混合电路的部分。图1中的装置100形成于半导体衬底102上，例如硅晶片、绝缘体上硅(SOI)衬底或其它半导体结构。一或多个隔离结构103形成于衬底102的上表面的选择部分上。在一些实例中，隔离结构103可为浅沟槽隔离(STI)特征或场氧化物(FOX)结构。在一个实例中，高电压电容器101形成于衬底102上方的多层金属化结构中。金属化结构包含形成于衬底102上方的第一电介质结构104。在一个实例中，第一电介质104是多层结构。在一个实例中，第一电介质104安置于预金属电介质(PMD)层106上方。在一个实例中，PMD层106包含沉积于衬底102及场氧化物结构103之上的二氧化硅(SiO2)。在所说明的实例中，导电法拉第笼结构107形成于衬底102上方以围绕高电压电容器装置101的全部或一部分。法拉第笼结构107在第一电介质104中形成隔离缺口，使得第一电介质104在隔离缺口处不连续。在一个实例中，隔离缺口法拉第笼结构107横向环绕高电压电容器101的全部或至少一部分。
在一个实例中，第一电介质104是多层结构。在一个实例中，多层结构使用集成电路制造处理形成为多层金属化结构。图1展示实例6层电介质结构，其包含第一层108，在本文中称为层间(interlayer/interlevel)电介质(ILD)层。在其它实施方案中可使用不同数目个层。在一个实例中，第一电介质的个别层由二氧化硅(SiO2)或其它合适的电介质材料形成。在某些实施方案中，多层第一电介质104的个别层在两个阶段中形成，包含金属内电介质(IMD)子层及上覆于IMD子层的ILD子层。个别IMD及ILD子层可由任一或多种合适的电介质材料形成，例如基于SiO2的电介质材料。实例微电子装置100是包含高电压电容器组件101及一或多个低电压组件(例如形成于衬底102上或中的金属氧化物半导体(MOS)晶体管109)的集成电路。穿过PMD层106的选择性部分形成钨或其它导电接点110，包含形成法拉第笼结构107到衬底102的底部连接的接点，还包含到晶体管109的端子的接点。
高电压电容器101的低电压节点111形成为衬底102上方的导电第一电容器板。低电压节点111提供实例垂直电容器结构101中的底部电容器板。在一个实例中，低电压节点111是铝或其它合适的导电材料，其在集成电路制造期间作为多层金属化工艺的部分形成于PMD层106的一部分之上。第一电介质结构104的第一层108覆盖导电低电压节点111。在某些实施方案中，低电压节点111电连接到微电子装置100内的一或多个额外电路组件。在一个实例中，电容器101用作用于与外部电路(未展示)通信的隔离电容器，且低电压电容器板连接到微电子装置100内的收发器电路(未展示)。在此实例中，下文进一步描述的高电压电容器板连接到外部电路以允许跨电压势垒通信。低电压节点111可由第一层或图5中所展示的方法形成，或在各种实施方案中，可形成于任何其它金属层中。
第一ILD层108及多层第一电介质结构104中的后续ILD层包含形成于下伏层的顶部表面上的金属化互连结构112，例如铝。在此实例中，第一层108还包含导电通孔113，例如钨，从而提供从层108的金属化特征112到上覆金属化层的电连接。图1展示七层金属化结构，但可使用任何数目个金属化层。在所说明的实例中，第二层114形成于第一层108之上，且包含导电互连结构112及通孔113。所说明的结构包含具有对应电介质层115、116、117及118的另外金属化层。个别层115到118包含导电互连结构112及相关联通孔113。在此实例中，法拉第笼结构107通过连续连接衬底102与钨接点110、互连结构112及通孔113而形成以基本上围封且电隔离高电压电容器101与微电子装置100内的其它电路。以此方式，晶体管109及其它低电压组件可与高电压节点及电容器101的其它高电压特征电隔离。另外，第一电介质104，包含由法拉第笼结构107的导电结构110、112及113提供的隔离缺口内的层108及114到117，为高电压电容器101提供第一电介质。
电容器101进一步包含安置于第一电介质104之上的导电第一浮动板120。在所说明的实例中，第一浮动板120是导电板，例如铝，其形成为电介质层118中的金属化层特征的部分。导电浮动板120增强微电子装置的电容密度。第一浮动板120与第一电容器板111及上电容器板电隔离。在一个实例中，浮动板120完全由电介质材料层117及118囊封。在此实例中，第一电介质104在浮动板120的下表面与低电压节点111的上表面之间(在图1中的Y方向上)具有第一厚度121。
高电压电容器101进一步包含安置于第一浮动板120之上的第二电介质123。在此实例中，第二电介质123由上覆于第一浮动板120的电介质层118的部分形成。电容器101还包含安置于第二电介质123之上的导电第二或上电容器板130。在所说明的实例中，第二电容器板130是形成于第二电介质123的顶部表面之上的导电板，例如铝。第二电容器板130与第一电容器板111及浮动板120电隔离。浮动板120上方的第二电介质123在第一浮动板120的上表面与高电压节点130的下表面之间具有厚度122(沿Y方向)。第一厚度121与第二厚度122可相同。在某些实例中，第一厚度121不同于第二厚度122。在图1的实例中，第一厚度121显著大于第二厚度122。在一个实例中，电容器电介质104、123的厚度121及122是至少2μm，且可通过高电压节点130相对于低电压节点111及(可能地)衬底102的所要操作电压来确定。举例来说，其中高电压节点130经设计以在1000伏特操作的高电压电容器101的版本可具有电容器电介质104、123，其具有层121及122的5微米到20微米的组合厚度。
微电子装置100进一步包含上IMD电介质层124及保护外套(PO)层126及128，例如，氮化硅(SiN)、氮氧化硅(SiOxNy)或二氧化硅(SiO2)。在一个实例中，层124、126及128包含开口，其允许接合线结构134连接到第二电容器板134的上表面，连接到外部电路(未展示)。在此实例中，第二电容器板130提供高电压电容器101的高电压节点。
如图1中展示，高电压电容器101包含通过安置于低电压节点111与高电压节点130之间的第一电介质104分离的高电压节点130(例如导电上电容器板)及低电压节点111(例如导电下电容器板)。图1中的高电压组件101包含安置于第一电介质104与高电压节点130之间的第一导电板120。另外，高电压组件101包含安置于第一导电板120与高电压节点130之间的第二电介质123。在一个实例中，第一导电板120是浮动的且与低电压节点111及高电压节点130电隔离。
高电压节点130通过第一电介质104及第二电介质123与低电压节点111隔离，且电容器结构101包含高电压节点130与低电压节点111之间的额外浮动板120。在操作中，在电容器板111与130之间提供导电浮动板120会修改电容器电介质材料104及123中的电场分布。
还参考图2及3，图2展示具有由上电容器板202、下导电电容器板204及中介电介质材料206形成的高电压电容器的微电子装置200。图2中的电容器形成于衬底208之上，其中场氧化物结构210位于下电容器板204下方。法拉第笼结构212与电容器的侧间隔。图2展示当上电容器板202处于相对于下电容器板204的电压的高电压时的实例等势线214。在等势线214在上电容器板202的横向底部边缘附近的电介质材料206中彼此靠近之处电场强度较高。图3展示曲线图300，其说明电场强度301在上电容器板202的横向边缘处的距离D1处达到显著峰值的电场强度曲线301。为了避免电介质材料击穿，图2的电容器针对给定额定击穿电压加大尺寸，使得曲线301中的峰值低于电介质材料206的击穿电压阈值。
返回到图1，与不具有浮动板120的电容器设计(例如图2)相比，在高电压组件101中提供浮动板120有利地降低了高电压节点130的底部拐角附近的电场电平。高电压节点130具有第一横向尺寸131(例如在图1中沿X方向的宽度)。低电压节点111具有第二横向尺寸132，且第一导电板120具有第三横向尺寸133。在图1的实例中，浮动板120比高电压节点130宽(浮动板宽度尺寸133大于上电容器板宽度尺寸131)。另外，浮动板120距上电容器板130比距下电容器板111更近。在各种实施方案中，浮动板120相对于电容器板111及130的相对大小及位置可经裁剪以控制第一电介质材料104及第二电介质材料123中的电场强度以满足给定额定电压击穿电平而无需将电容器101的尺寸设置过大。此有利地节省微电子装置100中的面积，无论是独立高电压组件产品还是集成电路。
图4展示包含高电压电容器101的另一实例微电子装置400，其中浮动板120位于高电压节点130与低电压节点111之间。图4还展示当高电压节点130处于相对于低电压节点111的电压的高电压时的等势线402。电容器101大体上如上文描述。在此实例中，浮动板120距低电压节点111比距高电压节点130更近。第二电介质123的厚度尺寸122(沿Y方向)大于第一电介质104的厚度尺寸121。另外，浮动板120的横向宽度尺寸133(沿图4中的X方向)大于高电压节点130及低电压节点111的横向宽度尺寸131及132。
图5提供曲线图500，其展示两个实例电介质位置处随图4的电容器中的电容器电介质123及104中的横向位置(沿X方向)而变化的对应电场强度。特定来说，图5中的第一曲线501展示随恰好在高电压节点130下方的第二电介质123中的垂直位置404(图4)处的X方向位置而变化的电场强度。曲线501包含对应于高电压节点130的横向边缘的第一距离D1处的峰值。图5中的第二曲线502展示随恰好在浮动板120下方的第一电介质104中的第二垂直位置406(图4)处的X方向位置而变化的电场强度。曲线502包含对应于浮动板120的横向边缘的第二距离D2处的峰值。在此实例中(如同上文图1的实例)，较宽浮动板120趋于使等势线402横向向外延伸以减少高电压节点130的底部横向边缘附近的等势线拥挤。浮动板120的横向范围可经裁剪以便调整电容器电介质104及123的电场强度中的峰值，使得所有峰值电平(例如，包含曲线501及502中的峰值)低于给定电介质材料的击穿公差电平及电容器101的给定额定操作电压。
参考图6及7，说明另一实例微电子装置600，包含包括上文大体上所描述的高电压节点130、低电压节点111、第一电介质104及第二电介质123及浮动板120的高电压电容器101。图6还展示当高电压节点130处于比低电压节点111更高的电压时的等势线602。在此实例中，浮动板120距高电压节点130比距低电压节点111更近。第二电介质123的厚度尺寸122(沿Y方向)小于第一电介质104的厚度尺寸121。如同图4的实例，浮动板120的横向宽度尺寸133(沿图6中的X方向)大于高电压节点130及低电压节点111的横向宽度尺寸131及132。
图7展示两个实例电介质位置604及606处随图6中的电容器电介质123及104中的横向位置(沿X方向)而变化的电场强度的曲线图700。曲线图700包含第一曲线701，其展示恰好在高电压节点130下方的第二电介质123中的垂直位置604(图4)处的电场强度。第一曲线701包含对应于高电压节点130的横向边缘的第一距离D1处的峰值。曲线图700包含第二曲线702，其展示随恰好在浮动板120下方的第一电介质104中的第二垂直位置606处的电场强度。曲线702包含对应于浮动板120的横向边缘的第二距离D2处的峰值。图6中的浮动板120使等势线602横向向外延伸以减少高电压节点130的底部横向边缘附近的等势线拥挤。在此案例中，浮动板120下的第一电介质104中的曲线702中的电场强度峰值高于高电压节点130下的曲线701中的峰值。
参考图8，在另外实例中，两个或两个以上浮动板可包含于高电压节点130与低电压节点111之间。图8展示具有上文大体上所描述的高电压电容器101的另一实例微电子装置。在此实例中，高电压电容器101包含电容器板130与111之间的多个浮动板800、802及120。此实例还包含另外电介质层804及806。另外，浮动板800、802及120分别具有不同横向长度133、803及801。在此实例中，电容器101包含低电压节点111与最下浮动板800之间的具有深度尺寸121的第一电介质104。另外，第二电介质123安置于高电压节点130与第一浮动板120之间，其具有厚度尺寸122。在此实例中，第二浮动板802安置于第一浮动板120与第一电介质104之间。另外，在此实例中，第二浮动板802具有比第一浮动板120长的横向尺寸803。具有厚度尺寸807的第三电介质806安置于第一浮动板120与第二浮动板802之间。第三浮动板800具有比第二浮动板802长的横向尺寸801。具有厚度尺寸805的第四电容器电介质804形成于第二浮动板802与第三浮动板800之间。图8展示操作的等势线808，其中高电压节点130处于比低电压节点111高的电压。图8中的等势线808展现指示浮动板800、802及120的横向端处的高电场强度的拥挤。另外，如在上文实例中，浮动板800、802及120的存在趋于减少高电压节点130的横向端附近的等势线拥挤。
在上文实例中使用一或多个浮动板120、800、802有利地控制高电压电子组件101的场分布。特定设计可经裁剪以减小电容器101中的高电场点的量值以改进所得高电压电容器101的最大额定电压及/或减小电容器101针对给定最大额外电压的大小。以此方式，形成导电浮动板120增强了微电子装置的电容密度。另外，使用浮动板的某些实施方案可有利地增加在板之间且远离其横向边缘的电场，借此增加高电压组件101的电容。所描述的实例可结合任何类型的电容器电介质材料及任何合适的导电板材料使用。一些实施例可作为集成电路制造工艺的部分进行制造，其中一或多个金属化层掩模选择性地经修改以在选择金属化层(layer/level)之间提供一或多个浮动板120、800、802。此外，此类掩模修改可经设计以提供任何所要横向浮动板尺寸以针对特定电介质材料额定击穿电压及电容器操作电压电平裁剪给定设计。在一个实例中，上文描述的微电子装置可通过在衬底(例如半导体衬底102)上方形成导电第一电容器板(例如低电压节点111)及在导电下板111之上形成第一电介质(例如电介质104)来制造。第一电介质可经形成为多个电介质层(例如108、114到117)。实例制造工艺进一步包含：在第一电介质104之上形成导电第一浮动板(例如浮动板120)；在第一浮动板120之上形成第二电介质(例如123)；及在第二电介质123之上形成导电第二电容器板(例如高电压节点130)。如上文在图1中展示，制造工艺还可包含在第一电介质104中形成隔离缺口107，使得第一电介质104在隔离缺口处不连续，且隔离缺口107环绕第一浮动板120。在某些实施例中，制造工艺还可包含在衬底102上或中形成一或多个低电压组件(例如，图1中的晶体管109)。
修改在所描述的实施例中是可能的，且在权利要求书的范围内，其它实施例是可能的。

Claims (21)

1.一种微电子装置，其包括：
所述微电子装置的高电压组件的高电压节点；
所述高电压组件的低电压节点；
第一电介质，其安置于所述低电压节点与所述高电压节点之间；
第一导电板，其安置于所述第一电介质与所述高电压节点之间；及
第二电介质，其安置于所述第一导电板与所述高电压节点之间。
2.根据权利要求1所述的微电子装置，其中所述高电压组件是高电压电容器，所述低电压节点是所述高电压电容器的下板，所述高电压节点是所述高电压电容器的上板，且所述第一导电板与所述低电压节点及所述高电压节点电隔离。
3.根据权利要求1所述的微电子装置，其中所述第一电介质具有第一厚度，所述第二电介质具有第二厚度，且所述第一厚度不同于所述第二厚度。
4.根据权利要求3所述的微电子装置，其中所述高电压节点具有第一横向尺寸，所述低电压节点具有第二横向尺寸，所述第一导电板具有第三横向尺寸，所述第三横向尺寸大于所述第一横向尺寸。
5.根据权利要求1所述的微电子装置，其中所述高电压节点具有第一横向尺寸，所述低电压节点具有第二横向尺寸，所述第一导电板具有第三横向尺寸，所述第三横向尺寸大于所述第一横向尺寸。
6.根据权利要求1所述的微电子装置，其进一步包括：
第二导电板，其安置于所述第一导电板与所述第一电介质之间；及
第三电介质，其安置于所述第一导电板与所述第二导电板之间。
7.根据权利要求6所述的微电子装置，其中所述第二导电板具有第四横向尺寸，且所述第四横向尺寸不同于所述第三横向尺寸。
8.根据权利要求1所述的微电子装置，其中所述第一电介质包括多个电介质层，所述多个电介质层包括基于二氧化硅的电介质材料。
9.根据权利要求1所述的微电子装置，其进一步包括所述第一电介质中的隔离缺口，使得所述第一电介质在所述隔离缺口处不连续，且所述隔离缺口环绕所述第一导电板。
10.根据权利要求8所述的微电子装置，其进一步包括安置于所述隔离缺口外的低电压组件。
11.一种电容器，其包括：
导电第一电容器板，其安置于衬底上方；
第一电介质，其安置于所述导电下板之上；
导电第一浮动板，其安置于所述第一电介质之上，所述第一浮动板与所述第一电容器板电隔离；
第二电介质，其安置于所述第一浮动板之上；及
导电第二电容器板，其安置于所述第二电介质之上，所述第二电容器板与所述第一浮动板电隔离。
12.根据权利要求11所述的电容器，其中所述第一电介质具有第一厚度，所述第二电介质具有第二厚度，且所述第一厚度不同于所述第二厚度。
13.根据权利要求11所述的电容器，其中所述浮动板具有不同于所述第一电容器板的横向尺寸的横向尺寸。
14.根据权利要求11所述的电容器，其进一步包括：
导电第二浮动板，其安置于所述第一浮动板与所述第一电介质之间，所述第二浮动板与所述第一及第二电容器板电隔离；及
第三电介质，其安置于所述第一浮动板与所述第二浮动板之间。
15.根据权利要求14所述的电容器，其中所述第二浮动板具有不同于所述第一浮动板的横向尺寸的横向尺寸。
16.根据权利要求11所述的电容器，其中所述第一电介质包括多个电介质层，所述多个电介质层包括基于二氧化硅的电介质材料。
17.一种形成微电子装置的方法，所述方法包括：
在衬底上方形成导电第一电容器板；
在所述导电下板之上形成第一电介质；
在所述第一电介质之上形成导电第一浮动板；
在所述第一浮动板之上形成第二电介质；及
在所述第二电介质之上形成导电第二电容器板。
18.根据权利要求17所述的方法，其进一步包括：
在所述第一浮动板与所述第一电介质之间形成导电第二浮动板；及
在所述第一浮动板与所述第二浮动板之间形成第三电介质。
19.根据权利要求17所述的方法，其进一步包括：
形成所述第一电介质作为包括基于二氧化硅的电介质材料的多个电介质层。
20.根据权利要求17所述的方法，其进一步包括：
在所述第一电介质中形成隔离缺口，使得所述第一电介质在所述隔离缺口处不连续，且所述隔离缺口环绕所述第一浮动板。
21.根据权利要求17所述的方法，其中形成所述导电第一浮动板增强了所述微电子装置的电容密度。
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