CN111261614A - Anti-electromagnetic pulse protection ring around PN junction and manufacturing method thereof - Google Patents
Anti-electromagnetic pulse protection ring around PN junction and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses an anti-electromagnetic pulse protection ring around a PN junction and a manufacturing method thereof, belonging to the field of microelectronic manufacturing processes. A manufacturing method of an anti-electromagnetic pulse protection ring around a PN junction comprises the following steps: 1) oxidizing the silicon material, and carrying out protective ring photoetching according to a design layout; 2) injecting boron element into the photoetching area for doping; the doping concentration of boron element is 1 x 1016～5×1016cm‑3(ii) a 3) Performing impurity diffusion at 1150-1180 ℃ to form an initial protection ring; 4) injecting a P region, and injecting boron again for doping after the P region is injected; and performing secondary diffusion on the doping elements at 1100-1150 ℃, and forming the anti-electromagnetic pulse protection ring with the junction depth of more than 5 mu m through the secondary diffusion. The anti-electromagnetic pulse protection ring around the PN junction solves the problem that the anti-electromagnetic impact capability is improved by increasing the peripheral area or the junction depth of the PN junction in the prior art.
Description
Technical Field
The invention belongs to the field of microelectronic manufacturing processes, and particularly relates to an anti-electromagnetic pulse protection ring around a PN junction and a manufacturing method thereof.
Background
At present, a metal shielding method is mainly adopted for protecting the semiconductor discrete device from strong electromagnetic pulses, and the method has complex production process and higher control difficulty; and the long-term reliability of the device is reduced due to the mutual influence between the metal materials.
The semiconductor discrete device can be damaged under the impact of electromagnetic pulses, and the damage modes are as follows: open circuit, short circuit, transistor gain drop, etc., and the damage mechanisms are mainly thermal ablation and electrical breakdown. At present, the anti-electromagnetic shock capability is generally improved by increasing the peripheral area or the junction depth of the PN junction.
Disclosure of Invention
The invention aims to overcome the defect that a semiconductor discrete device can be damaged under the impact of electromagnetic pulses, and provides an anti-electromagnetic pulse protection ring around a PN junction and a manufacturing method thereof.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
an anti-electromagnetic pulse protection ring around a PN junction, the junction depth of the protection ring is greater than that of the PN junction.
Further, the guard ring is obtained by impurity diffusion of a group IIIA element.
A manufacturing method of an anti-electromagnetic pulse protection ring around a PN junction comprises the following steps:
1) oxidizing the silicon material, and carrying out protective ring photoetching according to a design layout;
2) injecting IIIA group elements into the photoetching area for doping;
the doping concentration of the element is 1 x 1016～5×1016cm-3；
3) Performing impurity diffusion at 1150-1180 ℃ to form an initial protection ring;
4) injecting a P region, and injecting elements again for doping after the P region is injected;
performing secondary diffusion on the doping element at 1100-1150 ℃ to form a protective ring through the secondary diffusion; the guard ring junction depth is greater than the PN junction depth.
Further, the initial guard ring junction depth is equal to the PN junction depth.
Further, the injection element in the step 2) and the step 4) is boron element.
Further, the implantation element in the step 2) and the step 4) is indium element.
Compared with the prior art, the invention has the following beneficial effects:
according to the anti-electromagnetic pulse protection ring around the PN junction, the junction depth of the protection ring is larger than that of the PN junction, the anti-electromagnetic impact capability is improved by arranging the protection ring at the periphery of the PN junction, the curvature radius of the PN junction can be increased by the protection ring around the PN junction, the PN junction is similar to a plane junction, the current distribution of the PN junction is uniform, the breakdown voltage is improved, the resistance to strong current and strong voltage is enhanced, and the purpose of improving the strong electromagnetic pulse resistance of a device is achieved; the anti-electromagnetic pulse protection ring around the PN junction improves the anti-electromagnetic impact capability of the PN junction and reduces the size of a device.
According to the manufacturing method of the anti-electromagnetic pulse protection ring around the PN junction, secondary diffusion is adopted, and the diffusion temperature is reduced during the secondary diffusion, so that the formation of defects in silicon materials is reduced; on the other hand, the secondary diffusion changes the impurity concentration distribution of the doped region, so that the impurity concentration on the surface of the protection ring is improved, and the surface leakage current of the device is reduced; the secondary diffusion is adopted, so that the transverse diffusion of the protection ring is reduced, and the effective area of the PN junction is increased; the anti-electromagnetic impact capacity is adjusted by adjusting the distance between the PN junction and the protection ring, the TVS device meeting different parameter requirements is wide in application range.
Drawings
FIG. 1 is a schematic structural diagram of an electromagnetic pulse resistant guard ring made in accordance with the present invention;
fig. 2 is a diagram of a typical output waveform of a bi-exponential pulse.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The PN junction thermal ablation mainly occurs in the area with concentrated edge current, so that the appearance of the PN junction is improved, the current edge effect of the device is reduced, the thermal ablation phenomenon of the device can be effectively prevented, and the electromagnetic pulse resistance of the device is improved; for the electric breakdown phenomenon, the PN junction breakdown is changed into the plane junction breakdown mainly by improving the junction surface appearance of the PN junction, so that the capability of improving the electric breakdown resistance of the device is achieved. In order to improve the strong electromagnetic pulse resistance of the device and meet the use requirements of the space electromagnetic environment on the semiconductor discrete device. According to the invention, an anti-electromagnetic pulse protection ring structure is formed around the main junction of the device by adopting a secondary diffusion method, so that on one hand, the current edge concentration effect of a PN junction is eliminated, and the thermal ablation resistance of the device is improved; on the other hand, the junction surface appearance of the PN junction is shaped, so that the breakdown voltage of the PN junction is greatly improved, and the aim of improving the strong electromagnetic pulse resistance of the device is fulfilled.
The invention is described in further detail below with reference to the accompanying drawings: the process method is adopted to complete the development of the TVS device, and the developed device passes a strong electromagnetic pulse environment test, and the process method specifically comprises the following steps:
1. high current pulse test
The research device carries out a current pulse test according to the requirement of a strong electromagnetic pulse test, the current pulse is a double-exponential pulse, a typical waveform is shown in figure 2, and the current fluence reaches 120A; the device has normal function after passing through strong current pulse, the main parameter index transformation quantity of the device is very small, and the test data is shown in table 1:
TABLE 1 comparison table of device parameters before and after strong current pulse
2. High voltage pulse test
The developed device carries out a voltage pulse test according to the requirements of a strong electromagnetic pulse test, the voltage pulse is in a contact discharge mode, the voltage is impacted for 20 times, the interval of each time is 1 second, and the impact voltage is 20 KV. The device has normal function after strong voltage pulse, the main parameter index transformation quantity of the device is very small, and the test data is shown in table 2:
TABLE 2 comparison table of device parameters before and after strong voltage pulse
A strong electromagnetic pulse test is also carried out on the conventional TVS device which does not adopt the process method, the current pulse resistance of the device is 30A, the voltage pulse resistance of the device is 4000V, and the comparison shows that the strong electromagnetic pulse resistance of the device adopting the process method is greatly improved, and the performance is stable and reliable.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (6)
1. The anti-electromagnetic pulse protection ring around the PN junction is characterized in that the junction depth of the protection ring is larger than that of the PN junction.
2. The electromagnetic pulse resistance guard ring around a PN junction of claim 1, wherein the guard ring is obtained by impurity diffusion of iiia element.
3. A manufacturing method of an anti-electromagnetic pulse protection ring around a PN junction is characterized by comprising the following steps:
1) oxidizing the silicon material, and carrying out protective ring photoetching according to a design layout;
2) injecting IIIA group elements into the photoetching area for doping;
the doping concentration of the element is 1 x 1016～5×1016cm-3；
3) Performing impurity diffusion at 1150-1180 ℃ to form an initial protection ring;
4) injecting a P region, and injecting the element again for doping after the P region is injected;
performing secondary diffusion on the doping element at 1100-1150 ℃ to form a protective ring through the secondary diffusion; the guard ring junction depth is greater than the PN junction depth.
4. The method of manufacturing a PN junction perimeter anti-electromagnetic pulse guard ring of claim 3, wherein said initial guard ring junction depth is equal to a PN junction depth.
5. The method for manufacturing the anti-electromagnetic pulse protection ring around the PN junction according to claim 3, wherein the injection element in the step 2) and the step 4) is boron.
6. The method for manufacturing the anti-electromagnetic pulse protection ring around the PN junction according to claim 3, wherein the implantation element in the step 2) and the step 4) is indium.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010067670.0A CN111261614A (en) | 2020-01-20 | 2020-01-20 | Anti-electromagnetic pulse protection ring around PN junction and manufacturing method thereof |
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| CN202010067670.0A CN111261614A (en) | 2020-01-20 | 2020-01-20 | Anti-electromagnetic pulse protection ring around PN junction and manufacturing method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522136A (en) * | 2011-12-23 | 2012-06-27 | 南京航空航天大学 | Epitaxial silicon-based PIN node micro isotope battery and preparation method thereof |
| KR20140028319A (en) * | 2012-08-28 | 2014-03-10 | 주식회사 시지트로닉스 | Structure and fabrication method of high-voltage ufred |
| CN105185698A (en) * | 2015-08-11 | 2015-12-23 | 上海华虹宏力半导体制造有限公司 | Method of reducing source drain breakdown voltage creep deformation of channel power device |
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2020
- 2020-01-20 CN CN202010067670.0A patent/CN111261614A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522136A (en) * | 2011-12-23 | 2012-06-27 | 南京航空航天大学 | Epitaxial silicon-based PIN node micro isotope battery and preparation method thereof |
| KR20140028319A (en) * | 2012-08-28 | 2014-03-10 | 주식회사 시지트로닉스 | Structure and fabrication method of high-voltage ufred |
| CN105185698A (en) * | 2015-08-11 | 2015-12-23 | 上海华虹宏力半导体制造有限公司 | Method of reducing source drain breakdown voltage creep deformation of channel power device |
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Application publication date: 20200609 |