CN111211158B - 二极管制造方法 - Google Patents
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Abstract
本发明涉及一种二极管制造方法，其包括：(1)依序沉积磊晶层和氧化结构于基板上。(2)利用氧化结构的设置，蚀刻磊晶层而形成多个主动沟槽和终止沟槽，终止沟槽具有第一侧壁、第二侧壁以及底部。(3)执行热氧化程序，以沉积沟槽氧化层覆盖各主动沟槽的侧壁及底部、第一侧壁、第二侧壁以及底部。(4)沉积半导体层于各主动沟槽、第一侧壁以及第二侧壁，从而将半导体层填充于各主动沟槽及覆盖第一侧壁以及第二侧壁。(5)沉积金属硅化层于各主动沟槽上，且金属硅化层部分覆盖第一侧壁及第二侧壁的半导体层。本发明相对于现有技术少了绝缘层设置的程序即完成二极管的制造，达到简化二极管的制造程序以及降低制造成本的目的。
Description
技术领域
本发明涉及一种半导体制造方法，尤其是一种具有简化制造流程之优点的二极管制造方法。
背景技术
随着电子技术的进步以及电子产品的小型化趋势，越来越多电子组件利用集成电路制程的方式生产，然而，集成电路型式的电子组件需考虑许多层面，例如耐压、相互干扰或抗噪声之类的问题。
其中，二极管在电路中扮演相当重要的角色，因为二极管具备顺向导通及逆向截止的特性，往往因为二极管的设计所需，导致二极管的制造方法过于繁琐，如何解决前述症结点，遂成为待解决的问题。
综观前所述，本发明之发明者思索并设计一种二极管制造方法，以期针对现有技术之缺失加以改善，进而增进产业上的实施利用。
发明内容
本发明的目的是针对现有技术的不足，提供一种二极管制造方法，用以解决当前半导体制造业所面临的问题。
本发明的技术方案是：
一种二极管制造方法，其包括：
沉积磊晶层于基板上；
沉积氧化结构于磊晶层上；
利用氧化结构的设置，蚀刻磊晶层而形成多个主动沟槽和终止沟槽，终止沟槽具有第一侧壁、第二侧壁以及底部；
执行热氧化程序，以沉积沟槽氧化层覆盖各主动沟槽的侧壁及底部、第一侧壁、第二侧壁以及底部；
沉积半导体层于各主动沟槽、第一侧壁以及第二侧壁，从而将半导体层填充于各主动沟槽及覆盖第一侧壁以及第二侧壁；以及
沉积金属硅化层于各主动沟槽上，且金属硅化层覆盖第一侧壁及第二侧壁的半导体层。
较佳的，还包括界定多个主动沟槽为主动区，第一侧壁靠近主动区，第二侧壁远离主动区。
较佳的，还包括沉积金属电极于各主动沟槽的金属硅化层上，且金属电极部分覆盖第一侧壁及第二侧壁的金属硅化层。
较佳的，还包括沉积背电极于基板下。
较佳的，氧化结构由多个氧化屏蔽组成。
较佳的，终止沟槽的宽度大于各主动沟槽的宽度。
本发明的有益效果：
本发明的二极管制造方法，相对于现有技术少了绝缘层设置的程序即完成二极管的制造，达到简化二极管的制造程序以及降低制造成本的目的。
附图说明
图1是本发明的流程图。
其中：10-基板；20-磊晶层；30-氧化结构；31-氧化屏蔽；40-主动沟槽；41-沟槽氧化层；42-半导体层；50-终止沟槽；60-金属硅化层；70-金属电极；80-背电极；BTM-底部；S1-第一侧壁；S2-第二侧壁；W1-主动沟槽的宽度；W2-终止沟槽的宽度。
具体实施方式
下面结合附图和实施例对本发明作进一步的说明。
本发明可以不同形式来实现，故不应被理解仅限于此处所陈述的实施例，相反地，对所属技术领域具有通常知识者而言，所提供的实施例将使本揭露更加透彻与全面且完整地传达本发明的范畴，且本发明将仅为所附加的申请专利范围所定义。
如图1所示，一种二极管制造方法，其包括: (1)S11步骤：依序沉积磊晶层20和氧化结构30于基板10上，其中，氧化结构30由多个氧化屏蔽31组成，氧化结构30的设置可透过曝光显影和光罩设置来完成，根据二极管设计的不同，各氧化屏蔽31的间距也有所不同，于此，可以不加以限定氧化屏蔽31的数目和其间距。(2)S12步骤：利用氧化结构30的设置，决定多个主动沟槽40和终止沟槽50的位置，并界定多个主动沟槽40为主动区及终止沟槽50为终止区，据此进行蚀刻磊晶层20而形成多个主动沟槽40和终止沟槽50，终止沟槽50具有第一侧壁S1、第二侧壁S2以及底部BTM，第一侧壁S1靠近主动区，第二侧壁S2远离主动区，其中，终止沟槽50的宽度W2大于各主动沟槽40的宽度W1；接续执行热氧化程序，以沉积沟槽氧化层41覆盖各主动沟槽40的侧壁及底部、第一侧壁S1、第二侧壁S2以及底部BTM。(3)S13步骤：沉积半导体层42于各主动沟槽40、第一侧壁S1以及第二侧壁S2，从而将半导体层42填充于各主动沟槽40及覆盖第一侧壁S1以及第二侧壁S2。(4)S14步骤：沉积金属硅化层60于各主动沟槽40上，且金属硅化层60部分覆盖第一侧壁S1及第二侧壁S2的半导体层42。(5)S15步骤：沉积金属电极70于各主动沟槽40的金属硅化层60上，且金属电极70部分覆盖第一侧壁S1及第二侧壁S2的金属硅化层60，并沉积背电极80于基板10下。本发明的二极管制造方法，相对于现有技术少了绝缘层设置的程序即完成二极管的制造，达到简化二极管的制造程序以及降低制造成本的目的。
需说明的是，金属电极70和背电极80的沉积也可透过无电电镀达成，具体而言，由于终止沟槽50的沟槽氧化层41的设置，沟槽氧化层41的导电性差，金属硅化层60的导电性相对较高，因此，透过无电电镀的方法，金属电极70选择性沉积主动沟槽40的金属硅化层60上而非沉积于沟槽氧化层41上，背电极80沉积于基板10下。
此外，对于透过本发明的方法所制造的二极管可设定如下：在此实施例中，基板10为硅基板，磊晶层20可为n型或 p型，n型和p型的达成则为在半导体材料掺入杂质，而半导体材料为硅及杂质为第三族元素或第五族元素，掺入杂质则可透过离子布值或固体扩散源或液体扩散源在高温下扩散杂质于半导体材料的方式达成；半导体层42的材料包括多晶硅；沟槽氧化层41和多个氧化屏蔽31的材料包括二氧化硅(SiO2)；金属硅化层60由金属硅化物组成；金属硅化层60的金属材料、金属电极70和背电极80的材料包括铟(In)、锡(Sn)、铝(Al)、金(Au)、铂(Pt)、铟(In)、锌(Zn)、锗(Ge)、银(Ag)、铅(Pb)、钯(Pd)、铜(Cu)、铍化金(AuBe)、铍化锗(BeGe)、镍(Ni)、锡化铅(PbSn)、铬(Cr)、锌化金(AuZn)、钛(Ti)、钨(W)以及钨化钛(TiW)等所组成材料中至少一种。
综上所述，本发明之二极管制造方法，相对于现有技术，少了绝缘层设置的程序即完成二极管的制造，达到简化二极管的制造程序以及降低制造成本的目的，从而可将本发明的方法应用于半导体的制造业。
本发明未涉及部分均与现有技术相同或可采用现有技术加以实现。
Claims (5)
1.一种二极管制造方法，其特征在于，其包括：
沉积磊晶层于基板上；
沉积氧化结构于所述磊晶层上；
利用所述氧化结构的设置，蚀刻所述磊晶层而形成多个主动沟槽和终止沟槽，所述终止沟槽具有第一侧壁、第二侧壁以及底部；
执行热氧化程序，以沉积沟槽氧化层覆盖各所述主动沟槽的侧壁及底部、所述第一侧壁、所述第二侧壁以及所述底部；
沉积半导体层于各所述主动沟槽、所述第一侧壁以及所述第二侧壁，从而将所述半导体层填充于各所述主动沟槽及覆盖所述第一侧壁以及所述第二侧壁；
沉积金属硅化层于各所述主动沟槽上，且所述金属硅化层覆盖所述第一侧壁及所述第二侧壁的所述半导体层；以及
沉积金属电极于各所述主动沟槽的所述金属硅化层上，且所述金属电极部分覆盖所述第一侧壁及所述第二侧壁的所述金属硅化层。
2.根据权利要求1所述的二极管制造方法，其特征是还包括界定所述多个主动沟槽为主动区，所述第一侧壁靠近所述主动区，所述第二侧壁远离所述主动区。
3.根据权利要求1所述的二极管制造方法，其特征是还包括沉积背电极于所述基板下。
4.根据权利要求1所述的二极管制造方法，其特征是所述氧化结构由多个氧化屏蔽组成。
5.根据权利要求1所述的二极管制造方法，其特征是所述终止沟槽的宽度大于各所述主动沟槽的宽度。
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| US (1) | US20200161444A1 (zh) |
| CN (1) | CN111211158B (zh) |
| TW (1) | TWI726260B (zh) |
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| TWI742902B (zh) * | 2020-10-30 | 2021-10-11 | 台灣奈米碳素股份有限公司 | 利用電漿輔助原子層沉積技術製造半導體裝置的方法 |
| TWI784335B (zh) * | 2020-10-30 | 2022-11-21 | 台灣奈米碳素股份有限公司 | 三維半導體二極體裝置的製造方法 |
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| CN105720109A (zh) * | 2014-12-05 | 2016-06-29 | 无锡华润上华半导体有限公司 | 一种沟槽型肖特基势垒二极管及其制备方法 |
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| US7491633B2 (en) * | 2006-06-16 | 2009-02-17 | Chip Integration Tech. Co., Ltd. | High switching speed two mask schottky diode with high field breakdown |
| DE102008045410B4 (de) * | 2007-09-05 | 2019-07-11 | Denso Corporation | Halbleitervorrichtung mit IGBT mit eingebauter Diode und Halbleitervorrichtung mit DMOS mit eingebauter Diode |
| US8653587B2 (en) * | 2012-02-13 | 2014-02-18 | Force Mos Technology Co., Ltd. | Trench MOSFET having a top side drain |
| TWI576920B (zh) * | 2015-11-20 | 2017-04-01 | 敦南科技股份有限公司 | 二極體元件及其製造方法 |
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| CN105720109A (zh) * | 2014-12-05 | 2016-06-29 | 无锡华润上华半导体有限公司 | 一种沟槽型肖特基势垒二极管及其制备方法 |
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| Publication number | Publication date |
|---|---|
| US20200161444A1 (en) | 2020-05-21 |
| TW202020984A (zh) | 2020-06-01 |
| CN111211158A (zh) | 2020-05-29 |
| TWI726260B (zh) | 2021-05-01 |
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