CN111129165B - Schottky diode and preparation method thereof - Google Patents
Schottky diode and preparation method thereof Download PDFInfo
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- CN111129165B CN111129165B CN201911231623.9A CN201911231623A CN111129165B CN 111129165 B CN111129165 B CN 111129165B CN 201911231623 A CN201911231623 A CN 201911231623A CN 111129165 B CN111129165 B CN 111129165B
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- 238000002360 preparation method Methods 0.000 title abstract description 9
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims abstract description 108
- 229910001195 gallium oxide Inorganic materials 0.000 claims abstract description 108
- 229910052751 metal Inorganic materials 0.000 claims abstract description 78
- 239000002184 metal Substances 0.000 claims abstract description 78
- 238000000137 annealing Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 11
- 238000004528 spin coating Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 18
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 description 18
- 239000000463 material Substances 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000000969 carrier Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241001354791 Baliga Species 0.000 description 1
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
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- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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Abstract
The application relates to the field of semiconductors, in particular to a Schottky diode and a preparation method thereof. The schottky diode includes: a substrate; the n-type gallium oxide layer is formed on the substrate, wherein an inclined plane structure is formed on the n-type gallium oxide layer, the outer edge of the inclined plane structure is overlapped with the outer edge of the n-type gallium oxide layer, the thickness of the n-type gallium oxide layer in a corresponding area of the inclined plane structure is increased from the outer edge to the inner edge, and a thermal oxidation treatment area formed by high-temperature annealing treatment of the n-type gallium oxide layer is arranged below the inclined plane structure; an anode metal layer formed on the n-type gallium oxide layer; the projection of the anode metal layer on the n-type gallium oxide layer covers the inner edge of the inclined plane structure, and the horizontal distance between the projected edge and the inner edge of the inclined plane structure is smaller than or equal to a preset distance; and the cathode metal layer is formed on the back surface of the substrate. The structure can improve the breakdown voltage of the device.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a Schottky diode and a preparation method thereof.
Background
Gallium oxide is a wide bandgap semiconductor material, beta-Ga 2 O 3 The forbidden bandwidth is about 4.85eV, the critical breakdown electric field is as high as 8MV/cm, the n-type doping is controllable, the radiation resistance is high, and the melting point is high, so that the method is very suitable for manufacturing high-voltage electronic devices. The application of the device comprises a power electronic device, a radio frequency electronic device, an ultraviolet detector, a gas sensor and the like, and has wide application prospect in the fields of solid-state lighting, communication, consumer electronics, new energy automobiles, smart grids and the like. The gallium oxide has the characteristics of high pressure resistance and the like which are more excellent than the third-generation semiconductor materials such as silicon carbide and the like, the Baliga figure of merit (BFOM) of the gallium oxide is about 4 times higher than that of the gallium nitride and 9 times higher than that of the silicon carbide, and the homogeneous substrate can be processed in a melt mode, so that the gallium oxide has wide application prospect and meets the requirements of national energy conservation and emission reduction, intelligent manufacturing, communication and information safety.
At present, research on gallium oxide is still in a starting stage, and although experiments show that the breakdown electric field test value of a gallium oxide device is already higher than the theoretical value of gallium nitride and silicon carbide, the acceptor level of gallium oxide is deeper, and a hole self-binding effect exists, so that a traditional p-type acceptor element is difficult to dope into gallium oxide to form p-type materials. Under the existing technological conditions, the pn junction realized by using the gallium oxide material is generally accompanied with the problems of high technical difficulty and high cost, which limits the manufacturing of the Schottky diode by using the gallium oxide material to a great extent, namely, the gallium oxide material cannot be used for manufacturing the high-performance Schottky diode, so that the breakdown voltage of the gallium oxide Schottky diode still has a certain gap compared with other third-generation semiconductor devices at present.
Disclosure of Invention
In view of the above, the embodiment of the application provides a schottky diode and a preparation method thereof, so as to improve the breakdown voltage of the schottky diode.
A first aspect of an embodiment of the present application provides a schottky diode, including:
a substrate;
the n-type gallium oxide layer is formed on the substrate, wherein an inclined plane structure is formed on the n-type gallium oxide layer, the outer edge of the inclined plane structure is overlapped with the outer edge of the n-type gallium oxide layer, the thickness of the n-type gallium oxide layer in a corresponding area of the inclined plane structure is increased from the outer edge to the inner edge, and a thermal oxidation treatment area formed by high-temperature annealing treatment of the n-type gallium oxide layer is arranged below the inclined plane structure;
an anode metal layer formed on the n-type gallium oxide layer; the projection of the anode metal layer on the n-type gallium oxide layer covers the inner edge of the inclined plane structure, and the horizontal distance between the projected edge and the inner edge of the inclined plane structure is smaller than or equal to a preset distance;
and the cathode metal layer is formed on the back surface of the substrate.
Optionally, the included angle between the slope in the slope structure and the horizontal direction is smaller than 60 °.
Optionally, a second dielectric layer is disposed above the inclined plane structure.
Optionally, a field plate structure is further arranged above the anode metal layer, wherein the orthographic projection of the field plate structure covers all anode metal layers.
Optionally, a second dielectric layer is filled between the field plate structure and the inclined plane structure for supporting.
A second aspect of the embodiment of the present application provides a method for manufacturing a schottky diode, including:
an n-type gallium oxide layer is epitaxially grown on the substrate;
preparing a first dielectric layer on the n-type gallium oxide layer; the area where the first dielectric layer is located in the area range corresponding to the anode metal layer to be prepared;
preparing a mask layer on the n-type gallium oxide layer with the first dielectric layer; the mask layer is provided with an inclined side wall, and the length of the side wall is greater than or equal to that of an inclined plane structure to be prepared;
dry etching is carried out on the front surface of the device until all mask layers in the region corresponding to the inclined plane to be prepared are removed, and an inclined plane structure is formed on the n-type gallium oxide layer;
removing a mask layer remained on the surface of the device, performing high-temperature annealing treatment on the front surface of the device, and forming a thermal oxidation treatment region in the n-type oxide layer, wherein the thermal oxidation treatment region is a region except for a region corresponding to the first dielectric layer;
removing the first dielectric layer;
preparing an anode metal layer; wherein the horizontal distance between the edge of the anode metal layer and the edge of the first dielectric layer is smaller than or equal to a preset distance;
and preparing a cathode metal layer.
Optionally, the preparing the mask layer on the n-type gallium oxide layer on which the first dielectric layer is prepared includes:
spin-coating photoresist on the n-type gallium oxide layer on which the first dielectric layer is prepared;
baking the device subjected to spin coating of the photoresist to form inclined side walls of the photoresist, wherein the angle between the side walls and the n-type gallium oxide is smaller than 60 degrees.
Optionally, the baking treatment is performed at 110 ℃ for 2 minutes.
Optionally, the performing high-temperature annealing treatment on the front surface of the device includes:
and carrying out high-temperature annealing treatment on the front surface of the device by adopting an annealing mode of first temperature and then second temperature or an annealing mode of first temperature and then first temperature, wherein the first temperature is smaller than the second temperature, the first temperature and the second temperature are both between 200 ℃ and 900 ℃, and the sum of the annealing time corresponding to the first temperature and the annealing time corresponding to the second temperature is between 10 seconds and 30 minutes.
Optionally, after preparing the anode metal layer, the method further comprises:
depositing a second dielectric layer on the front surface of the device;
removing the second dielectric layer of the area where the field plate structure to be prepared is located through dry etching;
preparing a field plate structure, wherein an orthographic projection of the field plate structure covers all anode metal layers.
According to the Schottky diode provided by the embodiment of the application, the n-type gallium oxide layer grown on the substrate is provided with the inclined plane structure, the outer edge of the inclined plane structure is overlapped with the outer edge of the n-type gallium oxide layer, the thickness of the n-type gallium oxide layer in the corresponding area of the inclined plane structure is increased from the outer edge to the inner edge, the anode metal layer is formed on the n-type gallium oxide layer, and the projection of the anode metal layer on the n-type gallium oxide layer covers the inner edge of the inclined plane structure; the arrangement mode can enable the angle formed at the contact end point of the anode metal layer and the n-type gallium oxide layer to be an obtuse angle, so that the strength of a peak electric field is weakened, and the breakdown voltage is improved. Meanwhile, a thermal oxidation treatment area formed by high-temperature annealing treatment of the n-type gallium oxide layer is arranged below the inclined plane structure, so that the concentration of carriers can be greatly reduced, the forward voltage drop and the surface electric field intensity are reduced, and the breakdown voltage is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a schottky diode according to an embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a schottky diode with an included angle between a slope and a horizontal direction smaller than 60 ° in a slope structure according to an embodiment of the present application;
fig. 3 is a schematic cross-sectional structure of a schottky diode with a second dielectric layer disposed above a bevel structure according to an embodiment of the present application;
fig. 4 is a schematic cross-sectional structure of a schottky diode provided with a field plate structure and a second dielectric layer filling according to an embodiment of the present application;
fig. 5 is a schematic flow chart of a method for manufacturing a schottky diode according to an embodiment of the present application;
fig. 6 is a schematic cross-sectional structure of a device provided in an embodiment of the present application after an n-type gallium oxide layer is epitaxially grown on a substrate;
fig. 7 is a schematic cross-sectional structure of a device after a first dielectric layer is formed on the n-type gallium oxide layer according to an embodiment of the present application;
fig. 8 is a schematic cross-sectional structure of a device after a mask layer is formed on an n-type gallium oxide layer on which a first dielectric layer is formed according to an embodiment of the present application;
fig. 9 is a schematic cross-sectional view of a device with a bevel structure formed by an n-type gallium oxide layer according to an embodiment of the application;
fig. 10 is a schematic cross-sectional view of a device after forming a thermal oxidation treatment region in an n-type oxide layer according to an embodiment of the present application;
FIG. 11 is a schematic cross-sectional structure of a device after removing a first dielectric layer according to an embodiment of the present application;
FIG. 12 is a schematic cross-sectional view of a device after preparing an anode metal layer according to an embodiment of the present application;
fig. 13 is a schematic cross-sectional structure of a device after preparing a cathode metal layer according to an embodiment of the present application;
FIG. 14 is a schematic cross-sectional view of a device after depositing a second dielectric layer on the front surface of the device according to an embodiment of the present application;
fig. 15 is a schematic cross-sectional structure of a device provided in an embodiment of the present application after a second dielectric layer in a region where a field plate structure to be fabricated is located is removed by dry etching;
FIG. 16 is a schematic cross-sectional view of a device after fabrication of a field plate structure according to an embodiment of the present application;
fig. 17 is a schematic cross-sectional view of a schottky diode corresponding to fig. 16 after preparing a cathode metal layer according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings in combination with the embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Fig. 1 is a schematic cross-sectional structure of a schottky diode according to an embodiment of the present application, and referring to fig. 1, the schottky diode may include:
a substrate 101.
And an n-type gallium oxide layer 102 formed on the substrate 101, wherein the n-type gallium oxide layer 102 is formed with a bevel structure, the outer edge of the bevel structure is overlapped with the outer edge of the n-type gallium oxide layer, the thickness of the n-type gallium oxide layer 102 in a corresponding area of the bevel structure is increased from the outer edge to the inner edge, and a thermal oxidation treatment area formed by high-temperature annealing the n-type gallium oxide layer is arranged below the bevel structure.
An anode metal layer 105 formed on the n-type gallium oxide layer 102; wherein, the projection of the anode metal layer 105 on the n-type gallium oxide layer 102 covers the inner edge of the inclined plane structure, and the horizontal distance between the projected edge and the inner edge of the inclined plane structure is smaller than or equal to the preset distance.
And a cathode metal layer 106 formed on the back surface of the substrate 101.
Because of the strong spike electric field under the edge of the anode of conventional gallium oxide devices, breakdown of the device tends to occur under the anode. In the embodiment of the present application, the n-type gallium oxide layer 102 has a bevel structure, the anode metal layer 105 is formed on the n-type gallium oxide layer 102, and the end point of the anode metal layer 105 contacting the n-type gallium oxide layer 102 forms an obtuse angle, so that the arrangement can weaken the intensity of the peak electric field, thereby improving the breakdown voltage. Under the bevel structure, a thermal oxidation treatment region, that is, a portion shown by a broken line in fig. 1, is formed by performing a high-temperature annealing treatment on the device in an oxygen-containing atmosphere. After the n-type gallium oxide layer 102 corresponding to the inclined plane structure is subjected to high-temperature annealing treatment, the concentration of carriers is reduced, so that the forward voltage drop is reduced, the surface electric field intensity is reduced, and the breakdown voltage is further improved. In practice, it is very difficult to align the edge of the anode metal layer 105 with the inner edge of the inclined plane structure completely when preparing the anode metal layer 105, and when the projection of the anode metal layer 105 onto the n-type gallium oxide layer 102 is located inside the inner edge of the inclined plane structure, an obtuse angle cannot be formed at the contact point of the anode metal layer 105 and the n-type gallium oxide layer 102. Therefore, the projection of the anode metal layer 105 on the n-type gallium oxide layer 102 covers the inner edge of the inclined plane structure, so that an error space can be reserved for actual manufacturing, the defective rate is reduced, and meanwhile, the horizontal distance between the projected edge and the inner edge of the inclined plane structure is smaller than or equal to a preset distance, so that the structure can play a larger role. In practice, the setting of the preset distance depends on the process level, which in the present embodiment is 50 μm.
In some embodiments, the slope in the ramp structure has an angle of less than 60 ° from horizontal.
In the embodiment of the present application, referring to fig. 2, the included angle between the slope and the horizontal direction in the slope structure is smaller than 60 °, i.e. 0 ° < θ <60 °. When the inclination angle of the inclined plane structure is in the range, the purpose of weakening the strength of the peak electric field can be better achieved, and the breakdown voltage is improved.
In some embodiments, a second dielectric layer is disposed over the bevel structure.
In the embodiment of the present application, referring to fig. 3, the second dielectric layer 107 is disposed above the inclined plane structure, so that the inclined plane structure is prone to generate electric leakage, and the second dielectric layer 107 is grown on the n-type gallium oxide layer 102 corresponding to the inclined plane structure, so as to avoid the occurrence of electric leakage. The shape of the second dielectric layer in fig. 3 is merely illustrative, and in practice, the second dielectric layer may cover the n-type gallium oxide layer corresponding to the inclined plane structure completely.
In some embodiments, a field plate structure is further disposed over the anode metal layer, wherein an orthographic projection of the field plate structure covers all of the anode metal layer.
In some embodiments, the support is filled between the field plate structure and the bevel structure by a second dielectric layer.
In an embodiment of the present application, referring to fig. 4, the anode metal layer 105 may further be provided with a field plate structure 108, where a front projection of the field plate structure 108 covers the entire anode metal layer 105, and the space between the field plate structure and the bevel structure is filled with a support by a second dielectric layer 107. Setting the field plate structure for the anode metal layer 105 can optimize the electric field distribution of the device, so that the electric field distribution below the anode metal layer 105 is more uniform, the peak electric field intensity is further reduced, and the breakdown characteristic is improved.
In some embodiments, the second dielectric layer may be SiN, having a thickness between 50-1000 nm.
In some embodiments, the substrate is an n-type gallium oxide substrate with a doping concentration of greater than or equal to 1.0X10 18 cm -3 . The n-type gallium oxide layer is realized by doping Si or Sn, etc., and the doping concentration is 1.0x10 15 cm -3 Up to 1.0X10 20 cm -3 Between the ranges. The thickness of the n-type gallium oxide layer is 100nm to 50 μm.
In some embodiments, the n-type gallium oxide layer is unevenly doped, and the n-type gallium oxide layer has a multilayer structure with concentration increasing from top to bottom, which is more beneficial to improving the high voltage resistance level of the device.
In some embodiments, the anodic metal layer may be a metal such as Ni/Au or Pt/Au.
In some embodiments, the field plate structure may be Ti/Au or Ti/Al/Ni/Au or other metals.
In some embodiments, the cathode metal layer may be a metal such as Ti/Au or Ti/Al/Ni/Au.
Fig. 5 is a schematic flow chart of a preparation method of a schottky diode according to an embodiment of the present application, and referring to fig. 5, the preparation method of the schottky diode may include:
in step S501, an n-type gallium oxide layer is epitaxially grown on a substrate.
In an embodiment of the present application, referring to fig. 6, the substrate 101 may be an n-type heavily doped gallium oxide substrate. The n-type gallium oxide layer 102 may be implemented by doping Si or Sn, and the thickness of the n-type gallium oxide layer 102 is set according to actual requirements.
Step S502, preparing a first dielectric layer on the n-type gallium oxide layer; the area where the first dielectric layer is located in the area range corresponding to the anode metal layer to be prepared.
In the embodiment of the present application, referring to fig. 7, a first dielectric layer 103 is prepared in a region corresponding to the anode metal layer to be prepared in the subsequent step, and the first dielectric layer is located on the n-type gallium oxide layer 102. During the preparation, a layer of SiO may be deposited on the n-type gallium oxide layer 102 by PECVD 2 The material of the first dielectric layer is 50-1000nm thick, and then the photoresist is used as a mask to make SiO in the area outside the anode pattern 2 And removing by adopting a dry etching/wet etching method or a wet etching method to form the first dielectric layer 103.
Step S503, preparing a mask layer on the n-type gallium oxide layer with the first dielectric layer prepared; the mask layer is provided with an inclined side wall, and the length of the side wall is greater than or equal to that of the inclined plane structure to be prepared.
In an embodiment of the present application, referring to fig. 8, a mask layer 104 having an inclined sidewall is formed on an n-type gallium oxide layer 102 on which a first dielectric layer 103 is formed. Wherein the length of the formed side wall is greater than or equal to the length of the bevel structure to be prepared.
And step S504, carrying out dry etching on the front surface of the device until all mask layers in the region corresponding to the inclined surface to be prepared are removed, and forming an inclined surface structure on the n-type gallium oxide layer.
In the embodiment of the application, referring to fig. 8 and 9 in combination, dry etching is performed on the front surface of the device until the mask layer in the region corresponding to the bevel to be prepared is completely removed, so as to form the device with the bevel structure formed by the n-type gallium oxide layer as shown in fig. 9. Because of the existence of the mask layer 104, during the etching process, the inclined sidewall portion of the mask layer 104 is gradually etched, and the plasma continues to etch the n-type gallium oxide layer 102 under the mask layer 104, so that the n-type gallium oxide layer 102 also forms a bevel structure similar to the inclined sidewall portion of the mask layer 104.
In step S505, the mask layer remaining on the surface of the device is removed, and a thermal oxidation treatment area is formed in the n-type oxide layer by performing a high temperature annealing treatment on the front surface of the device, where the thermal oxidation treatment area is an area other than the area corresponding to the first dielectric layer.
In the embodiment of the present application, referring to fig. 10, if after the n-type gallium oxide layer 102 forms the inclined plane structure, there is a part of mask layer residue, and the mask layer residue on the device surface is removed, so as not to affect the formation of the subsequent thermal oxidation treatment area or the anode metal layer. After the mask layer is removed, the device is subjected to high-temperature annealing treatment in an oxygen atmosphere, and due to the shielding of the first dielectric layer 103, a thermal oxidation treatment region is formed in the n-type gallium oxide layer 102 in a region other than the region corresponding to the first dielectric layer 103, i.e., a thermal oxidation treatment region is formed below the inclined plane structure, as indicated by a dotted line in fig. 10. The concentration of carriers can be reduced by forming a thermal oxidation treatment area under the inclined plane structure, so that the forward voltage drop and the surface electric field intensity are reduced, and the breakdown voltage of the device is further improved.
And step S506, removing the first dielectric layer.
In an embodiment of the present application, referring to fig. 11, the first dielectric layer is removed, and a device structure as shown in fig. 11 is formed.
Step S507, preparing an anode metal layer; the horizontal distance between the edge of the anode metal layer and the edge of the first dielectric layer is smaller than or equal to a preset distance.
In an embodiment of the present application, referring to fig. 12, an anode metal layer 105 is prepared on the front side of the device from which the first dielectric layer is removed. After the preparation is completed, as shown in fig. 12, the contact point between the anode metal layer 105 and the n-type gallium oxide layer 102 forms an obtuse angle, so that the intensity of the peak electric field can be greatly weakened, and the breakdown characteristic of the device is improved. It is very difficult to align the edge of the anode metal layer 105 with the inner edge of the bevel structure completely during the manufacturing process, and when the projection of the anode metal layer 105 onto the n-type gallium oxide layer 102 is located inside the inner edge of the bevel structure, an obtuse angle cannot be formed at the contact point of the anode metal layer 105 and the n-type gallium oxide layer 102. Therefore, the projection of the anode metal layer 105 on the n-type gallium oxide layer 102 covers the inner edge of the inclined plane structure, so that an error space can be reserved for actual manufacturing, the defective rate is reduced, and meanwhile, the horizontal distance between the projected edge and the inner edge of the inclined plane structure is smaller than or equal to a preset distance, so that the structure can play a larger role. In practice, the setting of the preset distance depends on the process level, which in the present embodiment is 50 μm.
In step S508, a cathode metal layer is prepared.
In the embodiment of the present application, referring to fig. 13, a cathode metal layer 106 is prepared on the back of the device by electron beam evaporation or the like, and then the device is placed in N 2 An annealing process is performed in an atmosphere to form an ohmic contact between the cathode metal layer 106 and the substrate 101. In practice, the step of preparing the cathode metal layer may be placed in any of the above steps.
When the schottky diode is manufactured, the first dielectric layer and the mask layer with the inclined side wall are used for shielding, and dry etching is conducted on the front surface of the device, so that the n-type gallium oxide layer forms an inclined surface structure similar to the inclined side wall of the mask layer. The angle formed at the contact end point of the anode metal layer and the inclined plane structure prepared later is an obtuse angle, so that the strength of a peak electric field is greatly reduced, and the breakdown voltage is improved. And meanwhile, before preparing anode metal, carrying out high-temperature annealing treatment on the front surface of the device to form a thermal oxidation treatment area below the inclined plane structure, so that the concentration of carriers is reduced, the forward voltage drop is promoted to be reduced, the surface electric field intensity is further reduced, and the breakdown voltage is improved.
In some embodiments, the preparing a mask layer on the n-type gallium oxide layer on which the first dielectric layer is prepared includes: spin-coating photoresist on the n-type gallium oxide layer on which the first dielectric layer is prepared; baking the device subjected to spin coating of the photoresist to form inclined side walls of the photoresist, wherein the angle between the side walls and the n-type gallium oxide is smaller than 60 degrees.
In the embodiment of the application, when the mask layer is prepared, photoresist can be adopted as the mask layer, photoresist is firstly spin-coated on the n-type gallium oxide layer for preparing the first dielectric layer, and baking treatment is carried out on a device subjected to spin-coating of the photoresist so as to enable the photoresist to form inclined side walls, wherein the angle between the side walls and the n-type gallium oxide layer is smaller than 60 degrees, and particularly, the form of the mask layer 104 in fig. 8 can be referred to, and the angle between the side walls and the n-type gallium oxide layer 102 is smaller than 60 degrees, so that the inclined plane structure prepared in the subsequent step can form a similar inclined angle.
In some embodiments, the baking process is performed at a temperature of 110 ℃ for a period of 2 minutes.
In some embodiments, the performing a high temperature annealing process on the front surface of the device includes: and carrying out high-temperature annealing treatment on the front surface of the device by adopting an annealing mode of first temperature and then second temperature or an annealing mode of first temperature and then first temperature, wherein the first temperature is smaller than the second temperature, the first temperature and the second temperature are both between 200 ℃ and 900 ℃, and the sum of the annealing time corresponding to the first temperature and the annealing time corresponding to the second temperature is between 10 seconds and 30 minutes.
In the embodiment of the present application, when the high temperature annealing treatment is performed on the front surface of the device in step S505, the annealing may be performed by adopting a temperature-changing time-changing annealing manner, specifically, the high temperature annealing treatment may be performed on the front surface of the device by adopting a first temperature-then-second temperature annealing manner or a first temperature-then-first temperature annealing manner, where the first temperature is less than the second temperature, and the first temperature and the second temperature are both between 200 ℃ and 900 ℃, and the sum of the annealing time corresponding to the first temperature and the annealing time corresponding to the second temperature is between 10 seconds and 30 minutes. And annealing is performed at different temperatures and for different times, so that thermal oxidation treatment areas with different ion concentration levels can be formed, and the carrier concentration can be further reduced, thereby improving the breakdown voltage of the device.
In some embodiments, after preparing the anodic metal layer, further comprising: depositing a second dielectric layer on the front surface of the device; removing the second dielectric layer of the area where the field plate structure to be prepared is located through dry etching; preparing a field plate structure, wherein an orthographic projection of the field plate structure covers all anode metal layers.
In the embodiment of the present application, referring to fig. 12 and fig. 14 to 16 in combination, a second dielectric layer is deposited on the front surface of the device shown in fig. 12 by a PECVD method to form the device structure shown in fig. 14, the second dielectric layer 107 in the field plate pattern region is removed by dry etching to form the device structure shown in fig. 15, and a field plate structure is prepared on the anode metal layer 105 to form the device structure shown in fig. 16. The field plate structure 108 is arranged for the anode metal layer 105, so that the electric field distribution of the device can be optimized, the electric field distribution below the anode metal layer 105 is more uniform, the peak electric field intensity is further reduced, and the breakdown characteristic is improved. The device structure shown in fig. 16 is shown in fig. 17 after the cathode metal layer is prepared. The cathode metal layer 106 may be prepared in any one of steps S501 to S507, or in any one of the steps in preparing the field plate structure.
In some embodiments, the n-type gallium oxide layer is unevenly doped, and the n-type gallium oxide layer has a multilayer structure with concentration increasing from top to bottom, which is more beneficial to improving the high voltage resistance level of the device.
In some embodiments, the second dielectric layer may be SiN, having a thickness between 50-1000 nm.
In some embodiments, the substrate is an n-type gallium oxide substrate with a doping concentration of greater than or equal to 1.0X10 18 cm -3 . The n-type gallium oxide layer is realized by doping Si or Sn, etc., and the doping concentration is 1.0x10 15 cm -3 Up to 1.0X10 20 cm -3 Between the ranges. The thickness of the n-type gallium oxide layer is 100nm to 50 μm.
In some embodiments, the anodic metal layer may be a metal such as Ni/Au or Pt/Au.
In some embodiments, the field plate structure may be Ti/Au or Ti/Al/Ni/Au or other metals.
In some embodiments, the cathode metal layer may be a metal such as Ti/Au or Ti/Al/Ni/Au.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (6)
1. A method of manufacturing a schottky diode comprising:
an n-type gallium oxide layer is epitaxially grown on the substrate;
preparing a first dielectric layer on the n-type gallium oxide layer; the area where the first dielectric layer is located in the area range corresponding to the anode metal layer to be prepared;
preparing a mask layer on the n-type gallium oxide layer with the first dielectric layer; the mask layer is provided with an inclined side wall, and the length of the side wall is greater than or equal to that of an inclined plane structure to be prepared;
dry etching is carried out on the front surface of the device until all mask layers in the region corresponding to the inclined plane to be prepared are removed, and an inclined plane structure is formed on the n-type gallium oxide layer; the outer edge of the inclined plane structure is overlapped with the outer edge of the n-type gallium oxide layer, and the thickness of the n-type gallium oxide layer in the corresponding area of the inclined plane structure is increased from the outer edge to the inner edge;
removing a mask layer remained on the surface of the device, performing high-temperature annealing treatment on the front surface of the device, and forming a thermal oxidation treatment region in the n-type oxide layer, wherein the thermal oxidation treatment region is a region except for a region corresponding to the first dielectric layer;
removing the first dielectric layer;
preparing an anode metal layer; wherein the horizontal distance between the edge of the anode metal layer and the edge of the first dielectric layer is smaller than or equal to a preset distance; the projection of the anode metal layer on the n-type gallium oxide layer completely covers the inner edge of the inclined plane structure; the included angle between the inclined surface structure on the n-type gallium oxide layer and the contact end point of the anode metal layer is an obtuse angle; wherein the obtuse angle is greater than 120 °;
and preparing a cathode metal layer.
2. The method of manufacturing a schottky diode of claim 1 wherein said preparing a mask layer on the n-type gallium oxide layer from which the first dielectric layer is prepared comprises:
spin-coating photoresist on the n-type gallium oxide layer on which the first dielectric layer is prepared;
baking the device subjected to spin coating of the photoresist to form inclined side walls of the photoresist, wherein the angle between the side walls and the n-type gallium oxide is smaller than 60 degrees.
3. The method of manufacturing a schottky diode as described in claim 2, wherein the baking process is performed at a temperature of 110 ℃ for 2 minutes.
4. The method of manufacturing a schottky diode of claim 1 wherein said high temperature annealing the front surface of the device comprises:
and carrying out high-temperature annealing treatment on the front surface of the device by adopting an annealing mode of first temperature and then second temperature or an annealing mode of first temperature and then first temperature, wherein the first temperature is smaller than the second temperature, the first temperature and the second temperature are both between 200 ℃ and 900 ℃, and the sum of the annealing time corresponding to the first temperature and the annealing time corresponding to the second temperature is between 10 seconds and 30 minutes.
5. The method of manufacturing a schottky diode of claim 1, further comprising, after the anode metal layer is manufactured:
depositing a second dielectric layer on the front surface of the device;
removing the second dielectric layer of the area where the field plate structure to be prepared is located through dry etching;
preparing a field plate structure, wherein an orthographic projection of the field plate structure covers all anode metal layers.
6. A schottky diode produced by the method of any one of claims 1 to 5.
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