CN111129164B - Schottky diode and preparation method thereof - Google Patents
Schottky diode and preparation method thereof Download PDFInfo
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- CN111129164B CN111129164B CN201911231606.5A CN201911231606A CN111129164B CN 111129164 B CN111129164 B CN 111129164B CN 201911231606 A CN201911231606 A CN 201911231606A CN 111129164 B CN111129164 B CN 111129164B
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- 238000002360 preparation method Methods 0.000 title abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 115
- 239000002184 metal Substances 0.000 claims abstract description 115
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims abstract description 101
- 229910001195 gallium oxide Inorganic materials 0.000 claims abstract description 101
- 238000000137 annealing Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 230000003647 oxidation Effects 0.000 claims abstract description 19
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 19
- 238000001312 dry etching Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
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- 230000015556 catabolic process Effects 0.000 abstract description 19
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 description 21
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000000969 carrier Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000003313 weakening effect Effects 0.000 description 2
- 241001354791 Baliga Species 0.000 description 1
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 1
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- 238000005566 electron beam evaporation Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
The application relates to the field of semiconductors, in particular to a Schottky diode and a preparation method thereof. The preparation method comprises the following steps: an n-type gallium oxide layer is epitaxially grown on the substrate; preparing an anode metal layer on the n-type gallium oxide layer; preparing a mask layer on the n-type gallium oxide layer on which the anode metal layer is prepared; the mask layer is provided with an inclined side wall, and the projection of the upper edge of the side wall on the anode metal layer is positioned in the area of the anode metal layer or coincides with the edge of the anode metal layer; dry etching is carried out on the front surface of the device until a mask layer outside a corresponding area of the anode metal layer is removed, and an inclined plane structure with the inner edge overlapped with the edge of the anode metal layer is formed on the n-type gallium oxide layer; removing the mask layer remained on the surface of the device, performing high-temperature annealing treatment on the front surface of the device, and forming a thermal oxidation treatment area in the n-type oxide layer; and preparing a cathode metal layer. The breakdown voltage of the prepared device can be improved by adopting the preparation method.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a Schottky diode and a preparation method thereof.
Background
Gallium oxide is a wide bandgap semiconductor material, beta-Ga 2 O 3 The forbidden bandwidth is about 4.85eV, the critical breakdown electric field is as high as 8MV/cm, the n-type doping is controllable, the radiation resistance is high, and the melting point is high, so that the method is very suitable for manufacturing high-voltage electronic devices. The application of the device comprises a power electronic device, a radio frequency electronic device, an ultraviolet detector, a gas sensor and the like, and has wide application prospect in the fields of solid-state lighting, communication, consumer electronics, new energy automobiles, smart grids and the like. The gallium oxide has the characteristics of high pressure resistance and the like which are more excellent than the third-generation semiconductor materials such as silicon carbide and the like, the Baliga figure of merit (BFOM) of the gallium oxide is about 4 times higher than that of the gallium nitride and 9 times higher than that of the silicon carbide, and the homogeneous substrate can be processed in a melt mode, so that the gallium oxide has wide application prospect and meets the requirements of national energy conservation and emission reduction, intelligent manufacturing, communication and information safety.
At present, research on gallium oxide is still in a starting stage, and although experiments show that the breakdown electric field test value of a gallium oxide device is already higher than the theoretical value of gallium nitride and silicon carbide, the acceptor level of gallium oxide is deeper, and a hole self-binding effect exists, so that a traditional p-type acceptor element is difficult to dope into gallium oxide to form p-type materials. Under the existing technological conditions, the pn junction realized by using the gallium oxide material is generally accompanied with the problems of high technical difficulty and high cost, which limits the manufacturing of the Schottky diode by using the gallium oxide material to a great extent, and the existing preparation method cannot prepare the high-performance Schottky diode by using the gallium oxide material, so that the breakdown voltage of the gallium oxide Schottky diode still has a certain gap compared with other third-generation semiconductor devices.
Disclosure of Invention
In view of the above, the embodiment of the application provides a schottky diode and a preparation method thereof, so as to improve the breakdown voltage of the schottky diode.
An embodiment of the present application provides a method for manufacturing a schottky diode, including:
an n-type gallium oxide layer is epitaxially grown on the substrate;
preparing an anode metal layer on the n-type gallium oxide layer;
preparing a mask layer on the n-type gallium oxide layer on which the anode metal layer is prepared; the mask layer is provided with an inclined side wall, and the projection of the upper edge of the side wall on the anode metal layer is positioned in the area of the anode metal layer or coincides with the edge of the anode metal layer;
dry etching is carried out on the front surface of the device until a mask layer outside a corresponding area of the anode metal layer is removed, and an inclined plane structure with the inner edge overlapped with the edge of the anode metal layer is formed on the n-type gallium oxide layer;
removing a mask layer remained on the surface of the device, performing high-temperature annealing treatment on the front surface of the device, and forming a thermal oxidation treatment region in the n-type oxide layer, wherein the thermal oxidation treatment region is a region except a region corresponding to the anode metal layer;
and preparing a cathode metal layer.
Optionally, preparing the mask layer on the n-type gallium oxide layer on which the anode metal layer is prepared includes:
spin-coating photoresist on the n-type gallium oxide layer on which the anode metal layer is prepared;
and baking the device subjected to photoresist spin coating to form inclined side walls of the photoresist, wherein the angle between the side walls and the n-type gallium oxide layer is smaller than 60 degrees.
Optionally, the baking treatment is performed at 110 ℃ for 2 minutes.
Optionally, the performing high-temperature annealing treatment on the front surface of the device includes:
and carrying out high-temperature annealing treatment on the front surface of the device by adopting an annealing mode of first temperature and then second temperature or an annealing mode of first temperature and then first temperature, wherein the first temperature is smaller than the second temperature, the first temperature and the second temperature are both between 200 ℃ and 900 ℃, and the annealing time corresponding to the first temperature and the annealing time corresponding to the second temperature are both between 10 seconds and 30 minutes.
Optionally, after the high-temperature annealing treatment is performed on the front surface of the device, the method further includes:
depositing a dielectric layer on the front surface of the device;
removing the dielectric layer of the area where the field plate structure to be prepared is located through dry etching;
preparing a field plate structure, wherein an orthographic projection of the field plate structure covers all anode metal layers.
A second aspect of an embodiment of the present application provides a schottky diode, including:
a substrate;
an n-type gallium oxide layer formed on the substrate, wherein the n-type gallium oxide layer is formed with a bevel structure, the outer edge of the bevel structure is overlapped with the outer edge of the n-type gallium oxide layer, the thickness of the n-type gallium oxide layer in a corresponding area of the bevel structure is increased from the outer edge to the inner edge, and a thermal oxidation treatment area formed by high-temperature annealing treatment of the n-type gallium oxide is arranged below the bevel structure;
an anode metal layer formed on the n-type gallium oxide layer; wherein the projected edge of the anode metal layer on the n-type gallium oxide layer coincides with the inner edge of the inclined plane structure;
and a cathode metal layer formed on the back surface of the substrate.
Optionally, an included angle between the slope in the slope structure and the horizontal direction is smaller than 60 DEG
Optionally, a dielectric layer is disposed above the inclined plane structure.
Optionally, a field plate structure is further arranged above the anode metal layer, wherein the orthographic projection of the field plate structure covers all anode metal layers.
Optionally, a dielectric layer is filled between the field plate structure and the inclined plane structure for supporting.
The embodiment of the application provides a method for manufacturing a Schottky diode, which comprises the steps of firstly preparing an anode metal layer on an n-type gallium oxide layer after growing the n-type gallium oxide layer on a substrate, then preparing a mask layer with an inclined side wall on the n-type gallium oxide layer of the anode metal layer, and then carrying out dry etching on the front surface of the device. The angle formed at the contact end point of the anode metal layer and the inclined plane structure is an obtuse angle, so that the intensity of a peak electric field can be greatly reduced, and the breakdown voltage is improved. And the anode metal layer is prepared and then etched, so that the inclined plane structure and the anode metal layer can be completely aligned after etching, and the strength of the peak electric field is further reduced. Meanwhile, after the inclined plane structure is formed, the front surface of the device is subjected to high-temperature annealing treatment, so that a thermal oxidation treatment area is formed below the inclined plane structure, the concentration of carriers is reduced, forward voltage drop is promoted to be reduced, the surface electric field intensity is further reduced, and the breakdown voltage is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a schottky diode according to an embodiment of the present application;
fig. 2 is a schematic cross-sectional structure of a device provided in an embodiment of the present application after an n-type gallium oxide layer is epitaxially grown on a substrate;
fig. 3 is a schematic cross-sectional structure of a device provided by an embodiment of the present application after an anode metal layer is prepared on the n-type gallium oxide layer;
fig. 4 is a schematic cross-sectional structure of a device provided in an embodiment of the present application after a mask layer is formed on an n-type gallium oxide layer on which an anode metal layer is formed;
fig. 5 is a schematic cross-sectional structure of a device provided in an embodiment of the present application after an n-type gallium oxide layer forms a bevel structure;
fig. 6 is a schematic cross-sectional structure of a device after forming a thermal oxidation treatment region in an n-type oxide layer according to an embodiment of the present application;
fig. 7 is a schematic cross-sectional structure of a device after preparing a cathode metal layer according to an embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of a device after a dielectric layer is deposited on the front surface of the device according to an embodiment of the present application;
fig. 9 is a schematic cross-sectional structure of a device provided in an embodiment of the present application after a dielectric layer in a region where a field plate structure to be fabricated is located is removed by dry etching;
FIG. 10 is a schematic cross-sectional view of a device after fabrication of a field plate structure according to an embodiment of the present application;
fig. 11 is a schematic cross-sectional structure of a schottky diode corresponding to fig. 10 after a cathode metal layer is prepared according to an embodiment of the present application;
fig. 12 is a schematic cross-sectional view of a schottky diode according to an embodiment of the present application;
fig. 13 is a schematic cross-sectional view of a schottky diode with an included angle between a slope and a horizontal direction smaller than 60 ° in a slope structure according to an embodiment of the present application;
fig. 14 is a schematic cross-sectional view of a schottky diode with a dielectric layer disposed over a bevel structure according to an embodiment of the present application;
fig. 15 is a schematic cross-sectional structure of a schottky diode with field plate structure and dielectric layer filling according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings in combination with the embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Fig. 1 is a schematic flow chart of a preparation method of a schottky diode according to an embodiment of the present application, and referring to fig. 5, the preparation method of the schottky diode may include:
step S101, an n-type gallium oxide layer is epitaxially grown on the substrate.
In an embodiment of the present application, referring to fig. 2, the substrate 101 may be an n-type heavily doped gallium oxide substrate. The n-type gallium oxide layer 102 may be implemented by doping Si or Sn, and the thickness of the n-type gallium oxide layer 102 is set according to actual requirements.
And step S102, preparing an anode metal layer on the n-type gallium oxide layer.
In an embodiment of the present application, referring to fig. 3, an anode metal layer 105 is prepared on the n-type gallium oxide layer 102, so as to form a device structure as shown in fig. 3.
Step S103, preparing a mask layer on the n-type gallium oxide layer with the anode metal layer prepared; the mask layer is provided with an inclined side wall, and the projection of the upper edge of the side wall on the anode metal layer is positioned in the area of the anode metal layer or coincides with the edge of the anode metal layer.
In an embodiment of the present application, referring to fig. 4, a mask layer 104 having an inclined sidewall is prepared on an n-type gallium oxide layer 102 on which an anode metal layer 105 is prepared. Wherein the projection of the upper edge of the formed sidewall onto the anode metal layer 105 is located in the area of the anode metal layer 105 or coincides with the edge of the anode metal layer 105.
And step S104, carrying out dry etching on the front surface of the device until the mask layer outside the corresponding area of the anode metal layer is removed, and forming an inclined plane structure with the inner edge overlapped with the edge of the anode metal layer on the n-type gallium oxide layer.
In the embodiment of the present application, referring to fig. 4 and 5 in combination, dry etching is performed on the front surface of the device until the mask layer outside the corresponding area of the anode metal layer 105 is removed, so as to form a device with an n-type gallium oxide layer forming an inclined plane structure as shown in fig. 5. Because of the existence of the mask layer 104, during the etching process, the inclined sidewall portion of the mask layer 104 is gradually etched, and the plasma continues to etch the n-type gallium oxide layer 102 under the mask layer 104, so that the n-type gallium oxide layer 102 also forms a bevel structure similar to the inclined sidewall portion of the mask layer 104. In the formed device, the contact point of the anode metal layer 105 and the n-type gallium oxide layer 102 forms an obtuse angle, so that the intensity of a peak electric field can be greatly weakened, and the breakdown characteristic of the device is improved. In practice, the metal electrode is generally manufactured in the final step, in which case it is very difficult to align the anode metal layer to be manufactured later and the bevel structure to be manufactured earlier, and when the projection of the anode metal layer 105 onto the n-type gallium oxide layer 102 is located inside the inner edge of the bevel structure, an obtuse angle cannot be formed at the contact point between the anode metal layer 105 and the n-type gallium oxide layer 102. In the embodiment of the application, the anode metal layer 105 is prepared first and then etched, so that the edge of the anode metal layer 105 and the inner edge of the formed inclined plane structure are completely aligned, the process steps are simplified, and the capability of weakening the peak electric field is further improved.
Step S105, removing the mask layer remained on the surface of the device, performing high-temperature annealing treatment on the front surface of the device, and forming a thermal oxidation treatment region in the n-type oxide layer, wherein the thermal oxidation treatment region is a region except for a region corresponding to the anode metal layer.
In the embodiment of the present application, referring to fig. 6, after forming the n-type gallium oxide layer 102 by dry etching to form the inclined plane structure, there may be a portion of mask layer residue, such as carbonized residue when the mask layer is photoresist, and the mask layer remaining on the surface of the device is removed, so as not to affect the formation of the subsequent thermal oxidation treatment region. After the mask layer is removed, the device is subjected to high-temperature annealing treatment in an oxygen atmosphere, and due to the shielding of the anode metal layer 105, a thermal oxidation treatment region is formed in the n-type gallium oxide layer 102 except for the region corresponding to the anode metal layer 105, i.e., a thermal oxidation treatment region is formed below the inclined plane structure, as indicated by a dotted line in fig. 10. The concentration of carriers can be reduced by forming a thermal oxidation treatment area under the inclined plane structure, so that the forward voltage drop and the surface electric field intensity are reduced, and the breakdown voltage of the device is further improved.
Step S106, preparing a cathode metal layer.
In the embodiment of the present application, referring to fig. 7, a cathode metal layer 106 is prepared on the back of the device by electron beam evaporation or the like, and then the device is placed in N 2 An annealing process is performed in an atmosphere to form an ohmic contact between the cathode metal layer 106 and the substrate 101. In actual operationThe step of preparing the cathode metal layer may be placed in any of the above steps.
When the schottky diode is manufactured, the positive surface of the device is etched by using the shielding of the anode metal layer and the mask layer with the inclined side wall, so that an inclined surface structure similar to the inclined side wall of the mask layer is formed on the n-type gallium oxide layer, and the edge of the inclined surface structure is completely aligned with the edge of the anode metal layer. The angle formed at the contact end point of the anode metal layer and the inclined plane structure is an obtuse angle, so that the strength of a peak electric field is greatly reduced, and the breakdown voltage is improved. Meanwhile, after the inclined plane structure is formed, the front surface of the device is subjected to high-temperature annealing treatment, so that a thermal oxidation treatment area is formed below the inclined plane structure, the concentration of carriers is reduced, forward voltage drop is promoted to be reduced, the surface electric field intensity is further reduced, and the breakdown voltage is improved.
In some embodiments, the preparing a mask layer on the n-type gallium oxide layer on which the anode metal layer is prepared includes: spin-coating photoresist on the n-type gallium oxide layer on which the anode metal layer is prepared; and baking the device subjected to photoresist spin coating to form inclined side walls of the photoresist, wherein the angle between the side walls and the n-type gallium oxide layer is smaller than 60 degrees.
In the embodiment of the application, when the mask layer is prepared, photoresist can be adopted as the mask layer, photoresist is firstly spin-coated on the n-type gallium oxide layer on which the anode metal layer is prepared, and baking treatment is carried out on a device subjected to spin-coating of the photoresist so as to enable the photoresist to form inclined side walls, wherein the angle between the side walls and the n-type gallium oxide layer is smaller than 60 degrees, and particularly, the form of the mask layer 104 in fig. 4 can be referred to, and the angle between the side walls and the n-type gallium oxide layer 102 is smaller than 60 degrees, so that the inclined plane structure prepared in the subsequent step can form a similar inclined angle.
In some embodiments, the baking process is performed at a temperature of 110 ℃ for a period of 2 minutes.
In some embodiments, the performing a high temperature annealing process on the front surface of the device includes: and carrying out high-temperature annealing treatment on the front surface of the device by adopting an annealing mode of first temperature and then second temperature or an annealing mode of first temperature and then first temperature, wherein the first temperature is smaller than the second temperature, the first temperature and the second temperature are both between 200 ℃ and 900 ℃, and the sum of the annealing time corresponding to the first temperature and the annealing time corresponding to the second temperature is between 10 seconds and 30 minutes.
In the embodiment of the present application, when the high temperature annealing treatment is performed on the front surface of the device in step S105, the annealing may be performed by adopting a temperature-changing time-changing annealing manner, specifically, the high temperature annealing treatment may be performed on the front surface of the device by adopting a first temperature-then-second temperature annealing manner or a first temperature-then-first temperature annealing manner, where the first temperature is less than the second temperature, and the first temperature and the second temperature are both between 200 ℃ and 900 ℃, and the sum of the annealing time corresponding to the first temperature and the annealing time corresponding to the second temperature is between 10 seconds and 30 minutes. And annealing is performed at different temperatures and for different times, so that thermal oxidation treatment areas with different ion concentration levels can be formed, and the carrier concentration can be further reduced, thereby improving the breakdown voltage of the device.
In some embodiments, after the high temperature annealing treatment is performed on the front surface of the device, the method further includes: depositing a dielectric layer on the front surface of the device; removing the dielectric layer of the area where the field plate structure to be prepared is located through dry etching; preparing a field plate structure, wherein an orthographic projection of the field plate structure covers all anode metal layers.
In the embodiment of the present application, referring to fig. 6 and fig. 8 to 10 in combination, a dielectric layer is deposited on the front surface of the device shown in fig. 6 by a PECVD method to form the device structure shown in fig. 8, the dielectric layer 107 in the field plate pattern region is removed by dry etching to form the device structure shown in fig. 9, and a field plate structure is prepared on the anode metal layer 105 to form the device structure shown in fig. 10. The field plate structure 108 is arranged for the anode metal layer 105, so that the electric field distribution of the device can be optimized, the electric field distribution below the anode metal layer 105 is more uniform, the peak electric field intensity is further reduced, and the breakdown characteristic is improved. The device structure shown in fig. 10 is shown in fig. 11 after the cathode metal layer is prepared. The cathode metal layer 106 may be prepared in any one of steps S101 to S105, or in any one of steps in preparing the field plate structure.
In some embodiments, the n-type gallium oxide layer is unevenly doped, and the n-type gallium oxide layer has a multilayer structure with concentration increasing from top to bottom, which is more beneficial to improving the high voltage resistance level of the device.
In some embodiments, the dielectric layer may be SiN, having a thickness between 50-1000 nm.
In some embodiments, the substrate is an n-type gallium oxide substrate with a doping concentration of greater than or equal to 1.0X10 18 cm -3 . The n-type gallium oxide layer is realized by doping Si or Sn, etc., and the doping concentration is 1.0x10 15 cm -3 Up to 1.0X10 20 cm -3 Between the ranges. The thickness of the n-type gallium oxide layer is 100nm to 50 μm.
In some embodiments, the anodic metal layer may be a metal such as Ni/Au or Pt/Au.
In some embodiments, the field plate structure may be Ti/Au or Ti/Al/Ni/Au or other metals.
In some embodiments, the cathode metal layer may be a metal such as Ti/Au or Ti/Al/Ni/Au.
Fig. 12 is a schematic cross-sectional structure of a schottky diode according to an embodiment of the present application, and referring to fig. 12, the schottky diode may include:
a substrate 101.
And an n-type gallium oxide layer 102 formed on the substrate 101, wherein the n-type gallium oxide layer 102 is formed with a bevel structure, the outer edge of the bevel structure is overlapped with the outer edge of the n-type gallium oxide layer, the thickness of the n-type gallium oxide layer 102 in a corresponding area of the bevel structure is increased from the outer edge to the inner edge, and a thermal oxidation treatment area formed by high-temperature annealing the n-type gallium oxide layer is arranged below the bevel structure.
An anode metal layer 105 formed on the n-type gallium oxide layer 102; wherein the projected edge of the anode metal layer 105 on the n-type gallium oxide layer 102 coincides with the inner edge of the bevel structure.
And a cathode metal layer 106 formed on the back surface of the substrate 101.
Because of the strong spike electric field under the edge of the anode of conventional gallium oxide devices, breakdown of the device tends to occur under the anode. In the embodiment of the present application, the n-type gallium oxide layer 102 has a bevel structure, the anode metal layer 105 is formed on the n-type gallium oxide layer 102, and the end point of the anode metal layer 105 contacting the n-type gallium oxide layer 102 forms an obtuse angle, so that the arrangement can weaken the intensity of the peak electric field, thereby improving the breakdown voltage. The edges of the anode metal layer 105 are perfectly aligned with the inner edges of the bevel structure, which can optimize the electric field under the anode metal layer 105, further improving the breakdown voltage. Under the bevel structure, a thermal oxidation treatment region, which is a portion shown by a broken line in fig. 12, is formed by performing a high-temperature annealing treatment on the device in an oxygen-containing atmosphere. After the n-type gallium oxide layer 102 corresponding to the inclined plane structure is subjected to high-temperature annealing treatment, the concentration of carriers is reduced, so that the forward voltage drop is reduced, the surface electric field intensity is reduced, and the breakdown voltage is further improved.
In some embodiments, the slope in the ramp structure has an angle of less than 60 ° from horizontal.
In the embodiment of the present application, referring to fig. 13, the included angle between the slope and the horizontal direction in the slope structure is smaller than 60 °, that is, 0 ° < θ <60 °. When the inclination angle of the inclined plane structure is in the range, the purpose of weakening the strength of the peak electric field can be better achieved, and the breakdown voltage is improved.
In some embodiments, a dielectric layer is disposed over the bevel structure.
In the embodiment of the present application, referring to fig. 14, a dielectric layer 107 is disposed above the inclined plane structure, so that the inclined plane structure is prone to leakage, and the dielectric layer 107 is deposited on the n-type gallium oxide layer 102 corresponding to the inclined plane structure, so as to avoid the leakage phenomenon. The shape of the dielectric layer in fig. 14 is merely illustrative, and in practice, the dielectric layer may cover the n-type gallium oxide layer corresponding to the inclined plane structure completely.
In some embodiments, a field plate structure is further disposed over the anode metal layer, wherein an orthographic projection of the field plate structure covers all of the anode metal layer.
In some embodiments, the field plate structure and the bevel structure are supported by dielectric layer filling.
In an embodiment of the present application, referring to fig. 15, the anode metal layer 105 may further be provided with a field plate structure 108, where a front projection of the field plate structure 108 covers the entire anode metal layer 105, and the space between the field plate structure and the bevel structure is filled with a support by a dielectric layer 107. Setting the field plate structure for the anode metal layer 105 can optimize the electric field distribution of the device, so that the electric field distribution below the anode metal layer 105 is more uniform, the peak electric field intensity is further reduced, and the breakdown characteristic is improved.
In some embodiments, the dielectric layer may be SiN, having a thickness between 50-1000 nm.
In some embodiments, the substrate is an n-type gallium oxide substrate with a doping concentration of greater than or equal to 1.0X10 18 cm -3 . The n-type gallium oxide layer is realized by doping Si or Sn, etc., and the doping concentration is 1.0x10 15 cm -3 Up to 1.0X10 20 cm -3 Between the ranges. The thickness of the n-type gallium oxide layer is 100nm to 50 μm.
In some embodiments, the n-type gallium oxide layer is unevenly doped, and the n-type gallium oxide layer has a multilayer structure with concentration increasing from top to bottom, which is more beneficial to improving the high voltage resistance level of the device.
In some embodiments, the anodic metal layer may be a metal such as Ni/Au or Pt/Au.
In some embodiments, the field plate structure may be Ti/Au or Ti/Al/Ni/Au or other metals.
In some embodiments, the cathode metal layer may be a metal such as Ti/Au or Ti/Al/Ni/Au.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. A method of manufacturing a schottky diode comprising:
an n-type gallium oxide layer is epitaxially grown on the substrate;
preparing an anode metal layer on the n-type gallium oxide layer;
preparing a mask layer on the n-type gallium oxide layer on which the anode metal layer is prepared; the mask layer is provided with an inclined side wall, and the projection of the upper edge of the side wall on the anode metal layer is positioned in the area of the anode metal layer or coincides with the edge of the anode metal layer;
dry etching is carried out on the front surface of the device until a mask layer outside a corresponding area of the anode metal layer is removed, and an inclined plane structure with the inner edge overlapped with the edge of the anode metal layer is formed on the n-type gallium oxide layer; the included angle between the plane where the inclined plane structure is positioned and the contact surface is an obtuse angle; the contact surface is the surface of the anode metal layer, which is contacted with the n-type gallium oxide layer;
removing a mask layer remained on the surface of the device, performing high-temperature annealing treatment on the front surface of the device, and forming a thermal oxidation treatment region in the n-type oxide layer, wherein the thermal oxidation treatment region is a region except a region corresponding to the anode metal layer;
and preparing a cathode metal layer.
2. The method of fabricating a schottky diode of claim 1 wherein fabricating a mask layer on the n-type gallium oxide layer on which the anode metal layer is fabricated comprises:
spin-coating photoresist on the n-type gallium oxide layer on which the anode metal layer is prepared;
and baking the device subjected to photoresist spin coating to form inclined side walls of the photoresist, wherein the angle between the side walls and the n-type gallium oxide layer is smaller than 60 degrees.
3. The method of manufacturing a schottky diode of claim 2 wherein the baking process is performed at a temperature of 110 ℃ for a period of 2 minutes.
4. The method of manufacturing a schottky diode of claim 1 wherein said high temperature annealing the front surface of the device comprises:
and carrying out high-temperature annealing treatment on the front surface of the device by adopting an annealing mode of first temperature and then second temperature or an annealing mode of first temperature and then first temperature, wherein the first temperature is smaller than the second temperature, the first temperature and the second temperature are both between 200 ℃ and 900 ℃, and the annealing time corresponding to the first temperature and the annealing time corresponding to the second temperature are both between 10 seconds and 30 minutes.
5. The method of manufacturing a schottky diode of claim 1, further comprising, after the high temperature annealing of the front surface of the device:
depositing a dielectric layer on the front surface of the device;
removing the dielectric layer of the area where the field plate structure to be prepared is located through dry etching;
preparing a field plate structure, wherein an orthographic projection of the field plate structure covers all anode metal layers.
6. A schottky diode, wherein the schottky diode is prepared by the method of any one of claims 1 to 5, and the schottky diode comprises:
a substrate;
an n-type gallium oxide layer formed on the substrate, wherein the n-type gallium oxide layer is formed with a bevel structure, the outer edge of the bevel structure is overlapped with the outer edge of the n-type gallium oxide layer, the thickness of the n-type gallium oxide layer in a corresponding area of the bevel structure is increased from the outer edge to the inner edge, and a thermal oxidation treatment area formed by high-temperature annealing treatment of the n-type gallium oxide is arranged below the bevel structure;
an anode metal layer formed on the n-type gallium oxide layer; wherein the projected edge of the anode metal layer on the n-type gallium oxide layer coincides with the inner edge of the inclined plane structure; the included angle between the plane where the inclined plane structure is positioned and the contact surface is an obtuse angle; the contact surface is the surface of the anode metal layer, which is contacted with the n-type gallium oxide layer;
and a cathode metal layer formed on the back surface of the substrate.
7. The schottky diode of claim 6 wherein,
the included angle between the slope in the inclined plane structure and the horizontal direction is smaller than 60 degrees.
8. The schottky diode of claim 6 wherein a dielectric layer is disposed over said sloped structure.
9. The schottky diode of claim 6 further comprising a field plate structure disposed over said anode metal layer, wherein an orthographic projection of said field plate structure covers all of the anode metal layer.
10. The schottky diode of claim 9 wherein said field plate structure and said bevel structure are supported therebetween by a dielectric fill.
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