CN110931571A - Vertical GaN-based groove junction barrier Schottky diode and manufacturing method thereof - Google Patents
Vertical GaN-based groove junction barrier Schottky diode and manufacturing method thereof Download PDFInfo
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Abstract
The invention belongs to the technical field of semiconductor power electronic devices, and particularly relates to a vertical GaN-based groove junction barrier Schottky diode and a manufacturing method thereof. The device structure comprises from bottom to top in sequence: an ohmic contact electrode-diode cathode overlying the substrate; a GaN self-supporting substrate; an n-type low carrier concentration region-device drift region including a first drift region and a device second drift region located over the device first drift region; p-type GaN regions staggered with the second drift region of the device; an electrode forming a schottky contact with the second drift region of the device-a diode anode. The p-type GaN region is formed by an epitaxial method, and the p-type GaN with high carrier concentration is obtained; by the method of epitaxial growth of the drift region of the device in the region selected after p-GaN etching, GaN-based groove type JBS is formed, and high p-GaN depth is obtained, so that the shielding effect of a pn junction on the Schottky junction is enhanced under reverse bias, the reverse leakage of the device is reduced, and the breakdown voltage of the device is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor power electronic devices, and particularly relates to a vertical GaN-based groove junction barrier Schottky diode and a manufacturing method thereof.
Background
The Schottky diode has the characteristics of low turn-on voltage and reverse quick recovery, and is applied to a plurality of fields such as power supplies, driving circuits and the likeDomains have a wide range of applications. Application requirements for schottky devices include low on-resistance, high breakdown voltage. With the maturation of the conventional semiconductor material Si process, semiconductor devices based on Si materials have reached theoretical limits. The GaN material has high critical breakdown electric field (3.3MV/cm), high mobility (1000 cm)2V · s), the theoretical limit of the material is far beyond that of Si material, and higher breakdown voltage and lower on-resistance can be obtained when applied to power devices. Therefore, the development of the GaN-based Schottky diode has huge application prospect.
However, the main problem of the schottky diode is the soft breakdown of the device caused by the large reverse leakage, which is caused by the image barrier lowering effect of the schottky junction under the reverse bias and the tunneling current of the schottky junction. In order to reduce reverse leakage of the schottky junction, the method mainly adopted is to isolate the schottky junction under reverse bias, and a Junction Barrier Schottky (JBS) diode is a common device structure. In the JBS diode, a plurality of pn junctions are formed in a drift region of the device through ion implantation and are staggered with Schottky junctions. The working principle of the JBS device is as follows: under forward bias, the Schottky junction barrier is low in height and can be started first, so that the JBS device is small in starting voltage, and the excellent forward characteristic of the Schottky diode is reserved; under reverse bias, the depletion regions of adjacent pn junctions are communicated in an expanding mode, the Schottky junctions can be isolated, the reverse characteristic of the device is shown as the reverse characteristic of the pn junctions, the pn junctions have higher potential barrier than the Schottky junctions, reverse leakage current of the device can be reduced, and breakdown voltage of the device is improved, so that the JBS diode gets rid of the defects of the Schottky diode existing under the reverse bias.
The GaN-based JBS diode with high breakdown voltage has important significance for promoting GaN material industrialization, high-efficiency power electronic device application and the like, a small part of reports related to the GaN-based JBS diode appear at present, but the breakdown voltage of the diode is far lower than a theoretical value, and the diode has no advantages in practical application, mainly because of the following key problems:
1. ion implantation makes p-GaN difficult. Conventionally, in a Si, SiC based JBS structure, a p-type region is formed by ion implantation of acceptor impurities. Mg is commonly used as an acceptor impurity in GaN materials, and in order to activate ion-implanted Mg in GaN, a high temperature anneal of about 1300 ℃ is required, which can lead to decomposition of n-type GaN. The currently optimized method for activating ion implantation of Mg is SMRTA (symmetric multiple-cycle rapid thermal annealing), but even if acceptor impurities are activated by this method, the activation efficiency and the hole concentration after activation are still low, and the activation efficiency and the hole concentration are not suitable for a diode of a JBS structure.
The depth of p-GaN is small. The p-GaN depth here refers to the distance between the bottom of the p-type lattice and the schottky junction at the top of the drift region in the JBS cell. In the JBS structure diode, the large p-GaN depth is beneficial to the isolation of Schottky junctions under reverse bias and the expansion of a device design window. However, the power of the ion implanter is limited, and the depth of the p-type lattice formed by the ion implantation method is very small, for example, the implantation depth is usually less than 500nm when the power of the ion implanter is 500 keV; whereas in the reported select area epitaxial JBS devices (CN 105405897A; 2019.02.05), the depth of the p-type lattice depends on the height of the epitaxial mesa; in the JBS structure (US 8,969,994B 2; 2015.01.21) formed by the double epitaxial back etching method, the depth of the p-type lattice depends on the etching depth of the drift region of the device. The limited p-GaN depth limits the design window of the GaN-based JBS diode and the breakdown voltage of the device.
Disclosure of Invention
The invention provides a vertical GaN-based groove junction barrier Schottky diode and a manufacturing method thereof to overcome the defects in the prior art, so that the GaN-based Schottky diode keeps low turn-on voltage, low conduction voltage drop and low conduction loss when being conducted in the forward direction, and has low leakage current and high breakdown voltage under reverse bias.
In order to solve the technical problems, the invention adopts the technical scheme that: the utility model provides a vertical type GaN base groove junction barrier schottky diode, device structure includes from bottom to top in proper order: an ohmic contact electrode-diode cathode overlying the substrate; a GaN self-supporting substrate; an n-type low carrier concentration region-device drift region including a first drift region and a device second drift region located over the device first drift region; p-type GaN regions staggered with the second drift region of the device; an electrode forming a schottky contact with the second drift region of the device-a diode anode.
In one embodiment, Al is further arranged between the second drift region of the device and the anode of the diode2O3A dielectric layer region.
In one embodiment, a mask layer is further arranged between the second drift region and the p-type GaN region of the device.
In one embodiment, the substrate is an n-type GaN self-supporting substrate, the substrate resistivity ranges from 0.005 Ω -cm to 0.1 Ω -cm, and the thickness ranges from 100 μm to 500 μm.
In one embodiment, the first drift region of the device is any one of an unintentionally doped GaN epitaxial layer, a Si doped epitaxial layer and an As doped epitaxial layer; the thickness of the first drift region of the device is 1-50 μm, and the carrier concentration is 1 × 1014cm-3～5×1017cm-3。
In one embodiment, the second drift region of the device is any one of an unintentionally doped GaN epitaxial layer, a Si doped epitaxial layer and an As doped epitaxial layer; the thickness of the second drift region of the device is 0.2-25 μm, and the carrier concentration is 1 x 1014cm-3～5×1017cm-3。
In one embodiment, the p-type GaN region is p-type GaN material with a hole concentration of 1 × 1016cm-3～1×1019cm-3The thickness is 0.1-20 μm.
In one embodiment, the cathode of the diode is made of any one of Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; the anode of the diode is made of one of metal Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, TiN, Ta, TaN, ZrN, VN and NbN or a stacked structure thereof.
The invention also provides a manufacturing method of the vertical GaN-based groove junction barrier Schottky diode, which comprises the following steps:
s1, epitaxially growing a first drift region of a device on a substrate;
s2, continuing to epitaxially grow a p-type GaN region on the first drift region of the device;
s3, depositing a dielectric layer SiO2 on the p-type GaN region through PECVD as a mask, and removing SiO at the position of a second drift region of the device2A mask layer;
s4, etching the p-type GaN to expose a first drift region of the device, and removing the photoresist by using acetone after the etching is finished;
s5, epitaxially growing a second drift region of the device, and removing SiO of the mask layer by using buffered hydrofluoric acid after growth is finished2；
S6, evaporating Ti/Al/Ni/Au on the substrate by adopting an electron beam evaporation method or a magnetron sputtering method to form an ohmic contact electrode as a diode cathode;
and S7, after photoetching, evaporating Ni/Au on the front surface of the device by adopting an electron beam evaporation method or a magnetron sputtering method to form a Schottky electrode, and selectively leaving the electrode by adopting a stripping method to serve as the anode of the diode.
In the invention, in order to solve the problem of low activation efficiency of ion implantation Mg in the GaN-based JBS diode, an epitaxial method is adopted to form p-type GaN; in order to solve the problem that the depth of p-GaN in a GaN-based JBS diode is small, a groove is etched on the p-GaN, and then a mesa device drift region is grown through an epitaxial method, so that a larger p-GaN depth can be obtained.
In one embodiment, in the steps S1, S2, and S5, the first drift region, the p-type GaN region, and the second drift region of the device may be epitaxially grown by MBE or HVPE.
In one embodiment, in the step S3, the SiO is removed by etching in the manners of photolithography, wet etching, RIE, and ICP2Masking; in step S4, the p-type GaN region is etched by ICP, reactive ion etching, and TMAH wet etching.
In one embodiment, the step S3 specifically includes:
s31, depositing SiO 0.1-10 microns on p-type GaN by PECVD2A mask layer;
s32, opening a window on the mask layer at the position of the second drift region of the device to be grown through photoetching;
and S33, removing the mask layer which is not covered by the photoresist by using buffered hydrofluoric acid.
In the invention, the principle of solving the problems of the existing GaN-based JBS by using the method is briefly described as follows:
1. difficulty in forming p-GaN by ion implantation: due to the problems of the ion implantation method, the manufacturing scheme adopts an epitaxial method to form the p-type GaN, so that high hole concentration is obtained, and meanwhile, ion implantation damage is avoided;
2. improving the depth of p-GaN: in order to form a JBS device structure in the manufacturing scheme, an initial epitaxial wafer structure before the epitaxy of the second drift region of the device is sequentially from top to bottom: p-type GaN; low carrier concentration n-type GaN; a GaN free-standing substrate. And after grooves are etched on the p-GaN, selective area epitaxy is carried out, and a second drift area of the mesa-shaped device is grown, so that the depth of the p-GaN is the sum of the heights of the p-GaN area and the drift area mesa beyond the p-GaN area. The fabrication scheme can result in a greater p-GaN depth than other schemes where the p-GaN depth is controlled by ICP etching the recess alone or by mesa drift region height.
Compared with the prior art, the beneficial effects are: according to the vertical GaN-based groove junction barrier Schottky diode and the manufacturing method thereof, the p-type GaN region is formed through an epitaxial method, and p-type GaN with high carrier concentration is obtained; by the method of epitaxial growth of the drift region of the device in the region selected after p-GaN etching, GaN-based groove type JBS is formed, and high p-GaN depth is obtained, so that the shielding effect of a pn junction on the Schottky junction is enhanced under reverse bias, the reverse leakage of the device is reduced, and the breakdown voltage of the device is improved.
Drawings
Fig. 1 to 5 are schematic views of a process of a device according to embodiment 1 of the present invention, wherein fig. 5 is a schematic view of an overall structure of the device according to embodiment 1.
Fig. 6 to 8 are schematic views of the processes of the device of embodiment 2 of the present invention, wherein fig. 8 is a schematic view of the overall structure of the device of embodiment 2.
Fig. 9 to 12 are schematic views of processes of a device according to embodiment 3 of the present invention, wherein fig. 12 is a schematic view of an overall structure of the device according to embodiment 3.
Fig. 13 to 15 are schematic views of processes of a device according to embodiment 4 of the present invention, wherein fig. 15 is a schematic view of an overall structure of the device according to embodiment 4.
Detailed Description
The drawings are for illustration purposes only and are not to be construed as limiting the invention; for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the invention.
Example 1:
as shown in fig. 5, fig. 5 is a schematic structural diagram of the device of this embodiment, and the structure thereof sequentially includes, from bottom to top: an ohmic contact electrode-diode cathode 15 covering the substrate 11; a GaN self-supporting substrate 11; n-type low carrier concentration region-device first drift region 12 and device second drift region 14; p-type GaN regions 13 arranged with a staggered arrangement with the device second drift region 14; an electrode forming a schottky contact with the device second drift region 14-a diode anode 16.
The specific process flow of this example is as follows:
1. initial epitaxial structure formation
A first drift region 12 of the device with n-type conductivity is extended on an n-type low resistivity substrate 11, and then a p-type conductive p-type GaN region 13 is extended, wherein the epitaxial structure of the material after the completion of the step is shown in fig. 1.
2. Selective area epitaxial mask preparation
2.1. PECVD deposition of SiO on p-type conductive p-type GaN regions 132As mask layer 17;
2.2. in SiO2The mask layer 17 is coated with photoresist, and the area of the mask layer 17 to be etched is exposed after exposure and development;
2.3. selectively etching the mask region by using a buffer hydrofluoric acid solution;
2.4. etching the epitaxial wafer by adopting ICP (inductively coupled plasma), removing the p-type GaN without the mask region, and stopping etching after the first drift region 12 of the device is exposed;
2.5 removing the photoresist with acetone, the device structure is shown in fig. 2.
3. Device second drift region 14 epitaxy
3.1. Placing the epitaxial wafer into MOCVD equipment, epitaxially growing a second drift region 14 of the device, and obtaining a structure shown in FIG. 3;
3.2. the mask layer 17 is removed by etching with buffered hydrofluoric acid, and the completed structure is shown in fig. 4.
4. Electrode evaporation
4.1. Evaporating Ti/Al/Ni/Au on the back of the epitaxial wafer to form ohmic contact to be used as a diode cathode 15;
4.2. coating photoresist on the surfaces of the second drift region 14 and the p-type GaN region 13 of the epitaxial wafer device, evaporating Ni/Au after exposure and development, forming Schottky contact with the second drift region 14 of the device, and forming an anode of the diode after stripping;
4.3. the process flow described in example 1 was completed and the final device structure is shown in fig. 5.
Example 2
The final device structure of this embodiment is shown in fig. 8, and compared with embodiment 1, the difference is that after the epitaxy of the second drift region 14 of the device in embodiment 1 is completed, the following process steps are performed in this embodiment:
1. sidewall forming MIS structure
1.1. Depositing Al on the surface of the epitaxial wafer by adopting an atomic layer deposition method2O3A dielectric layer region 18, the finished device structure being as shown in fig. 6;
1.2. coating photoresist on the dielectric layer region 18, and removing the photoresist on the top of the second drift region 14 and the p-type GaN region 13 of the device after exposure and development;
1.3. etching and removing the dielectric layer which is not covered by the photoresist by using buffered hydrofluoric acid;
1.4. the photoresist was removed with acetone and the finished device structure is shown in fig. 7.
2. Electrode evaporation
2.1. Evaporating Ti/Al/Ni/Au on the back of the epitaxial wafer to form ohmic contact to be used as a diode cathode 15;
2.2. coating photoresist on the surfaces of the second drift region 14 and the p-type GaN region 13 of the epitaxial wafer device, evaporating Ni/Au after exposure and development, forming Schottky contact with the second drift region 14 of the device, and forming an anode of the diode after stripping;
2.3. the process flow described in example 2 was completed and the device structure is shown in fig. 8.
Example 3
The final device structure of this embodiment is shown in fig. 12, and compared with embodiment 1, the difference is that the material epitaxially grown in the selected region is p-GaN, and only the device first drift region 12 and no device second drift region 14 are provided. The specific process flow of the embodiment is as follows:
1. initial epitaxial structure formation
Extending an n-type conductive device drift region on an n-type low-resistivity substrate 11, wherein the epitaxial structure of the material after the step is finished is shown as figure 9;
2. selective area etching and epitaxy
2.1. SiO is deposited on the first drift region 12 of the device by PECVD2As mask layer 17;
2.2. in SiO2Coating photoresist on the mask, exposing the mask layer 17 to be removed after exposure and development, and selectively etching the mask region by using a buffered hydrofluoric acid solution;
2.3. etching the epitaxial wafer by adopting ICP (inductively coupled plasma), etching a groove in the drift region of the device without being covered by the mask layer 17, and finishing the structure of the device as shown in figure 10;
2.4. and (3) placing the epitaxial wafer into an epitaxial chamber to grow p-type GaN, and removing the mask layer 17 after the growth is finished, wherein the device structure is shown in FIG. 11.
3. Evaporation electrode
3.1. Evaporating Ti/Al/Ni/Au on the back of the epitaxial wafer to form ohmic contact to be used as a diode cathode 15;
3.2. coating photoresist on one side of the first drift region 12 of the epitaxial wafer device, evaporating Ni/Au after exposure and development to form Schottky contact with the drift region of the device, and forming an anode of the diode after stripping;
3.3. the process flow described in example 3 was completed and the device structure is shown in fig. 12.
Example 4
Fig. 15 shows a final device structure in this embodiment, and the process of this embodiment is similar to that of embodiment 1, and includes controlling step 3 of embodiment 1: the structure shown in fig. 13 is formed by the factors such as chamber pressure, growth time, gas proportion and the like in the epitaxial process of the second drift region 14 of the device; when the mask is etched, by controlling the proportion and the temperature of the etching solution, a part of the mask layer 17 existing in the second drift region 14 of the device is not etched, so that the structure shown in fig. 14 is formed. After the electrodes were evaporated, the device structure of this example was formed as shown in fig. 15.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. The utility model provides a vertical type GaN base groove junction barrier schottky diode which characterized in that, the device structure includes by lower to upper in proper order: an ohmic contact electrode-diode cathode (15) covering the substrate (11); a GaN self-supporting substrate (11); an n-type low carrier concentration region-device drift region comprising a first drift region (12) and a device second drift region (14) located above the device first drift region (12); p-type GaN regions (13) staggered with the second drift region (14) of the device; a Schottky contact electrode-diode anode (16) is formed with the device second drift region (14).
2. The vertical GaN-based groove junction barrier Schottky diode of claim 1, wherein Al is further disposed between the second drift region (14) and the diode anode (16)2O3A dielectric layer region (18).
3. The vertical GaN-based groove junction barrier schottky diode of claim 1 wherein a mask layer (17) is further disposed between the second drift region (14) of the device and the p-type GaN region (13).
4. The vertical GaN-based groove-junction barrier schottky diode according to any one of claims 1 to 3, wherein the substrate (11) is an n-type GaN self-standing substrate (11), the substrate (11) has a resistivity ranging from 0.005 Ω -cm to 0.1 Ω -cm and a thickness ranging from 100 μm to 500 μm; the p-type GaN region (13) is p-type GaN material with a hole concentration of 1 × 1016cm-3～1×1019cm-3The thickness is 0.1-20 μm.
5. The vertical GaN-based groove-junction barrier schottky diode As claimed in any one of claims 1 to 3, wherein the device first drift region (12) is any one of an unintentionally doped GaN epitaxial layer, a Si doped epitaxial layer, and an As doped epitaxial layer; the thickness of the first drift region (12) of the device is 1-50 μm, and the carrier concentration is 1 x 1014cm-3～5×1017cm-3(ii) a The second drift region (14) of the device is any one of an unintentionally doped GaN epitaxial layer, a Si doped epitaxial layer and an As doped epitaxial layer; the thickness of the second drift region (14) of the device is 0.2-25 μm, and the carrier concentration is 1 x 1014cm-3～5×1017cm-3。
6. The vertical GaN-based groove-junction barrier Schottky diode according to any one of claims 1 to 3, wherein the material of the diode cathode (15) is any one of Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy, or Ti/Al/Ti/TiN alloy; the anode (16) of the diode is made of one of metal Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, TiN, Ta, TaN, ZrN, VN and NbN or a stacked structure thereof.
7. A manufacturing method of a vertical GaN-based groove junction barrier Schottky diode is characterized by comprising the following steps:
s1, epitaxially growing a first drift region (12) of a device on a substrate (11);
s2, continuing to epitaxially grow a p-type GaN region (13) on the first drift region (12) of the device;
s3, depositing a dielectric layer SiO on the p-type GaN region (13) through PECVD2As a mask layer (17), SiO at the position of the second drift region (14) of the device is removed2A mask layer (17);
s4, etching the p-type GaN to expose a first drift region (12) of the device, and removing the photoresist by using acetone after the etching is finished;
s5, epitaxially growing a second drift region (14) of the device, and removing the mask layer (17) SiO by using buffered hydrofluoric acid after the growth is finished2；
S6, evaporating Ti/Al/Ni/Au on the substrate (11) by adopting an electron beam evaporation method or a magnetron sputtering method to form an ohmic contact electrode as a diode cathode (15);
and S7, after photoetching, evaporating Ni/Au on the front surface of the device by adopting an electron beam evaporation method or a magnetron sputtering method to form a Schottky electrode, and selectively leaving the electrode by adopting a stripping method to be used as a diode anode (16).
8. The method of claim 7, wherein in the steps S1, S2 and S5, the first drift region (12), the p-type GaN region (13) and the second drift region (14) can be epitaxially grown by MBE or HVPE.
9. The method of claim 7, wherein in step S3, SiO is removed by etching in the manners of photolithography, wet etching, RIE and ICP2A mask layer (17); in the step S4, the p-type GaN region (13) is etched by ICP, reactive ion etching, and TMAH wet etching.
10. The method of claim 9, wherein the step S3 comprises:
s31, depositing SiO 0.1-10 microns on p-type GaN by PECVD2A mask layer (17);
s32, opening a window on the mask layer (17) at the position of the second drift region (14) of the device to be grown through photoetching;
and S33, removing the mask layer (17) which is not covered by the photoresist by using buffered hydrofluoric acid.
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