CN113658859B - Preparation method of gallium nitride power device - Google Patents
Preparation method of gallium nitride power device Download PDFInfo
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- CN113658859B CN113658859B CN202110743594.5A CN202110743594A CN113658859B CN 113658859 B CN113658859 B CN 113658859B CN 202110743594 A CN202110743594 A CN 202110743594A CN 113658859 B CN113658859 B CN 113658859B
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000005516 engineering process Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 238000001704 evaporation Methods 0.000 claims description 9
- 229910001020 Au alloy Inorganic materials 0.000 claims description 6
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 2
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 2
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 14
- 229910052681 coesite Inorganic materials 0.000 claims 7
- 229910052906 cristobalite Inorganic materials 0.000 claims 7
- 239000000377 silicon dioxide Substances 0.000 claims 7
- 235000012239 silicon dioxide Nutrition 0.000 claims 7
- 229910052682 stishovite Inorganic materials 0.000 claims 7
- 229910052905 tridymite Inorganic materials 0.000 claims 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 229910052593 corundum Inorganic materials 0.000 claims 1
- 229910001845 yogo sapphire Inorganic materials 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 6
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000000407 epitaxy Methods 0.000 abstract description 2
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a gallium nitride power device. The longitudinal conduction of the device is realized by the substrate stripping technology, so that the dependence on a GaN self-supporting substrate can be effectively relieved in the middle-low voltage application field, and the manufacturing cost of the device is greatly reduced; the terminal structure is manufactured by adopting the selective region epitaxy p-type GaN method, so that lattice damage caused by ion implantation or etching is avoided, p-type GaN with high carrier concentration is obtained, and the electric field concentration effect existing below the device electrode under reverse bias is slowed down, thereby improving the breakdown voltage of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a gallium nitride power device.
Background
The power semiconductor device can realize electric energy conversion and circuit control of the electric power equipment through the high-speed switch. Wherein the power diode mainly comprises a pn diode and a Schottky diode. Compared with a pn junction diode, the Schottky diode has the characteristics of low starting voltage and high switching speed, can exert the advantages of low power loss and high working frequency in a power electronic system, and has wide application prospects in the fields of power supplies, driving circuits and the like. In the past few decades, si materials have been widely used in the field of power electronics due to their low cost, simple process, easy integration, etc. However, the narrow forbidden bandwidth of Si material (1.12 eV), low critical breakdown field (0.3 MV/cm) makes Si devices unable to meet the demand for continuous increase of performance in the market. GaN, which is representative of third generation semiconductor materials, has a wide forbidden bandwidth (3.4 eV), a high critical breakdown field (3.4 MV/cm), and a high saturated electron drift rate (2.5X10) 7 cm/s), high thermal conductivity and the like, and has great development space in the fields of high-temperature, high-frequency and high-power electronic devices.
When a reverse bias is applied to the schottky diode, an electric field concentration effect occurs below the edge of the electrode where the electric field is much higher than the electric field at the Yu Xiaote base junction surface, resulting in early breakdown of the device. It is therefore often desirable to employ termination structures to mitigate the effects of electric field concentration. One common terminal structure is that a pn junction is formed below an electrode by ion implantation or etching of a p-type GaN epitaxial layer, and a pn junction depletion region is extended under reverse bias, so that an electric field concentration effect can be effectively relieved. However, there are difficulties in forming p-type GaN by ion implantation. Mg is generally used as acceptor impurity in GaN material, but to activate Mg in GaN, high temperature annealing above 1300 ℃ is required, which leads to n-type GaN decomposition, and the current activation efficiency and hole concentration after activation are still relatively low. In addition, ion implantation of Mg also causes some lattice damage. By adopting the method for etching the p-type GaN epitaxial layer, the etching depth needs to be accurately controlled, and certain etching damage exists on the side wall and the bottom surface of the etched groove, so that the performance of the device is affected.
On the other hand, gaN schottky diodes mainly have a longitudinal type and a quasi-longitudinal type structure from the viewpoint of device structure. For the longitudinal device, the current distribution is uniform, the occupied area is small, the heat dissipation is good, and the like, but a homogeneous substrate is generally needed, and the current GaN self-supporting substrate is high in price, small in wafer size and not beneficial to commercialization. While the quasi-longitudinal device can adopt an Si substrate and a sapphire substrate with low price, the quasi-longitudinal device also has the problems of uneven current distribution, deep side wall etching requirement, low wafer utilization rate and the like.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a preparation method of a gallium nitride power device, which can effectively reduce the cost of device preparation, effectively relieve the electric field concentration effect below a reverse bias lower electrode and improve the breakdown voltage of the device.
In order to solve the technical problems, the invention adopts the following technical scheme: a preparation method of a gallium nitride power device comprises the following steps:
s1, epitaxially growing a device drift region on a substrate through MOCVD;
s2, performing device isolation through an ICP etching table top;
s3, depositing a dielectric layer SiO on the drift region of the device by PECVD 2 As a mask, siO at the position of the p-type GaN region is removed 2 A mask layer;
s4, epitaxially growing a p-type GaN regionDomain, removing SiO 2 A mask layer;
s5, growing a dielectric layer on the device formed in the step S4, and removing the dielectric layer at the position of the Schottky contact area of the device;
s6, bonding the device formed in the step S5 onto a temporary substrate through a bonding layer;
s7, stripping the original substrate from the device formed in the step S6 through a substrate stripping technology;
s8, evaporating Ti/Al/Ni/Au on the drift region of the device by adopting an electron beam evaporation method or a magnetron sputtering method to form an ohmic contact electrode serving as a cathode of the diode;
s9, electroplating metal Ni on the ohmic contact electrode to form a metal substrate;
s10, removing the bonding layer and the temporary substrate;
s11, evaporating Ni/Au on the p-type GaN region and the drift region of the device by adopting an electron beam evaporation method or a magnetron sputtering method to form a Schottky electrode, and selectively leaving the electrode by adopting a stripping method to serve as a diode anode.
Further, the step S3 specifically includes:
s31, depositing SiO of 0.1-10 mu m on the drift region of the device by PECVD 2 A mask layer;
s32 SiO at the position where the p-type GaN region is to be grown 2 Opening a window on the mask layer by photoetching;
s33, removing SiO uncovered by photoresist through buffered hydrofluoric acid 2 And (5) a mask layer.
The method for manufacturing a gallium nitride power device according to claim 2, wherein the step S5 specifically includes:
s51, depositing a dielectric layer of 10 nm-500 nm on the device formed in the step S4;
s52, opening a window on the dielectric layer at the schottky contact position to be formed through photoetching;
and S53, removing the dielectric layer which is not covered by the photoresist through a buffer hydrofluoric acid solution.
Further, the device drift region is an unintentionally doped GaN epitaxial layer and an Si doped epitaxial layer with low dislocation densityOr an As doped epitaxial layer; the thickness of the drift region of the device is 1 μm to 50 μm, and the carrier concentration is 1×10 14 cm -3 ～5×10 17 cm -3 。
Further, the p-type GaN region has a hole concentration of 1×10 16 cm -3 ～1×10 19 cm -3 The thickness is 0.1 μm to 10 μm.
Further, the dielectric layer is made of Al 2 O 3 、SiN、SiO 2 The thickness of any one of the materials is 10 nm-500 nm.
Further, the metal substrate material is one of Cu and Ni, and the thickness is 40-100 μm.
Further, the material of the diode cathode is any one of Ti/Al/Ni/Au alloy, ti/Al/Ti/Au alloy, ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy.
Further, the material of the diode anode is one of metals Ni, au, pt, pd, ir, mo, al, ti, tiN, ta, taN, zrN, VN, nbN or a stacked structure thereof.
Further, the substrate in the step S1 includes a sapphire substrate, a SiC substrate, or a Si substrate.
Compared with the prior art, the beneficial effects are that: according to the preparation method of the gallium nitride power device, provided by the invention, the longitudinal conduction of the device is realized through the substrate stripping technology, so that the dependence on a GaN self-supporting substrate can be effectively relieved in the middle-low voltage application field, and the manufacturing cost of the device is greatly reduced; the terminal structure is manufactured by adopting the selective region epitaxy p-type GaN method, so that lattice damage caused by ion implantation or etching is avoided, p-type GaN with high carrier concentration is obtained, and the electric field concentration effect existing below the device electrode under reverse bias is slowed down, thereby improving the breakdown voltage of the device.
Drawings
Fig. 1 to 7 are schematic views showing the process flow of the device according to embodiment 1 of the present invention, wherein fig. 7 shows a schematic view of the overall structure of the device prepared in embodiment 1.
Fig. 8 to 12 are schematic process flow diagrams of the device of example 2 of the present invention, in which the overall structure of the device prepared in example 2 is identical to that of example 1.
Reference numerals: 1. a substrate; 2. a device drift region; 3. a mask layer; 4. a p-type GaN region; 5. a dielectric layer; 6. a bonding layer; 7. a temporary substrate; 8. a diode cathode; 9. a metal substrate; 10. and a diode anode.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the invention; for the purpose of better illustrating the embodiments, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the actual product dimensions; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationship described in the drawings are for illustrative purposes only and are not to be construed as limiting the invention.
Example 1:
as shown in fig. 7, the device structure of this embodiment is shown in the following order: a metal substrate 9 covering the device cathode; an ohmic electrode-diode cathode 8 covering the device drift region 2; n-type low carrier concentration region-device drift region 2; junction termination-p-type GaN region 4; a dielectric layer 5 covering the p-type GaN region 4; an electrode-diode anode 10 forming a schottky contact with the drift region.
The preparation method of the gallium nitride power device comprises the following steps:
step 1.1 epitaxial Structure
An n-type conductive device drift region 2 is epitaxially grown on a substrate 1, and the material epitaxial structure after this step is completed is shown in fig. 1.
Step 1.2 device isolation
S21, coating photoresist on the n-type conductive device drift region 2, exposing a region to be etched after exposure and development;
s22, etching the area which is not covered by the photoresist through ICP;
s23, removing the photoresist by using acetone.
Step 1.3 preparation of mask layer 3
S31, depositing SiO on the drift region 2 of the device 2 As a mask layer 3;
s32, at SiO 2 Coating photoresist on the mask layer 3, exposing the position of the p-type region to be epitaxially grown after exposure and development;
s33, selectively etching the mask layer 3 which is not covered by the photoresist by using a buffer hydrofluoric acid solution, wherein the structure of the completed device is shown in fig. 2.
Step 1.4 epitaxial growth of p-type GaN
S41, placing the device prepared in the step 1.3 into an MOCVD chamber to epitaxially grow p-type GaN, so as to form a p-type GaN region 4;
s42, removing SiO by using buffer hydrofluoric acid solution 2 Mask layer 3, the device structure after completion is shown in fig. 3.
Step 1.5, growing a medium layer 5;
s51, placing the device prepared in the step 1.4 into a cavity to grow a medium layer 5;
s52, coating photoresist on the dielectric layer 5, exposing a region needing to remove the dielectric layer 5 after exposure and development;
s53, selectively etching the dielectric layer 5 which is not covered by the photoresist by using a buffer hydrofluoric acid solution;
s54, removing the photoresist by using acetone, wherein the structure is shown in fig. 4 after completion.
Step 1.6 substrate 1 peeling
S61, bonding the device prepared in the step 5 onto a temporary substrate 7 through a bonding layer 6;
s62, peeling the substrate 1 from the device prepared in the step S1.5 through a substrate peeling technology, wherein the structure of the device after completion is shown in FIG. 5.
Step 1.7 deposition of cathode Metal
S71, evaporating Ti/Al/Ni/Au on the back of the device prepared in the step S1.6 to form ohmic contact, and taking the ohmic contact as a diode cathode 8;
s72, electroplating metal Ni on the ohmic contact electrode to form a metal substrate 9, and the structure of the completed device is shown in FIG. 6.
Step 1.8 deposition of anodic metal
S81, removing the bonding layer 6 and the temporary substrate 7;
s82, coating photoresist on the device prepared in the step 1.7, evaporating Ni/Au after exposure and development, forming Schottky contact with the drift region 2 of the device and the p-type GaN region 4, and stripping to form a diode anode 10;
s83, the process flow described in the embodiment 1 is completed, and the final device structure is shown in FIG. 7.
Example 2
The final device structure of this example is the same as that of example 1, except that in example 1, the device is transferred to the temporary substrate 7, and the temporary substrate 7 is removed after the original substrate 1 is peeled off, but the temporary substrate 7 is not used in this example. In this embodiment, after the growth of the n-type device drift region 2 is completed in embodiment 1, the following process flow is performed:
step 2.1 deposition of cathode Metal
S11, evaporating Ti/Al/Ni/Au on the front surface of the device after the growth of the n-type device drift region 2 is completed in the embodiment 1 to form ohmic contact, and taking the ohmic contact as a diode cathode 8;
s12, electroplating metal Ni on the ohmic contact electrode to form a metal substrate 9, and the structure of the finished device is shown in FIG. 8.
Step 2.2 substrate 1 peeling
The substrate 1 is peeled from the step 2.1 by a substrate 1 peeling technique, and the completed device structure is shown in fig. 9.
Step 2.3 device isolation
S31, coating photoresist on the n-type conductive device drift region 2, exposing a region to be etched after exposure and development;
s32, etching the area which is not covered by the photoresist through ICP;
and S33, removing the photoresist by using acetone.
Step 2.4 preparation of mask layer 3
S41 deposition of SiO on drift region 2 2 As a mask layer 3;
s42, at SiO 2 Coating photoresist on the mask layer 3, exposing a region needing to form p-type GaN after exposure and development;
s43, selectively etching the mask layer 3 which is not covered by the photoresist by using a buffer hydrofluoric acid solution, wherein the structure of the completed device is shown in FIG. 10;
step 2.6 epitaxial growth of p-type GaN
S61, placing the device prepared in the step 2.5 into an MOCVD chamber to epitaxially grow p-type GaN, so as to form a p-type GaN region 4;
s62, removing SiO by using buffer hydrofluoric acid solution 2 Mask layer 3, the completed device structure is shown in fig. 11.
Step 2.7 growth of dielectric layer 5
S71, placing the device prepared in the step 2.6 into a chamber to grow a medium layer 5;
s72, coating photoresist on the dielectric layer 5, exposing a region needing to remove the dielectric layer 5 after exposure and development;
s73, selectively etching the dielectric layer 5 which is not covered by the photoresist by using a buffer hydrofluoric acid solution;
s74, removing the photoresist by using acetone, wherein the structure is shown in FIG. 12 after completion.
Step 2.8 Evaporation of anode Metal
S81, coating photoresist on the device prepared in the step 2.7, evaporating Ni/Au after exposure and development, forming Schottky contact with the drift region 2 of the device and the p-type GaN region 4, and stripping to form an anode of the diode;
s82, the process flow described in the embodiment 2 is completed, and the final device structure is shown in FIG. 7.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
It is to be understood that the above examples of the present invention are provided by way of illustration only and not by way of limitation of the embodiments of the present invention. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are desired to be protected by the following claims.
Claims (1)
1. The preparation method of the gallium nitride power device is characterized by comprising the following steps of:
s1, epitaxially growing a device drift region (2) on a substrate (1) through MOCVD;
s2, performing device isolation on the ICP etching table top;
s3, depositing a dielectric layer (5) SiO2 serving as a mask on the device drift region (2) through PECVD, and removing the SiO2 mask layer (3) at the position of the p-type GaN region (4); the method specifically comprises the following steps:
s31, depositing a SiO2 mask layer (3) with the thickness of 0.1-10 mu m on the device drift region (2) through PECVD;
s32, opening a window on the SiO2 mask layer (3) at the position where the p-type GaN region (4) is to be grown through photoetching;
s33, removing the SiO2 mask layer (3) which is not covered by the photoresist through buffered hydrofluoric acid;
s4, epitaxially growing a p-type GaN region (4), and removing the SiO2 mask layer (3);
s5, growing a dielectric layer (5) on the device formed in the step S4, and removing the dielectric layer (5) at the position of the Schottky contact area of the device; the method specifically comprises the following steps:
s51, depositing a dielectric layer (5) of 10-500 nm on the device formed in the step S4;
s52, opening a window on the dielectric layer (5) where the Schottky contact position is to be formed through photoetching;
s53, removing the dielectric layer (5) which is not covered by the photoresist through buffered hydrofluoric acid;
s6, bonding the device formed in the step S5 onto a temporary substrate (7) through a bonding layer (6);
s7, stripping the original substrate (1) from the device formed in the step S6 through a substrate stripping technology;
s8, evaporating Ti/Al/Ni/Au on the device drift region (2) by adopting an electron beam evaporation method or a magnetron sputtering method to form an ohmic contact electrode serving as a diode cathode (8);
s9, electroplating metal Ni on the ohmic contact electrode to form a metal substrate (9);
s10, removing the bonding layer (6) and the temporary substrate (7);
s11, evaporating Ni/Au on a p-type GaN region (4) and a drift region of the device by adopting an electron beam evaporation method or a magnetron sputtering method to form a Schottky electrode, and selectively leaving the electrode by adopting a stripping method to serve as a diode anode (10);
the device drift region (2) is an unintentionally doped GaN epitaxial layer, an Si doped epitaxial layer or an As doped epitaxial layer with low dislocation density; the thickness of the device drift region (2) is 1-50 mu m, and the carrier concentration isThe method comprises the steps of carrying out a first treatment on the surface of the The p-type GaN region (4) has a hole concentration of +.>The thickness is 0.1-10 mu m; the material of the dielectric layer (5) is any one of Al2O3, siN and SiO2, and the thickness is 10 nm-500 nm; the metal substrate (9) is made of one of Cu and Ni, and the thickness is 40-100 mu m; the material of the diode cathode (8) is any one of Ti/Al/Ni/Au alloy, ti/Al/Ti/Au alloy, ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; the material of the diode anode (10) is one of metal Ni, au, pt, pd, ir, mo, al, ti, tiN, ta, taN, zrN, VN, nbN or a stacked structure thereof; the substrate (1) in the step S1 includes a sapphire substrate, a SiC substrate, or a Si substrate.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661985A (en) * | 2009-09-18 | 2010-03-03 | 厦门市三安光电科技有限公司 | Manufacturing method of gallium nitride based LED with vertical structure |
| CN102299226A (en) * | 2010-06-24 | 2011-12-28 | 上海蓝光科技有限公司 | LED (light emitting diode) with vertical structure and manufacturing method thereof |
| CN106611809A (en) * | 2017-01-11 | 2017-05-03 | 东莞市中镓半导体科技有限公司 | Preparing method for GaN growth composite substrate with isolation protection layer |
| CN110085518A (en) * | 2019-05-06 | 2019-08-02 | 南京邮电大学 | A kind of preparation method for the transferable GaN film and its device that selective electrochemical method is removed |
| CN110931571A (en) * | 2019-12-18 | 2020-03-27 | 中山大学 | Vertical GaN-based groove junction barrier Schottky diode and manufacturing method thereof |
| CN211017091U (en) * | 2019-12-18 | 2020-07-14 | 中山大学 | Vertical GaN-based groove junction barrier Schottky diode |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106169417A (en) * | 2016-07-11 | 2016-11-30 | 厦门市三安集成电路有限公司 | A kind of silicon carbide power device of hetero-junctions terminal and preparation method thereof |
-
2021
- 2021-06-30 CN CN202110743594.5A patent/CN113658859B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661985A (en) * | 2009-09-18 | 2010-03-03 | 厦门市三安光电科技有限公司 | Manufacturing method of gallium nitride based LED with vertical structure |
| CN102299226A (en) * | 2010-06-24 | 2011-12-28 | 上海蓝光科技有限公司 | LED (light emitting diode) with vertical structure and manufacturing method thereof |
| CN106611809A (en) * | 2017-01-11 | 2017-05-03 | 东莞市中镓半导体科技有限公司 | Preparing method for GaN growth composite substrate with isolation protection layer |
| CN110085518A (en) * | 2019-05-06 | 2019-08-02 | 南京邮电大学 | A kind of preparation method for the transferable GaN film and its device that selective electrochemical method is removed |
| CN110931571A (en) * | 2019-12-18 | 2020-03-27 | 中山大学 | Vertical GaN-based groove junction barrier Schottky diode and manufacturing method thereof |
| CN211017091U (en) * | 2019-12-18 | 2020-07-14 | 中山大学 | Vertical GaN-based groove junction barrier Schottky diode |
Non-Patent Citations (1)
| Title |
|---|
| 硅基GaN功率半导体技术;周琦;陈万军;张波;;电力电子技术(第12期);全文 * |
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