CN108206220B - Preparation method of diamond Schottky diode - Google Patents
Preparation method of diamond Schottky diode Download PDFInfo
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- CN108206220B CN108206220B CN201711474465.0A CN201711474465A CN108206220B CN 108206220 B CN108206220 B CN 108206220B CN 201711474465 A CN201711474465 A CN 201711474465A CN 108206220 B CN108206220 B CN 108206220B
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- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 132
- 239000010432 diamond Substances 0.000 title claims abstract description 132
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 73
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims abstract description 64
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000000206 photolithography Methods 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 19
- 125000005842 heteroatom Chemical group 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 238000005566 electron beam evaporation Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- JKQOBWVOAYFWKG-UHFFFAOYSA-N molybdenum trioxide Inorganic materials O=[Mo](=O)=O JKQOBWVOAYFWKG-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66022—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6603—Diodes
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Abstract
The invention is suitable for the technical field of semiconductors, and provides a preparation method of a diamond Schottky diode, which comprises the following steps: forming a lightly doped p-type second diamond layer with a second thickness on the upper surface of the heavily doped p-type first diamond layer with the first thickness, wherein the second thickness is smaller than the first thickness; forming an electrode on a lower surface of the first diamond layer; forming a groove in the first region of the second diamond layer by photolithography and etching processes; forming an N-type heterogeneous semiconductor layer on the surface of the groove; forming a second metal layer on the surface of the N-type heterogeneous semiconductor layer; and forming a third metal layer on the surface of the second metal layer and the upper surface of the second region of the second diamond layer. The invention can obviously improve the performance of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a diamond Schottky diode.
Background
Power electronic systems are developing towards higher breakdown voltage and smaller conduction loss, and higher requirements are put on devices. Among them, the diode device is one of the most basic devices in power electronic systems.
The diamond has the advantages of wide forbidden band, high thermal conductivity, high critical breakdown electric field, low dielectric constant, high carrier mobility and the like, and is an ideal material for manufacturing high-power, high-frequency, high-temperature and low-power loss power electronic devices.
The conventional schottky diode has large loss and conduction loss, large conduction loss and small breakdown voltage, and cannot meet the requirements of power electronic systems which are developed day by day, so how to prepare the high-performance diamond schottky diode is a problem to be solved urgently at present.
Disclosure of Invention
In view of this, the embodiment of the invention provides a method for manufacturing a diamond schottky diode, so as to solve the problem that the performance of the diamond schottky diode is poor in the prior art.
The embodiment of the invention provides a preparation method of a diamond Schottky diode, which comprises the following steps:
forming a lightly doped p-type second diamond layer with a second thickness on the upper surface of the heavily doped p-type first diamond layer with the first thickness, wherein the second thickness is smaller than the first thickness;
forming an electrode on a lower surface of the first diamond layer;
forming a groove in the first region of the second diamond layer by photolithography and etching processes;
forming an N-type heterogeneous semiconductor layer on the surface of the groove;
forming a second metal layer on the surface of the N-type heterogeneous semiconductor layer;
and forming a third metal layer on the surface of the second metal layer and the upper surface of a second area of the second diamond layer, wherein the second area is an area of the second diamond layer except the first area.
Optionally, forming a lightly doped p-type second diamond layer with a second thickness on the upper surface of the heavily doped p-type first diamond layer with the first thickness includes:
depositing a heavily doped p-type first diamond layer with a first thickness on a diamond substrate by a microwave plasma chemical vapor deposition process;
depositing a second lightly doped p-type diamond layer of a second thickness on the upper surface of the first diamond layer by a microwave plasma chemical vapor deposition process;
and removing the diamond substrate.
Optionally, the forming an electrode on the lower surface of the first diamond layer includes:
depositing a first metal layer on the lower surface of the first diamond layer by an electron beam evaporation process;
and forming ohmic contact between the first metal layer and the first diamond layer by a high-temperature annealing process.
Optionally, the forming a groove in the first region of the second diamond layer by photolithography and etching processes includes:
covering a photoresist layer on the upper surface of the second region of the second diamond layer through a photoetching process;
and etching the second diamond layer to form the groove by a dry etching process, wherein the etching depth is less than the second thickness.
Further, the forming an N-type hetero semiconductor layer on the surface of the groove and forming a second metal layer on the surface of the N-type hetero semiconductor layer includes:
depositing an N-type heterogeneous semiconductor layer on the surface of the groove and the upper surface of the photoresist through an atomic layer deposition process;
depositing a second metal layer on the surface of the N-type heterogeneous semiconductor layer through an electron beam evaporation process;
and removing the photoresist layer.
And forming ohmic contact between the second metal layer and the N-type heterogeneous semiconductor layer by a high-temperature annealing process.
Optionally, the forming a third metal layer on the surface of the second metal layer and the upper surface of the second region of the second diamond layer includes:
depositing a third metal layer on the surface of the second metal layer and the upper surface of the second region of the second diamond layer by an electron beam evaporation process.
Optionally, the method further includes forming a metal layer made of Au on the upper surface of the third metal layer.
Optionally, the third metal layer is formed of a metal having a work function value of less than 4.6 eV.
Optionally, the first thickness is 50 micrometers to 2000 micrometers, the second thickness is 5 nanometers to 20 micrometers, and the doping concentration of the first diamond layer is 1 × 2018cm-3To 1 × 2022cm-3The doping concentration of the second diamond layer is 1 × 2014cm-3To 1 × 2018cm-3。
Optionally, the thickness of the N-type hetero semiconductor layer is 20 nm to 200 nm.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: in the embodiment of the invention, a lightly doped p-type second diamond layer with a second thickness is formed on the upper surface of a heavily doped p-type first diamond layer with a first thickness, an electrode is formed on the lower surface of the first diamond layer, a groove is formed in a first region of the second diamond layer through photoetching and etching processes, an N-type heterogeneous semiconductor layer and a second metal layer are sequentially formed on the surface of the groove, and a third metal layer is formed on the surface of the second metal layer and the upper surface of a second region of the second diamond layer. Compared with the traditional Schottky diode, the Schottky heterojunction barrier Schottky diode prepared by the method has high breakdown voltage and small conduction loss, and can remarkably improve the performance of the device.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a flow chart of an implementation of a method for manufacturing a diamond schottky diode according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a method for manufacturing a diamond schottky diode according to an embodiment of the present invention;
FIG. 3 is a band diagram of a hetero PN junction provided by an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a method for manufacturing a diamond schottky diode according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Referring to fig. 1 and 2, a method for manufacturing a diamond schottky diode includes:
step S101, forming a lightly doped p-type second diamond layer with a second thickness on the upper surface of the heavily doped p-type first diamond layer with the first thickness, wherein the second thickness is smaller than the first thickness.
In an embodiment of the present invention, referring to fig. 2(1), a second diamond layer 202 is formed on the upper surface of the first diamond layer 201, wherein the doping element of the first diamond layer 201 and the second diamond layer 202 is boron element to form p-type doping, and other elements may be doped to form p-type doping, which is not limited herein.
Step S102, forming an electrode on the lower surface of the first diamond layer.
In the embodiment of the present invention, referring to fig. 2(2), a metal is deposited on the lower surface of the first diamond layer 201 to form the anode electrode 203. The electrode 203 is an ohmic contact electrode, that is, the metal deposited on the lower surface of the first diamond layer 201 forms an ohmic contact with the first diamond layer 201.
Step S103, forming a groove in the first area of the second diamond layer through photoetching and etching processes.
In the embodiment of the present invention, referring to fig. 2(3), by using photolithography and etching processes, the second diamond layer 202 is etched with one or more grooves 204, and the grooves 204 include, but are not limited to, rectangular grooves, circular grooves, and oval grooves. When the groove 204 is plural, the first region is constituted by plural small regions, and one groove 204 is formed in each small region.
And step S104, forming an N-type heterogeneous semiconductor layer on the surface of the groove.
In the embodiment of the present invention, referring to fig. 2(4), the surface of the groove 204 includes a bottom surface and a sidewall, and an N-type hetero semiconductor layer 205 is deposited on the bottom surface and the sidewall of the groove 204. The N-type hetero semiconductor layer 205 includes, but is not limited to, N-type doped TiO2Layer, MoO3Layer, ZnO layer, V2O5Layer, WO3Layer, NbO5Layer, GaN layer, AlN layer, SiC layer, Ga2O3Layer, Si layer, GeSi layer, and GaAs layer. The N-type hetero semiconductor layer 205 forms a hetero junction PN junction structure with the second diamond layer 202. For example, referring to FIG. 3, FIG. 3 shows p-type diamond and N-type TiO2The band diagram of the heterojunction structure is formed, the forbidden band width of the diamond is 5.5eV, the diamond is doped with boron to form a p-type semiconductor, the energy level of the boron is about 0.37eV above the valence band of the diamond, and TiO is doped with the boron2Has a forbidden band width of 3.4eV and is TiO2It is naturally an N-type semiconductor, and as can be seen from FIG. 3, p-type diamond and N-type TiO2The energy band diagram of the formed heterojunction structure is similar to that of a traditional PN junction.
Step S105, forming a second metal layer on the surface of the N-type heterogeneous semiconductor layer.
In an embodiment of the invention, referring to fig. 2(5), a second metal layer 206 is deposited on the surface of the N-type hetero semiconductor layer 205 in the recess 204, wherein the second metal layer 206 includes but is not limited to Ti, Pt, Al, Ni, Ir, or a combination of two or more thereof. The second metal layer 206 forms an ohmic contact with the N-type hetero semiconductor layer 205.
Step S106, forming a third metal layer on the surface of the second metal layer and the upper surface of a second region of the second diamond layer, where the second region is a region of the second diamond layer except the first region.
In the embodiment of the present invention, referring to fig. 2(6), a third metal layer 207 is deposited on the surface of the second metal layer 206 in the groove 204 and the upper surface of the region of the second diamond layer 202 outside the groove, and the portion of the third metal layer 207 contacting the second diamond layer 202 forms a schottky contact to serve as a cathode schottky electrode. The third metal layer 206 is made of a metal material having a low work function, including but not limited to Ti, Al, and Ni.
In the embodiment of the invention, a lightly doped p-type second diamond layer 202 with a second thickness is formed on the upper surface of a heavily doped p-type first diamond layer 201 with a first thickness, an electrode 203 is formed on the lower surface of the first diamond layer 201, a groove 204 is formed in a first region of the second diamond layer 202 through photoetching and etching processes, an N-type heterogeneous semiconductor layer 205 and a second metal layer 206 are sequentially formed on the bottom surface and the side wall of the groove 204, and a third metal layer 206 is formed on the bottom surface and the side wall of the groove 204 and the upper surface of a second region of the second diamond layer 202 after the second metal layer is formed. The second diamond layer 202 and the N-type hetero semiconductor layer 205 form a PN junction, so that the diamond heterojunction barrier Schottky diode is prepared.
Optionally, the specific implementation manner of step S101 is: depositing a heavily doped p-type first diamond layer with a first thickness on a diamond substrate by a microwave plasma chemical vapor deposition process; depositing a second lightly doped p-type diamond layer of a second thickness on the upper surface of the first diamond layer by a microwave plasma chemical vapor deposition process; and removing the diamond substrate.
Optionally, the first thickness is 50 to 2000 micrometers, the second thickness is 5 to 20 micrometers, and the doping concentration of the first diamond layer is 1 × 2018cm-3To 1 × 2022cm-3The doping concentration of the second diamond layer is 1 × 2014cm-3To 1 × 2018cm-3。
In the embodiment of the invention, the diamond substrate is an insulating high-resistance substrate, a first diamond layer 201 with the thickness of 50-2000 micrometers and a second diamond layer 202 with the thickness of 5-20 micrometers are sequentially grown on the diamond substrate by a microwave plasma chemical vapor deposition process, and the diamond substrate is removed by mechanical polishing, wherein the first diamond layer 201 is heavily doped, and the doping concentration is 1 × 2018cm-3To 1 × 2022cm-3The second diamond layer 202 was lightly doped with a doping concentration of 1 × 2014cm-3To 1 × 2018cm-3。
Optionally, the specific implementation manner of step S102 is: depositing a first metal layer on the lower surface of the first diamond layer by an electron beam evaporation process; and forming ohmic contact between the first metal layer and the first diamond layer by a high-temperature annealing process.
In the embodiment of the present invention, a first metal layer is deposited on the lower surface of the first diamond layer 201 by an electron beam evaporation process and annealed in a vacuum atmosphere or an inert gas atmosphere at 400 to 1200 c to form an ohmic contact as the anode electrode 203.
Further, the specific implementation manner of step S103 is: covering a photoresist layer on the upper surface of the second region of the second diamond layer through a photoetching process; and etching the second diamond layer to form the groove by a dry etching process, wherein the etching depth is less than the second thickness.
In the embodiment of the present invention, please refer to fig. 4(1) and fig. 4(2), first, a photoresist layer 401 is covered on the upper surface of a second region of the second diamond layer 202 by a photolithography process, wherein the first region is a region where the groove 204 is formed in the second diamond layer 202, and the second region is a region outside the region where the groove 204 is formed in the second diamond layer 202. And etching the second metal layer 202 by a dry etching process, wherein the second diamond layer 202 of the second region is not etched because the second region is protected by the photoresist, and the second diamond layer 202 of the first region is etched away to form a groove 204.
Further, the specific implementation manner of step S104 and step S105 is: depositing an N-type heterogeneous semiconductor layer on the surface of the groove and the upper surface of the photoresist through an atomic layer deposition process; depositing a second metal layer on the surface of the N-type heterogeneous semiconductor layer through an electron beam evaporation process; removing the photoresist layer; and forming ohmic contact between the second metal layer and the N-type heterogeneous semiconductor layer by a high-temperature annealing process.
In the embodiment of the invention, referring to fig. 4(3), an N-type hetero semiconductor layer 205 is deposited on the surface of the groove 204 and the upper surface of the photoresist layer 401 by an atomic deposition process, wherein the surface of the groove 204 includes the bottom surface and the sidewalls of the groove 204.
Referring to fig. 4(4) and 4(5), a second metal layer 206 is deposited on the surface of the N-type hetero semiconductor layer 205 by an electron beam evaporation process, the photoresist layer 401 is stripped by a photoresist stripping technique, the N-type hetero semiconductor layer 205 and the second metal layer 206 on the upper surface of the photoresist layer 401 are also removed to form the structure shown in fig. 4(5), and finally the second metal layer 206 and the N-type hetero semiconductor layer 205 form an ohmic contact by a high temperature annealing process.
Optionally, the specific implementation manner of step S106 is: depositing a third metal layer on the surface of the second metal layer and the upper surface of the second region of the second diamond layer by an electron beam evaporation process.
Optionally, the method further includes forming a metal layer made of Au on the upper surface of the third metal layer. Since the resistivity of Au is low, the resistance of the diode can be reduced by depositing a layer of Au on the upper surface of the third metal layer.
Optionally, the third metal layer is formed of a metal having a work function value of less than 4.6 eV. The work function is a work function, the magnitude of the work function indicates the strength of the confinement of electrons in the metal, and the larger the work function is, the less easily the electrons leave the metal. The metal forming the third metal layer has a relatively low work function, so that the schottky barrier formed has a better rectifying characteristic.
Optionally, the thickness of the N-type hetero semiconductor layer is 20 nm to 200 nm.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A preparation method of a diamond Schottky diode is characterized by comprising the following steps:
forming a lightly doped p-type second diamond layer with a second thickness on the upper surface of the heavily doped p-type first diamond layer with the first thickness, wherein the second thickness is smaller than the first thickness;
forming an electrode on a lower surface of the first diamond layer;
forming a groove in the first region of the second diamond layer by photolithography and etching processes;
forming an N-type heterogeneous semiconductor layer on the surface of the groove;
forming a second metal layer on the surface of the N-type heterogeneous semiconductor layer;
forming a third metal layer on the surface of the second metal layer and the upper surface of a second region of the second diamond layer, the second region being a region of the second diamond layer except the first region;
the surface of the groove is specifically the bottom surface and the side wall of the groove.
2. The method of forming a diamond schottky diode as in claim 1 wherein forming a second lightly doped p-type diamond layer of a second thickness on the top surface of the first heavily doped p-type diamond layer of a first thickness comprises:
depositing a heavily doped p-type first diamond layer with a first thickness on a diamond substrate by a microwave plasma chemical vapor deposition process;
depositing a second lightly doped p-type diamond layer of a second thickness on the upper surface of the first diamond layer by a microwave plasma chemical vapor deposition process;
and removing the diamond substrate.
3. The method of manufacturing a diamond schottky diode according to claim 1, wherein the forming of the electrode on the lower surface of the first diamond layer comprises:
depositing a first metal layer on the lower surface of the first diamond layer by an electron beam evaporation process;
and forming ohmic contact between the first metal layer and the first diamond layer by a high-temperature annealing process.
4. The method of forming a diamond schottky diode according to claim 1, wherein the forming a groove in the first region of the second diamond layer by the photolithography and etching process comprises:
covering a photoresist layer on the upper surface of the second region of the second diamond layer through a photoetching process;
and etching the second diamond layer to form the groove by a dry etching process, wherein the etching depth is less than the second thickness.
5. The method for preparing a diamond schottky diode according to claim 4, wherein the forming of the N-type hetero semiconductor layer on the surface of the groove and the forming of the second metal layer on the surface of the N-type hetero semiconductor layer comprises:
depositing an N-type heterogeneous semiconductor layer on the surface of the groove and the upper surface of the photoresist through an atomic layer deposition process;
depositing a second metal layer on the surface of the N-type heterogeneous semiconductor layer through an electron beam evaporation process;
removing the photoresist layer;
and forming ohmic contact between the second metal layer and the N-type heterogeneous semiconductor layer by a high-temperature annealing process.
6. The method of forming a diamond schottky diode according to claim 1 wherein forming a third metal layer on the surface of the second metal layer and the upper surface of the second region of the second diamond layer comprises:
depositing a third metal layer on the surface of the second metal layer and the upper surface of the second region of the second diamond layer by an electron beam evaporation process.
7. The method of forming a diamond schottky diode according to claim 1 further comprising forming a metal layer of Au on the top surface of the third metal layer.
8. The method of making a diamond schottky diode of claim 1 wherein the third metal layer is formed from a metal having a work function value of less than 4.6 eV.
9. The method of claim 1, wherein the first thickness is 50 to 2000 microns, the second thickness is 5 to 20 microns, and the doping concentration of the first diamond layer is 1 × 2018cm-3To 1 × 2022cm-3The doping concentration of the second diamond layer is 1 × 2014cm-3To 1 × 2018cm-3。
10. The method of manufacturing a diamond schottky diode according to any one of claims 1 to 9, wherein the thickness of the N-type hetero semiconductor layer is 20 nm to 200 nm.
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| CN110504329A (en) * | 2019-07-24 | 2019-11-26 | 中山大学 | A kind of preparation method of low on-resistance high voltage diamond power diode |
| CN113838817A (en) * | 2021-09-29 | 2021-12-24 | 太原理工大学 | Preparation method of diamond-based gallium nitride heterojunction diode device |
| CN114335238B (en) * | 2021-12-02 | 2024-01-30 | 航天科工(长沙)新材料研究院有限公司 | Electrode structure of diamond particle detector and preparation method thereof |
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| CN103400853A (en) * | 2013-08-01 | 2013-11-20 | 电子科技大学 | Silicon carbide Schottky barrier diode and manufacturing method thereof |
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