CN105552108A - Forming method of non-alloy ohmic contact of GaN HEMT device - Google Patents
Forming method of non-alloy ohmic contact of GaN HEMT device Download PDFInfo
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- CN105552108A CN105552108A CN201510896812.3A CN201510896812A CN105552108A CN 105552108 A CN105552108 A CN 105552108A CN 201510896812 A CN201510896812 A CN 201510896812A CN 105552108 A CN105552108 A CN 105552108A
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000000956 alloy Substances 0.000 title abstract 2
- 229910045601 alloy Inorganic materials 0.000 title abstract 2
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000005036 potential barrier Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 10
- 238000009616 inductively coupled plasma Methods 0.000 claims description 7
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 230000004888 barrier function Effects 0.000 abstract 2
- 239000013078 crystal Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 47
- 229910002601 GaN Inorganic materials 0.000 description 46
- 238000005516 engineering process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
- H01L29/454—Ohmic electrodes on AIII-BV compounds on thin film AIII-BV compounds
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a forming method of non-alloy ohmic contact of a GaN HEMT device. The method comprises the steps of: forming a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer successively on a Si substrate; deposing a SiO2 medium on the surface of the AlGaN barrier layer, covering the SiO2 medium with a mask layer, and using a photoetching process to form ohmic contact areas and a non-ohmic-contact area on the mask layer, wherein the ohmic contact areas are arranged at two sides of the non-ohmic-contact area; carrying out etching on the SiO2 medium exposed in the ohmic contact areas so as to form a channel embedded in the GaN channel layer; growing a n+GaN doped layer in the channel; removing the mask layer and the SiO2 medium; and deposing an ohmic contact metal layer corresponding to a GaN material on the ohmic contact areas and the non-ohmic-contact area. By adopting the method provided by the invention, damages of high-temperature annealing to GaN crystal lattices are avoided.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly relate to a kind of manufacture method of GaNHEMT device non-alloyed ohmic contact.
Background technology
Development decades of silicon base chip experience, Si based CMOS devices size constantly reduces, and its frequency performance but improves constantly, when characteristic size reaches 25nm, its f
t490GHz can be reached.But the Johnson figure of merit of Si material is only 0.5THzV, and reducing of size makes the puncture voltage of Si based CMOS devices much smaller than 1V, this greatly limits the application of silicon base chip in very high speed digital field.
In recent years, people constantly find the substitute of Si material, because wide bandgap semiconductor gallium nitride (GaN) material has the Johnson figure of merit (can reach 5THzV) of superelevation, when its device channel size reaches 10nm magnitude, puncture voltage still can remain on about 10V, therefore, GaN material causes gradually and payes attention to widely both at home and abroad.Along with, GaN material require high conversion efficiency and accurate threshold control, broadband, great dynamic range circuit (as ultra broadband ADC, DAC) digital and electronic field there is wide and special application prospect, GaN base logical device has become the focus of Speed Semiconductor area research in recent years, just becoming the contenders of Si base CMOS high speed circuit in the follow-up developments in digital-to-analogue and radio circuit field, be the sophisticated technology that state key is supported, can be rated as " heart " of information industry.
At present, conventional GaN device is higher due to the work function of GaN cap, if cannot realize good ohmic contact, device power will be caused to fail serious, in order to address this problem, and, industry adopts high annealing mode to realize ohmic contact usually.But the temperature of high annealing mode reaches 850 degree, so high temperature can bring damage to GaN lattice, causes electric leakage and the current collapse phenomenon of GaN device, have impact on the reliability of GaN device.Therefore, the ohmic contact implementation of conventional GaN device hinders the Main Bottleneck of the raising of GaN device performance and practical application.
Summary of the invention
The technical problem that the present invention mainly solves is to provide a kind of manufacture method of GaNHEMT device non-alloyed ohmic contact, can avoid the damage that high annealing brings GaN lattice.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: the manufacture method providing a kind of GaNHEMT device non-alloyed ohmic contact, comprise: from bottom to top form GaN resilient coating, GaN channel layer and AlGaN potential barrier successively on a si substrate, wherein, two-dimensional electron gas is formed with between described GaN channel layer and AlGaN potential barrier; At described AlGaN potential barrier surface deposition SiO
2medium, and at described SiO
2mask film covering layer on medium, adopt photoetching process to form ohmic contact regions and non-ohmic contact region on described mask layer, wherein, described ohmic contact regions is positioned at both sides, described non-ohmic contact region; To the SiO exposed in described ohmic contact regions
2medium etches, to form the groove embedding described GaN channel layer inside; Grow n+GaN doped layer in the trench; Remove described mask layer and described SiO
2medium; The ohmic contact metal layer that deposition is corresponding with the work function of GaN material on described ohmic contact regions and described non-ohmic contact region.
Preferably, the doping content of described n+GaN doped layer is 1 × 10
19-5 × 10
19.
Preferably, described ohmic contact metal layer is single or multiple lift structure.
Preferably, the described mask layer of described removal and described SiO
2in medium, described mask layer and described SiO
2medium adopts buffered oxide etch agent BOE solution to corrode.
Preferably, described SiO
2medium using plasma strengthens chemical vapour deposition technique pecvd process deposition and obtains.
Preferably, described SiO
2medium adopts inductively coupled plasma ICP technique to etch.
Preferably, described n+GaN doped layer adopts the growth of metallo-organic compound deposition MOCVD technique.
Be different from the situation of prior art, the invention has the beneficial effects as follows:
1. can improve the reliability of GaNHEMT device.
2. can reduce the surface of ohmic contact part and the roughness at edge, be conducive to subsequent technique.
3. due to the existence of n+GaN doped layer, the little order of magnitude of ohmic contact resistance that ohmic contact resistance can realize than conventional high temperature annealing.
4.n+GaN doped layer provides compression can to GaN channel layer, effectively improves the concentration of two-dimensional electron gas in raceway groove.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of embodiment of the present invention GaNHEMT device non-alloyed ohmic contact.
Fig. 2-Fig. 7 is the manufacturing process schematic diagram adopting the manufacture method of the embodiment of the present invention to make GaNHEMT device.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
See Fig. 1, it is the schematic diagram of the manufacture method of embodiment of the present invention GaNHEMT device non-alloyed ohmic contact.The manufacture method of the GaNHEMT device non-alloyed ohmic contact of the present embodiment comprises the following steps:
S1: from bottom to top form GaN resilient coating, GaN channel layer and AlGaN potential barrier successively on a si substrate, wherein, be formed with two-dimensional electron gas between GaN channel layer and AlGaN potential barrier.
Wherein, as shown in Figure 2, Si substrate 1, GaN resilient coating 2, GaN channel layer 3 and the structure of AlGaN potential barrier 4 for stacking gradually, two-dimensional electron gas 31 is formed between GaN channel layer 3 and AlGaN potential barrier 4.GaN channel layer 3 and AlGaN potential barrier 4 can form AlGaN/GaN heterojunction.
S2: at AlGaN potential barrier surface deposition SiO
2medium, and at SiO
2mask film covering layer on medium, adopt photoetching process on mask layer, form ohmic contact regions and non-ohmic contact region, wherein, ohmic contact regions is positioned at both sides, non-ohmic contact region.
Wherein, as shown in Figure 3, SiO
2medium 5 exposes in ohmic contact regions 61, and the SiO in non-ohmic contact region 62
2medium 5 is covered by mask layer 6, and ohmic contact regions 61 is positioned at marginal position, and non-ohmic contact region 62 is positioned at centre position.Alternatively, SiO
2medium 5 adopts PECVD (PlasmaEnhancedChemicalVaporDeposition, plasma enhanced chemical vapor deposition method) process deposits to obtain.The material of mask layer 6 can be photoresist.
S3: to exposing the SiO in ohmic contact regions
2medium etches, to form the groove embedding GaN channel layer inside.
Wherein, as shown in Figure 4, groove 21 gos deep into GaN channel layer 3 inside.Alternatively, SiO
2medium 5 adopts ICP (InductivelyCoupledPlasma, inductively coupled plasma) technique to etch.
S4: grow n+GaN doped layer in the trench.
Wherein, as shown in Figure 5, n+GaN doped layer 7 grows in groove 21, and the height of n+GaN doped layer 7 is concordant with AlGaN potential barrier 4.Alternatively, n+GaN doped layer 7 adopts MOCVD (Metal-organicChemicalVaporDeposition, metallo-organic compound deposits) technique growth, and is adopt self-aligned technology in growth.N+GaN doped layer 7 provides tunelling electrons can to the source electrode of follow-up formation on n+GaN doped layer 7 and drain region, forms non-alloyed ohmic contact.Further, n+GaN doped layer 7 can form compression to raceway groove, thus improves the concentration of two-dimensional electron gas.
In the present embodiment, n+GaN doped layer 7 is highly doped, and its doping content can be 1 × 10
19-5 × 10
19.
S5: remove mask layer and SiO
2medium.
Wherein, as shown in Figure 6, mask layer 6 and SiO
2after medium 5 is removed, expose n+GaN doped layer 7 and AlGaN potential barrier 4 completely.Alternatively, at removal mask layer 6 and SiO
2in medium 5 step, mask layer 6 and SiO
2medium 5 adopts BOE (buffered oxide etch agent) solution to corrode.
S6: the ohmic contact metal layer that deposition is corresponding with the work function of GaN material on ohmic contact regions and non-ohmic contact region.
Wherein, as shown in Figure 7, ohmic contact metal layer 41 covers n+GaN doped layer 7 and AlGaN potential barrier 4.Alternatively, ohmic contact metal layer 41 is single or multiple lift structure, such as, be Ti/Al/Ni/Au structure.
By the way, the manufacture method of the GaNHEMT device non-alloyed ohmic contact of the embodiment of the present invention passes through the mode of regrowth n+GaN doped layer in the trench, only need process annealing can form good ohmic contact, thus the damage that high annealing brings GaN lattice can be avoided, the reliability of GaNHEMT device can be improved, improve the concentration of raceway groove two-dimensional electron gas, for more extensive, more complicated numeral and radio circuit is integrated has established good basis, have and be easy to realize, the advantages such as the low and reliability of cost is strong, be easy at microwave, adopt in millimeter wave compound semiconductor circuit production and promote.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (7)
1. a manufacture method for GaNHEMT device non-alloyed ohmic contact, is characterized in that, comprising:
From bottom to top form GaN resilient coating, GaN channel layer and AlGaN potential barrier successively on a si substrate, wherein, between described GaN channel layer and AlGaN potential barrier, be formed with two-dimensional electron gas;
At described AlGaN potential barrier surface deposition SiO
2medium, and at described SiO
2mask film covering layer on medium, adopt photoetching process to form ohmic contact regions and non-ohmic contact region on described mask layer, wherein, described ohmic contact regions is positioned at both sides, described non-ohmic contact region;
To the SiO exposed in described ohmic contact regions
2medium etches, to form the groove embedding described GaN channel layer inside;
Grow n+GaN doped layer in the trench;
Remove described mask layer and described SiO
2medium;
The ohmic contact metal layer that deposition is corresponding with the work function of GaN material on described ohmic contact regions and described non-ohmic contact region.
2. manufacture method according to claim 1, is characterized in that, the doping content of described n+GaN doped layer is 1 × 10
19-5 × 10
19.
3. manufacture method according to claim 1, is characterized in that, described ohmic contact metal layer is single or multiple lift structure.
4. manufacture method according to claim 1, is characterized in that, the described mask layer of described removal and described SiO
2in medium, described mask layer and described SiO
2medium adopts buffered oxide etch agent BOE solution to corrode.
5. manufacture method according to claim 1, is characterized in that, described SiO
2medium using plasma strengthens chemical vapour deposition technique pecvd process deposition and obtains.
6. manufacture method according to claim 1, is characterized in that, described SiO
2medium adopts inductively coupled plasma ICP technique to etch.
7. manufacture method according to claim 1, is characterized in that, described n+GaN doped layer adopts the growth of metallo-organic compound deposition MOCVD technique.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510896812.3A CN105552108A (en) | 2015-12-07 | 2015-12-07 | Forming method of non-alloy ohmic contact of GaN HEMT device |
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|---|---|---|---|
| CN201510896812.3A CN105552108A (en) | 2015-12-07 | 2015-12-07 | Forming method of non-alloy ohmic contact of GaN HEMT device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107993934A (en) * | 2017-12-08 | 2018-05-04 | 中国科学院微电子研究所 | Method for enhancing ohmic contact of gallium oxide semiconductor device |
| CN108493111A (en) * | 2018-06-01 | 2018-09-04 | 苏州汉骅半导体有限公司 | Method, semi-conductor device manufacturing method |
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|---|---|---|---|---|
| US20030129820A1 (en) * | 2001-10-16 | 2003-07-10 | Wladyslaw Walukiewicz | Co-implantation of group VI elements and N for formation of non-alloyed Ohmic contacts for n-type semiconductors |
| CN1998085A (en) * | 2004-05-20 | 2007-07-11 | 克里公司 | Methods of fabricating nitride-based transistors having regrown ohmic contact regions and nitride-based transistors having regrown ohmic contact regions |
| CN103797581A (en) * | 2011-07-18 | 2014-05-14 | 埃皮根股份有限公司 | Method for growing iii-v epitaxial layers and semiconductor structure |
-
2015
- 2015-12-07 CN CN201510896812.3A patent/CN105552108A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030129820A1 (en) * | 2001-10-16 | 2003-07-10 | Wladyslaw Walukiewicz | Co-implantation of group VI elements and N for formation of non-alloyed Ohmic contacts for n-type semiconductors |
| CN1998085A (en) * | 2004-05-20 | 2007-07-11 | 克里公司 | Methods of fabricating nitride-based transistors having regrown ohmic contact regions and nitride-based transistors having regrown ohmic contact regions |
| CN103797581A (en) * | 2011-07-18 | 2014-05-14 | 埃皮根股份有限公司 | Method for growing iii-v epitaxial layers and semiconductor structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107993934A (en) * | 2017-12-08 | 2018-05-04 | 中国科学院微电子研究所 | Method for enhancing ohmic contact of gallium oxide semiconductor device |
| CN107993934B (en) * | 2017-12-08 | 2020-09-11 | 中国科学院微电子研究所 | Method for enhancing ohmic contact of gallium oxide semiconductor device |
| CN108493111A (en) * | 2018-06-01 | 2018-09-04 | 苏州汉骅半导体有限公司 | Method, semi-conductor device manufacturing method |
| US11049718B2 (en) | 2018-06-01 | 2021-06-29 | Suzhou Han Hua Semiconductor Co., Ltd. | Fabrication of group III-nitride semiconductor devices |
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