CN105552108A - Forming method of non-alloy ohmic contact of GaN HEMT device - Google Patents

Abstract

The present invention provides a GaN? A method for making non-alloy ohmic contacts of HEMT devices. It includes sequentially forming a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer on a Si substrate; depositing a SiO ₂ medium on the surface of the AlGaN barrier layer, and covering a mask layer on the SiO ₂ medium; An ohmic contact area and a non-ohmic contact area are formed on the mask layer, wherein the ohmic contact area is located on both sides of the non-ohmic contact area; the _SiO2 dielectric exposed in the ohmic contact area is etched to form an embedded GaN channel layer. The trench; grow n+GaN doped layer in the trench; remove the mask layer and SiO ₂ medium; deposit an ohmic contact metal layer corresponding to the work function of the GaN material on the ohmic contact area and the non-ohmic contact area. The invention can avoid damage to GaN crystal lattice caused by high temperature annealing.

Description

Fabrication method of non-alloy ohmic contact of GaN HEMT device

technical field

The invention relates to the technical field of semiconductor devices, in particular to a method for manufacturing non-alloy ohmic contacts of GaNHEMT devices.

Background technique

After decades of development of silicon-based chips, the size of Si-based CMOS devices has been continuously reduced, but its frequency performance has been continuously improved. When the feature size reaches 25nm, its f _T can reach 490GHz. However, the Johnson figure of merit of Si material is only 0.5THzV, and the reduction in size makes the breakdown voltage of Si-based CMOS devices far less than 1V, which greatly limits the application of silicon-based chips in the ultra-high-speed digital field.

In recent years, people are constantly looking for substitutes for Si materials. Since the wide-bandgap semiconductor Gallium Nitride (GaN) material has an ultra-high Johnson figure of merit (up to 5THzV), when the device channel size reaches the order of 10nm, it will hit The breakdown voltage can still be maintained at about 10V, therefore, GaN materials have gradually attracted widespread attention at home and abroad. As GaN materials have broad and special application prospects in the field of digital electronics that require high conversion efficiency and precise threshold control, broadband, and large dynamic range circuits (such as ultra-wideband ADCs, DACs), GaN-based logic devices have become a popular choice in recent years. The hotspot in the field of ultra-high-speed semiconductor research is becoming a strong competitor in the subsequent development of Si-based CMOS high-speed circuits in the field of digital-analog and radio-frequency circuits. It is a cutting-edge technology supported by the state and can be called the "heart" of the information industry.

At present, due to the high work function of the GaN cap layer of conventional GaN devices, if a good ohmic contact cannot be achieved, the power of the device will be severely degraded. In order to solve this problem, the industry usually uses high-temperature annealing to achieve ohmic contact. However, the temperature of the high temperature annealing method reaches 850 degrees. Such a high temperature will cause damage to the GaN lattice, causing leakage and current collapse of the GaN device, and affecting the reliability of the GaN device. Therefore, the ohmic contact implementation of conventional GaN devices is the main bottleneck hindering the performance improvement and practical application of GaN devices.

Contents of the invention

The main technical problem to be solved by the present invention is to provide a method for manufacturing non-alloy ohmic contacts of GaNHEMT devices, which can avoid damage to GaN lattice caused by high-temperature annealing.

In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a method for fabricating a non-alloy ohmic contact of a GaNHEMT device, comprising: sequentially forming a GaN buffer layer, a GaN channel layer and a GaN channel layer on a Si substrate from bottom to top. An AlGaN barrier layer, wherein a two-dimensional electron gas is formed between the GaN channel layer and the AlGaN barrier layer; a SiO ₂ medium is deposited on the surface of the AlGaN barrier layer, and a mask is covered on the SiO ₂ medium A film layer, forming an ohmic contact area and a non-ohmic contact area on the mask layer by using a photolithography process, wherein the ohmic contact area is located on both sides of the non-ohmic contact area; The SiO ₂ medium is etched to form a trench embedded in the GaN channel layer; an n+GaN doped layer is grown in the trench; the mask layer and the SiO ₂ medium are removed; An ohmic contact metal layer corresponding to the work function of the GaN material is deposited on the ohmic contact area and the non-ohmic contact area.

Preferably, the doping concentration of the n+GaN doped layer is 1×10 ¹⁹ -5×10 ¹⁹ .

Preferably, the ohmic contact metal layer is a single-layer or multi-layer structure.

Preferably, in the removal of the mask layer and the SiO ₂ medium, the mask layer and the SiO ₂ medium are etched using a buffered oxide etchant BOE solution.

Preferably, the SiO ₂ medium is deposited by plasma enhanced chemical vapor deposition (PECVD).

Preferably, the SiO ₂ medium is etched by an inductively coupled plasma ICP process.

Preferably, the n+GaN doped layer is grown by metal organic compound deposition MOCVD process.

Being different from the situation of the prior art, the beneficial effects of the present invention are:

1. It can improve the reliability of GaNHEMT devices.

2. The roughness of the surface and edge of the ohmic contact part can be reduced, which is beneficial to the subsequent process.

3. Due to the existence of the n+GaN doped layer, the ohmic contact resistance will be an order of magnitude smaller than that achieved by conventional high-temperature annealing.

4. The n+GaN doped layer can provide compressive stress to the GaN channel layer, effectively increasing the concentration of two-dimensional electron gas in the channel.

Description of drawings

FIG. 1 is a schematic flowchart of a method for fabricating a non-alloy ohmic contact of a GaNHEMT device according to an embodiment of the present invention.

FIG. 2-FIG. 7 are schematic diagrams of the fabrication process of GaNHEMT devices fabricated using the fabrication method of the embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Referring to FIG. 1 , it is a schematic diagram of a method for fabricating a non-alloy ohmic contact of a GaNHEMT device according to an embodiment of the present invention. The fabrication method of the GaNHEMT device non-alloy ohmic contact of the present embodiment comprises the following steps:

S1: A GaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially formed on a Si substrate from bottom to top, wherein a two-dimensional electron gas is formed between the GaN channel layer and the AlGaN barrier layer.

Among them, as shown in Fig. 2, the Si substrate 1, the GaN buffer layer 2, the GaN channel layer 3 and the AlGaN barrier layer 4 are sequentially stacked, and the two-dimensional electron gas 31 is formed between the GaN channel layer 3 and the AlGaN barrier layer. Between barrier layers 4. The GaN channel layer 3 and the AlGaN barrier layer 4 will form an AlGaN/GaN heterojunction.

S2: Deposit SiO ₂ medium on the surface of AlGaN barrier layer, and cover the mask layer on the SiO ₂ medium, and use photolithography to form ohmic contact area and non-ohmic contact area on the mask layer, wherein the ohmic contact area is located in the non-ohmic contact area. Both sides of the ohmic contact area.

Wherein, as shown in Figure 3, the _SiO2 dielectric 5 is exposed in the ohmic contact region 61, while the _SiO2 dielectric 5 in the non-ohmic contact region 62 is covered by the mask layer 6, the ohmic contact region 61 is located at the edge position, and the non-ohmic contact region 62 is covered by the mask layer 6. Region 62 is located in the middle. Optionally, the SiO ₂ medium 5 is deposited by PECVD (PlasmaEnhancedChemicalVaporDeposition, plasma enhanced chemical vapor deposition) process. The material of the mask layer 6 may be photoresist.

S3: Etching the SiO ₂ dielectric exposed in the ohmic contact region to form a trench embedded in the GaN channel layer.

Wherein, as shown in FIG. 4 , the trench 21 goes deep into the GaN channel layer 3 . Optionally, the SiO ₂ medium 5 is etched using an ICP (Inductively Coupled Plasma, Inductively Coupled Plasma) process.

S4: growing an n+GaN doped layer in the trench.

Wherein, as shown in FIG. 5 , the n+GaN doped layer 7 is grown in the trench 21 , and the height of the n+GaN doped layer 7 is even with the AlGaN barrier layer 4 . Optionally, the n+GaN doped layer 7 is grown by MOCVD (Metal-organic Chemical Vapor Deposition, metal-organic compound deposition) process, and self-alignment technology is used during growth. The n+GaN doped layer 7 can provide tunneling electrons to the source and drain regions subsequently formed on the n+GaN doped layer 7 to form a non-alloy ohmic contact. Moreover, the n+GaN doped layer 7 can form compressive stress on the channel, thereby increasing the concentration of the two-dimensional electron gas.

In this embodiment, the n+GaN doped layer 7 is highly doped, and its doping concentration may be 1×10 ¹⁹ -5×10 ¹⁹ .

S5: removing the mask layer and the SiO ₂ dielectric.

Wherein, as shown in FIG. 6 , after the mask layer 6 and the SiO ₂ dielectric 5 are removed, the n+GaN doped layer 7 and the AlGaN barrier layer 4 are completely exposed. Optionally, in the step of removing the mask layer 6 and the SiO ₂ dielectric 5, the mask layer 6 and the SiO ₂ dielectric 5 are etched with a BOE (buffered oxide etchant) solution.

S6: Depositing an ohmic contact metal layer corresponding to the work function of the GaN material on the ohmic contact region and the non-ohmic contact region.

Wherein, as shown in FIG. 7 , the ohmic contact metal layer 41 covers the n+GaN doped layer 7 and the AlGaN barrier layer 4 . Optionally, the ohmic contact metal layer 41 is a single-layer or multi-layer structure, such as a Ti/Al/Ni/Au structure.

Through the above method, the method for fabricating the non-alloy ohmic contact of the GaNHEMT device in the embodiment of the present invention only needs low-temperature annealing to form a good ohmic contact by regrowing the n+GaN doped layer in the trench, thereby avoiding high temperature The damage caused by annealing to the GaN lattice can improve the reliability of GaNHEMT devices, increase the concentration of two-dimensional electron gas in the channel, and lay a good foundation for larger-scale and more complex digital and radio frequency circuit integration. It is easy to implement, It has the advantages of low cost and strong reliability, and is easy to adopt and popularize in the production of microwave and millimeter wave compound semiconductor circuits.

The above is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process conversion made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in other related technologies fields, all of which are equally included in the scope of patent protection of the present invention.

Claims (7)

1. a manufacture method for GaNHEMT device non-alloyed ohmic contact, is characterized in that, comprising:

From bottom to top form GaN resilient coating, GaN channel layer and AlGaN potential barrier successively on a si substrate, wherein, between described GaN channel layer and AlGaN potential barrier, be formed with two-dimensional electron gas;

At described AlGaN potential barrier surface deposition SiO ₂medium, and at described SiO ₂mask film covering layer on medium, adopt photoetching process to form ohmic contact regions and non-ohmic contact region on described mask layer, wherein, described ohmic contact regions is positioned at both sides, described non-ohmic contact region;

To the SiO exposed in described ohmic contact regions ₂medium etches, to form the groove embedding described GaN channel layer inside;

Grow n+GaN doped layer in the trench;

Remove described mask layer and described SiO ₂medium;

The ohmic contact metal layer that deposition is corresponding with the work function of GaN material on described ohmic contact regions and described non-ohmic contact region.

2. manufacture method according to claim 1, is characterized in that, the doping content of described n+GaN doped layer is 1 × 10 ¹⁹-5 × 10 ¹⁹.

3. manufacture method according to claim 1, is characterized in that, described ohmic contact metal layer is single or multiple lift structure.

4. manufacture method according to claim 1, is characterized in that, the described mask layer of described removal and described SiO ₂in medium, described mask layer and described SiO ₂medium adopts buffered oxide etch agent BOE solution to corrode.

5. manufacture method according to claim 1, is characterized in that, described SiO ₂medium using plasma strengthens chemical vapour deposition technique pecvd process deposition and obtains.

6. manufacture method according to claim 1, is characterized in that, described SiO ₂medium adopts inductively coupled plasma ICP technique to etch.

7. manufacture method according to claim 1, is characterized in that, described n+GaN doped layer adopts the growth of metallo-organic compound deposition MOCVD technique.