CN114497186A - Preparation method of diamond/gallium oxide heterogeneous pn junction diode - Google Patents
Preparation method of diamond/gallium oxide heterogeneous pn junction diode Download PDFInfo
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- CN114497186A CN114497186A CN202111669320.2A CN202111669320A CN114497186A CN 114497186 A CN114497186 A CN 114497186A CN 202111669320 A CN202111669320 A CN 202111669320A CN 114497186 A CN114497186 A CN 114497186A
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 64
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 64
- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 50
- 239000010432 diamond Substances 0.000 title claims abstract description 50
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 16
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052742 iron Inorganic materials 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052593 corundum Inorganic materials 0.000 claims description 2
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000004913 activation Effects 0.000 abstract description 2
- 125000005842 heteroatom Chemical group 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 39
- 239000000463 material Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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Abstract
The invention discloses a preparation method of a diamond/gallium oxide heterogeneous pn junction diode, which comprises the following steps: extending a lightly doped p-type diamond epitaxial layer on a highly doped p-type diamond substrate; manufacturing a selective epitaxial mask; growing a lightly doped n-type gallium oxide epitaxial layer and a highly doped n-type gallium oxide epitaxial layer; stripping the gallium oxide epitaxial layer; and preparing front-side and back-side ohmic contacts. The invention develops a preparation method of a diamond hetero/gallium oxide ultra-wide bandgap heterogeneous pn junction diode based on a gallium oxide selective epitaxial growth technology aiming at the problems of high resistance of an n-type doped region and large on-resistance of a device caused by low n-type doping activation rate of the existing pn junction type diamond diode, and has the advantages of low on-resistance of the device, high breakdown voltage, good high-temperature stability and the like.
Description
Technical Field
The invention belongs to the technical field of semiconductor device preparation, and particularly relates to a preparation method of a diamond/gallium oxide heterogeneous pn junction diode.
Background
The diamond has excellent material characteristics of ultra-wide forbidden band, high breakdown electric field, high thermal conductivity and the like, and is a preferred material for preparing high-performance electronic devices. However, the diamond doping difficulty is high, particularly the activation rate of n-type doping is extremely low, so that the conductivity of n-type diamond is very low, and the development of diamond pn junction devices is severely restricted. Gallium oxide is also an ultra-wide bandgap semiconductor material with breakdown fields as high as 8 MV/cm. In contrast to diamond, gallium oxide is difficult to dope p-type, and no breakthrough is made at present.
Disclosure of Invention
The invention provides a preparation method of a diamond/gallium oxide heterogeneous pn junction diode by a gallium oxide heterogeneous epitaxial growth technology aiming at the problem that the existing pn junction type diamond device has high series resistance of the device due to high resistance of an n-type doping region, has the characteristics of low on-resistance, high voltage resistance, good high-temperature stability and high current bearing capacity, and can be applied to the development and production of diode power switching devices and related devices.
The technical scheme for realizing the invention is as follows: a preparation method of a diamond/gallium oxide heterojunction diode comprises the following steps:
step 4, removing the mask layer and the lightly doped n-type gallium oxide epitaxial layer and the highly doped n-type gallium oxide epitaxial layer on the mask layer by a stripping method;
and 6, defining a gallium oxide ohmic contact area by utilizing the photoresist through photoetching and developing processes, then depositing gallium oxide ohmic contact metal, stripping to form an ohmic electrode, and annealing to form ohmic contact.
Compared with the prior art, the invention has the following remarkable advantages: (1) the on-resistance of the device is low; (2) the breakdown voltage is high; (3) the high-temperature stability is good; (4) the forward bearing current capability is high.
Drawings
FIG. 1 is a schematic diagram of the structure of a diamond/gallium oxide heterojunction diode.
FIGS. 2(a) -2 (i) are flow charts of the preparation of diamond/gallium oxide heterojunction diodes.
Detailed Description
The n-type doping technology is mature and widely applied to gallium oxide Schottky diodes and gallium oxide MOSFET devices. The n-type gallium oxide can be obtained by growing on a foreign substrate in various modes such as laser pulse deposition, magnetron sputtering, chemical vapor deposition and the like. Therefore, the invention develops a preparation method of a diamond/gallium oxide heterogeneous pn junction diode based on a gallium oxide heterogeneous epitaxial growth technology on diamond, and the diamond/gallium oxide heterogeneous pn junction diode device with low on-resistance, high voltage resistance, good high-temperature stability and high current bearing capacity can be realized by the technology.
With reference to fig. 1, fig. 2(a) to fig. 2(i), the present invention provides a method for manufacturing a diamond/gallium oxide heterojunction diode, comprising performing a lightly doped diamond epitaxial layer on a highly doped diamond substrate; preparing a selective epitaxial mask; selective epitaxial growth of lightly doped and highly doped gallium oxide; stripping the gallium oxide epitaxial layer; and preparing front-side and back-side ohmic contacts. The specific method comprises the following steps:
step 4, removing the mask layer 3 and the lightly doped n-type gallium oxide epitaxial layer 5 and the highly doped n-type gallium oxide epitaxial layer 6 on the mask layer by a stripping method;
and 6, defining a gallium oxide ohmic contact area by using the photoresist 8 through conventional photoetching and developing processes, depositing gallium oxide ohmic contact metal 9, stripping by using organic solution such as acetone to form an ohmic electrode, and annealing to form ohmic contact.
Further, the highly doped diamond substrate 1 is monocrystalline or polycrystalline, the doping type is p-type, and the doping concentration is higher than 1E19cm-3The doping type of the lightly doped diamond epitaxial layer 2 is p type, and the doping concentration is 1E14cm-3To 1E18cm-3To (c) to (d);
further, the mask layer 3 is Si3N4、SiO2、Al2O3Or a single-layer or multi-layer dielectric or metal structure such as Ni, Ir, etc.;
further, the gallium oxide epitaxial method in the step 3 is laser pulse deposition, magnetron sputtering, chemical vapor deposition or molecular beam epitaxy, and the doping concentration of the lightly doped n-type gallium oxide epitaxial layer 5 is 1E14cm-3To 1E18cm-3Meanwhile, the doping concentration of the high-doped n-type gallium oxide epitaxial layer 6 is higher than 1E19cm-3；
Further, in step 5, the diamond ohmic contact layer 7 is one or a combination of more of Ti, Al, Au, Pt, Ni, Mo, Cu, Ag, Pd, W, and Fe, the thickness is 10nm to 1 μm, the annealing atmosphere is nitrogen, and the annealing temperature is 400 ℃ to 800 ℃;
further, in step 6, the gallium oxide ohmic contact metal 9 is one or a combination of Ti, Al, Au, Pt, Ni, Mo, Cu, Ag, Pd, W, Fe, and has a thickness of 10nm to 1 μm, an annealing atmosphere of nitrogen, and an annealing temperature of 400 ℃ to 800 ℃.
The present invention will be described in detail below with reference to the accompanying drawings and examples.
Examples
A preparation method of a diamond/gallium oxide heterojunction pn diode comprises the following steps:
(1) 1 mu m doping concentration of 1 x 10 is grown on a clean highly doped p-type doped diamond substrate 117cm-3P-type diamond epitaxial layer 2 as shown in fig. 2 (a);
(2) growing SiO with thickness of 5 μm on the surface of the sample2 A mask layer 3, defining an etching region by using photoresist 4 through conventional photoetching and developing processes, and etching SiO in the region without photoresist protection2 A mask layer 3, which is formed by removing the photoresist 4 through organic cleaning such as acetone, as shown in fig. 2(b), 2(c), and 2 (d);
(3) with the remaining SiO2The mask layer 3 is used as a mask to sequentially grow 1 μm of doping concentration of 1 × 1017cm-3And a lightly doped n-type gallium oxide epitaxial layer 5 and a doping concentration of 1 μm of 5 × 1019cm-3As shown in fig. 2(e), a highly doped n-type gallium oxide epitaxial layer 6;
(4) SiO removal by hydrofluoric acid stripping2 A mask layer 3 and gallium oxide epitaxial layers 5 and 6 thereon, as shown in fig. 2 (f);
(5) depositing 20/500nm Ti/Au diamond ohmic contact metal layer 7 on the back of the sample, and annealing at 700 ℃ in a nitrogen atmosphere to form ohmic contact, as shown in FIG. 2 (g);
(6) the gallium oxide ohmic contact region is defined by photoresist 8 through conventional photoetching and developing processes, then 20/500nm Ti/Au gallium oxide ohmic contact metal 9 is deposited, an ohmic electrode is formed by stripping with an organic solution such as acetone, and the ohmic contact is formed by annealing at 470 ℃ in a nitrogen atmosphere, as shown in FIGS. 2(h) and 2 (i).
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A preparation method of a diamond/gallium oxide heterojunction diode is characterized by comprising the following steps:
step 1, growing a lightly doped p-type diamond epitaxial layer (2) on a clean highly doped p-type diamond substrate (1);
step 2, growing a mask layer (3) on the surface of the sample, defining an etching area by using a photoresist (4) through photoetching and developing processes, then etching the mask layer (3) without the photoresist protection area, and removing the photoresist (4);
step 3, growing a lightly doped n-type gallium oxide epitaxial layer (5) and a highly doped n-type gallium oxide epitaxial layer (6) in sequence by taking the residual mask layer (3) as a mask;
step 4, removing the mask layer (3) and the lightly doped n-type gallium oxide epitaxial layer (5) and the highly doped n-type gallium oxide epitaxial layer (6) on the mask layer by a stripping method;
step 5, depositing a diamond ohmic contact metal layer (7) on the back surface of the sample, and annealing to form ohmic contact;
and 6, defining a gallium oxide ohmic contact area by using a photoresist (8) through photoetching and developing processes, then depositing gallium oxide ohmic contact metal (9), stripping to form an ohmic electrode, and annealing to form ohmic contact.
2. The method for preparing a diamond/gallium oxide heterojunction diode as claimed in claim 1 wherein said highly doped p-type diamond substrate (1) is monocrystalline or polycrystalline with a doping concentration higher than 1E19cm-3。
3. The method for preparing a diamond/gallium oxide heterojunction diode as claimed in claim 1, wherein the doping concentration of said lightly doped p-type diamond epitaxial layer (2) is 1E14cm-3To 1E18cm-3In the meantime.
4. A method of manufacturing a diamond/gallium oxide heterojunction diode according to claim 1, wherein in step 2, the photoresist (4) is removed by acetone; in step 6, ohmic electrodes were formed by acetone lift-off.
5. The method for preparing a diamond/gallium oxide heterojunction diode as claimed in claim 1, wherein said mask layer (3) is Si3N4、SiO2、Al2O3Ni or Ir.
6. The method of claim 1, wherein the gallium oxide epitaxy process in step 3 is laser pulse deposition, magnetron sputtering, chemical vapor deposition, or molecular beam epitaxy.
7. The method for preparing a diamond/gallium oxide heterojunction diode as claimed in claim 1, wherein the doping concentration of said lightly doped n-type gallium oxide epitaxial layer (5) is 1E14cm-3To 1E18cm-3In the meantime.
8. The method for preparing a diamond/gallium oxide heterojunction diode as claimed in claim 1, wherein the doping concentration of said highly doped n-type gallium oxide epitaxial layer (6) is higher than 1E19cm-3。
9. The method of claim 1, wherein in step 5, the diamond ohmic contact metal layer (7) is one or more of Ti, Al, Au, Pt, Ni, Mo, Cu, Ag, Pd, W, Fe in a thickness of 10nm to 1 μm, the annealing atmosphere is nitrogen, and the annealing temperature is between 400 ℃ and 800 ℃.
10. The method of claim 1, wherein in step 6, the gallium oxide ohmic contact metal (9) is one or a combination of Ti, Al, Au, Pt, Ni, Mo, Cu, Ag, Pd, W, Fe with a thickness of 10nm to 1 μm, the annealing atmosphere is nitrogen, and the annealing temperature is between 400 ℃ and 800 ℃.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116387152A (en) * | 2023-06-06 | 2023-07-04 | 江苏能华微电子科技发展有限公司 | Low-damage gallium nitride Schottky diode and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116387152A (en) * | 2023-06-06 | 2023-07-04 | 江苏能华微电子科技发展有限公司 | Low-damage gallium nitride Schottky diode and preparation method thereof |
| CN116387152B (en) * | 2023-06-06 | 2023-12-22 | 江苏能华微电子科技发展有限公司 | Low-damage gallium nitride Schottky diode and preparation method thereof |
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