TWI838037B - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a non-native substrate, a middle bonding layer configured on the non-native substrate, a gallium nitride base layer configured on the middle bonding layer and a semiconductor heterostructure formed on the gallium nitride base layer. The gallium nitride base layer has a mean carbon doping concentration between 8×10¹⁶cm^-3 to 1×10¹⁸cm^-3. The semiconductor heterostructure includes a gallium nitride carrier channel layer and an aluminum gallium nitride carrier barrier layer formed over the gallium nitride channel layer, in which a 2D electron gas is formed between the gallium nitride channel layer and the aluminum gallium nitride carrier barrier layer. The semiconductor device shows high voltage by using the non-native substrate with great thermal conductance.

Description

Semiconductor components

The present invention relates to a semiconductor element and a semiconductor epitaxial wafer, in particular to a semiconductor element disposed on a non-native substrate and a semiconductor epitaxial wafer having a two-dimensional material layer.

With the rise of smart grids, power equipment such as charging piles used in electric vehicles, converters derived from solar and wind energy, etc., must have the characteristics of withstanding high voltage. Therefore, in order to meet market demand, power semiconductors with wide bandgap are the focus of current research.

It is known that the substrate materials that can be used for high-voltage power semiconductors include silicon, silicon carbide and sapphire. However, if gallium nitride is to be grown on the above-mentioned substrate materials, the silicon substrate cannot further increase the voltage due to the defects of the material itself; the sapphire substrate has the problem of poor thermal conductivity; and the silicon carbide substrate cannot be used for mass production due to its high cost.

The known substrate release technologies for gallium nitride semiconductors include substrate removal by grinding, optical stripping (i.e. laser stripping) and mechanical stress stripping. However, grinding removal requires high costs; optical stripping and mechanical stress stripping are mainly used in light-emitting diodes, but are not suitable for power semiconductors with high voltage characteristics. Furthermore, the aforementioned grinding and mechanical stress stripping methods may produce defect centers, which usually have the function of donors, so they are not suitable for use in power semiconductors.

One aspect of the present invention is to provide a semiconductor device that is a gallium nitride power device configured on a non-native substrate.

Another aspect of the present invention is to provide a semiconductor epitaxial wafer, which includes a two-dimensional material layer between a gallium nitride power element and a growth substrate.

According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a non-native substrate, an intermediate bonding layer disposed on the non-native substrate, a gallium nitride base layer disposed on the intermediate bonding layer, and a semiconductor heterostructure formed on the gallium nitride base layer. The gallium nitride base layer has an average carbon doping concentration of 8×10 ¹⁶ cm ^-3 to 1×10 ¹⁸ cm ^-3 . The semiconductor heterostructure includes a gallium nitride carrier channel layer and an aluminum gallium nitride carrier barrier layer formed on the gallium nitride carrier channel layer, wherein a two-dimensional electron gas (2DEG) is formed between the gallium nitride carrier channel layer and the aluminum gallium nitride carrier barrier layer.

According to one embodiment of the present invention, the semiconductor element further comprises a p-type doped semiconductor layer formed on a semiconductor heterostructure, wherein the semiconductor heterostructure is located between the gallium nitride base layer and the p-type doped semiconductor layer.

According to one embodiment of the present invention, the semiconductor device further comprises an intrinsic gallium nitride layer formed on the aluminum gallium nitride carrier barrier layer, wherein the intrinsic gallium nitride layer is located between the p-type doped semiconductor layer and the semiconductor heterostructure.

According to one embodiment of the present invention, the non-native substrate is selected from the group consisting of molybdenum, tungsten, molybdenum-copper alloy, tungsten-copper alloy, silicon and silicon carbide.

According to one embodiment of the present invention, the intermediate bonding layer comprises metal bonding, oxide bonding or metal eutectic bonding to bond two adjacent layers.

According to one embodiment of the present invention, the thickness of the above-mentioned gallium nitride base layer is not more than 5μm.

According to one embodiment of the present invention, the semiconductor element is a Schottky Barrier Diode (SBD) or a High Electron Mobility Transistor (HEMT).

According to another aspect of the present invention, a semiconductor epitaxial wafer is provided. The semiconductor epitaxial wafer includes a growth substrate, a first flat layer formed on the growth substrate, a two-dimensional material layer formed on the growth substrate, a gallium nitride base layer formed on the two-dimensional material layer, and a semiconductor heterostructure formed on the gallium nitride base layer. The growth substrate is a sapphire substrate or a silicon carbide substrate. The first flat layer includes aluminum nitride or aluminum gallium nitride. The semiconductor heterostructure includes a gallium nitride carrier channel layer and an aluminum gallium nitride carrier barrier layer formed on the gallium nitride carrier channel layer, wherein a two-dimensional electron gas is formed between the gallium nitride carrier channel layer and the aluminum gallium nitride carrier barrier layer.

According to one embodiment of the present invention, the above-mentioned two-dimensional material layer is formed on the first flat layer.

According to one embodiment of the present invention, the semiconductor epitaxial wafer further includes a second flat layer formed between the two-dimensional material layer and the gallium nitride base layer, wherein the second flat layer includes aluminum nitride or aluminum gallium nitride.

According to one embodiment of the present invention, the first flat layer is formed on the two-dimensional material layer.

According to an embodiment of the present invention, the two-dimensional material layer includes graphene, molybdenum disulfide (MoS ₂ ), tungsten disulfide (WS ₂ ), molybdenum diselenide (MoSe ₂ ) or tungsten diselenide (WSe ₂ ).

According to one embodiment of the present invention, the above-mentioned two-dimensional material layer includes multiple layers of two-dimensional material, and the multiple layers of two-dimensional material are no more than 6 layers.

According to one embodiment of the present invention, the thickness of the above-mentioned gallium nitride base layer is not more than 5μm.

According to one embodiment of the present invention, the gallium nitride base layer has an average carbon doping concentration of 8×10 ¹⁶ cm ^-3 to 1×10 ¹⁸ cm ^-3 .

The semiconductor device of the present invention is applied by transferring the gallium nitride power device to a non-native substrate through a two-dimensional material layer to realize a power semiconductor device with high voltage characteristics, and has the advantages of good thermal conductivity and low cost.

100,200,300:Semiconductor epitaxial wafer

110: Growth substrate

120: First flat layer

125: Second flat layer

130: Two-dimensional material layer

140: Gallium nitride power element

145: Gallium nitride base layer

150: Semiconductor heterostructure

152: Gallium nitride carrier channel layer

154: Aluminum-gallium nitride carrier barrier layer

156: Intrinsic gallium nitride layer

160: p-type doped semiconductor layer

410:Metal stress layer

420: Tape layer

500,600,700,800: semiconductor components

510: Non-native substrate

520: Middle bonding layer

740: Gallium nitride power element

750: Semiconductor heterostructure

756: Intrinsic gallium nitride layer

760: p-type doped semiconductor layer

761: First P-type nitride layer

762: Second P-type nitride layer

790a: First electrode

790c: Second electrode

840: Gallium nitride power element

850: Semiconductor heterostructure

856: Intrinsic gallium nitride layer

860: p-type doped semiconductor layer

865: Gate insulation layer

890d: Drain

890g: Gate

890s: Source

The following detailed description and accompanying drawings will provide a better understanding of the present disclosure. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[Figure 1] shows a cross-sectional view of a semiconductor epitaxial wafer according to some embodiments of the present invention.

[Figure 2] shows a cross-sectional view of a semiconductor epitaxial wafer according to other embodiments of the present invention.

[Figure 3] shows a cross-sectional view of a semiconductor epitaxial wafer according to other embodiments of the present invention.

[FIG. 4A] and [FIG. 4B] illustrate cross-sectional views of intermediate stages of a process of transferring a semiconductor epitaxial wafer to a non-native substrate according to some embodiments of the present invention.

[Figure 5] shows a cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[Figure 6] shows a cross-sectional view of a semiconductor device according to some other embodiments of the present invention.

[Figure 7] shows a cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[Figure 8] shows a cross-sectional view of a semiconductor device according to some embodiments of the present invention.

The following disclosure provides many different embodiments or examples to implement different features of the invention. The specific examples of components and configurations described below are intended to simplify the disclosure. These are of course only examples and are not intended to be limiting. For example, a description of a first feature formed on or above a second feature includes embodiments in which the first feature and the second feature are in direct contact, and also includes embodiments in which other features are formed between the first feature and the second feature, so that the first feature and the second feature are not in direct contact. In addition, the disclosure repeats component symbols and/or letters in various specific examples. The purpose of this repetition is to simplify and clarify the description and does not indicate a relationship between the various discussed embodiments and/or configurations.

Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", etc., are used to easily describe the relationship between a part or feature shown in a figure and other parts or features. Spatially relative terms include different orientations of the element when it is in use or operation in addition to the orientation depicted in the figure. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used in this disclosure can also be interpreted in this way.

As used in the present invention, "around", "about", "approximately" or "substantially" generally means within 20%, within 10%, or within 5% of the value or range described.

As mentioned above, the present invention prepares a semiconductor epitaxial wafer by preparing a gallium nitride power element on a two-dimensional material layer of a suitable growth substrate. Then, the gallium nitride power element in the semiconductor epitaxial wafer is peeled off by the two-dimensional material layer and transferred to a substrate with thermal conductivity, and the gallium nitride power element is bonded to the substrate using an intermediate bonding layer. In this way, a high-voltage gallium nitride power semiconductor element on a thermally conductive substrate can be obtained.

Please refer to FIG. 1, which shows a cross-sectional view of a semiconductor epitaxial wafer 100 according to some embodiments of the present invention. The semiconductor epitaxial wafer 100 includes a growth substrate 110, a first flat layer 120, a two-dimensional material layer 130, and a gallium nitride power device 140. The gallium nitride power device 140 includes a gallium nitride base layer 145 and a semiconductor heterostructure 150.

0.5)，其中氮化鋁的效果優於氮化鋁鎵，所以採用氮化鋁製成的第一平坦層120有利於成長出品質較佳的氮化鎵基礎層145。 In some embodiments, the growth substrate 110 is a sapphire substrate or a silicon carbide substrate, preferably a sapphire substrate. The first flat layer 120 is formed on the growth substrate 110 to serve as a horizontal nucleation layer, which is beneficial to the subsequent growth of the gallium nitride base layer 145 (described below). In some embodiments, the first flat layer 120 comprises aluminum nitride or aluminum gallium nitride (Al _x Ga _(1-x) N, where x>0, preferably x

0.5), wherein the effect of aluminum nitride is better than that of aluminum gallium nitride, so the first flat layer 120 made of aluminum nitride is conducive to growing a gallium nitride base layer 145 with better quality.

In some embodiments, the first flat layer 120 can be grown on the growth substrate 110 by physical vapor deposition (PVD), preferably by sputtering. Sputtering is suitable for depositing the first flat layer 120 because of its advantages such as better deposition efficiency, easy control of large-scale deposition thickness, precise composition control and lower manufacturing cost. In some embodiments, the first flat layer 120 is grown by sputtering at a low temperature of about 400° C. to about 600° C. (e.g., about 550° C.) to a thickness of about 100 nm. Since the first flat layer 120 is grown on a flat growth substrate 110, the first flat layer 120 formed by sputtering at the above growth temperature is basically grown in a two-dimensional manner so that the first flat layer 120 has a relatively small grain size. In some embodiments, the above-mentioned grain size is less than about 20nm. In some embodiments, the root mean square roughness (RMS roughness) of the first flat layer 120 is about 1Å to about 10Å. It should be noted that the first flat layer 120 of the present embodiment is not formed by, for example, Metal-Organic Chemical Vapor Deposition (MOCVD), because MOCVD cannot form a first flat layer 120 with a flat surface.

The two-dimensional material layer 130 is grown on the first flat layer 120. In some embodiments, the two-dimensional material layer 130 includes at least one layer of two-dimensional material, for example, 1 to 6 layers. If the two-dimensional material layer 130 includes more than 6 layers of two-dimensional material, during the process of growing the gallium nitride base layer 145, the gallium nitride base layer 145 is difficult to grow according to the lattice of the first flat layer 120, thereby affecting the function of the gallium nitride power device 140, and may even cause the gallium nitride power device 140 to fail.

In some embodiments, the two-dimensional material layer 130 includes graphene, molybdenum disulfide (MoS ₂ ), tungsten disulfide (WS ₂ ), molybdenum diselenide (MoSe ₂ ) or tungsten diselenide (WSe ₂ ) or other two-dimensional materials of transition metal chalcogenides. It should be noted that the two-dimensional material layer 130 is not suitable to include nitrogen-based materials (such as hexagonal boron nitride (h-BN)) because the nitrogen-based materials will form bonds with the aluminum nitride or aluminum gallium nitride of the first flat layer 120, thereby affecting the subsequent structure growth.

In some embodiments, metal organic chemical vapor deposition (MOCVD) can be used to form the two-dimensional material layer 130. In some embodiments where the two-dimensional material layer 130 is graphene, it can be formed by chemical vapor deposition (CVD) or growth on SiC or other suitable methods. In addition to being directly grown on the growth substrate 110, the two-dimensional material layer 130 can also be formed on the growth substrate 110 by transfer.

在上式中，Di代表第i個碳摻雜氮化鎵層的厚度，Ci代表第i個碳摻雜氮化鎵層的碳摻雜濃度，而T為N個碳摻雜氮化鎵層的總厚度，例如氮化鎵基礎層145的整體厚度。此外，N與i皆為正整數，且N大於1，而i代表碳摻雜氮化鎵層的編號。 The gallium nitride power device 140 is formed on the two-dimensional material layer 130. The gallium nitride power device 140 includes a gallium nitride base layer 145 formed on the two-dimensional material layer 130 and a semiconductor heterostructure 150 formed on the gallium nitride base layer 145. In some embodiments, the gallium nitride base layer 145 is formed by metal organic chemical vapor deposition (MOCVD), for example, at a temperature of about 1000° C. The gallium nitride base layer 145 includes at least one carbon-doped gallium nitride layer. In other words, the gallium nitride base layer 145 may be a single carbon-doped gallium nitride layer or multiple carbon-doped gallium nitride layers. Specifically, the gallium nitride base layer 145 may include N carbon-doped gallium nitride layers stacked on each other, and the N carbon-doped gallium nitride layers satisfy the following mathematical formula:

In the above formula, Di represents the thickness of the i-th carbon-doped gallium nitride layer, Ci represents the carbon doping concentration of the i-th carbon-doped gallium nitride layer, and T is the total thickness of N carbon-doped gallium nitride layers, such as the total thickness of the gallium nitride base layer 145. In addition, N and i are both positive integers, and N is greater than 1, and i represents the number of the carbon-doped gallium nitride layer.

In some embodiments, the average carbon doping concentration of the gallium nitride base layer 145 is about 8×10 ¹⁶ cm ^-3 to about 1×10 ¹⁸ cm ^-3 , preferably about 1×10 ¹⁷ cm ^-3 to about 8×10 ¹⁷ cm ^-3 .

Since the thickness of the two-dimensional material layer 130 is very thin, the gallium nitride base layer 145 can grow according to the lattice of the first flat layer 120. In some embodiments, the thickness of the gallium nitride base layer 145 is not more than about 5μm, preferably not more than about 3μm, for example, about 2μm or about 1.5μm. If the thickness of the gallium nitride base layer 145 is too high (for example, greater than about 5μm), when there is a temperature change in the subsequent process or application, the epitaxial film will bend due to the lattice stress difference, and the voltage characteristics in the semiconductor heterostructure 150 will be uneven (affecting the two-dimensional electron gas), and may even cause stress peeling of the two-dimensional material layer 130 below.

By using the flat first flat layer 120, the gallium nitride base layer 145 can be grown at a higher temperature. The gallium nitride base layer 145 does not need to have a too high carbon doping concentration and can have an insulating effect and a flat surface.

The semiconductor heterostructure 150 includes a gallium nitride carrier channel layer 152 and an aluminum gallium nitride carrier barrier layer 154 formed on the gallium nitride carrier channel layer 152. A two-dimensional electron gas (2DEG) is formed between the gallium nitride carrier channel layer 152 and the aluminum gallium nitride carrier barrier layer 154. The two-dimensional electron gas is horizontally distributed and can serve as a channel for carrier transmission so that electrical signals can be transmitted in the horizontal direction. In some embodiments, the semiconductor heterostructure 150 further includes an intrinsic gallium nitride layer 156 on the aluminum gallium nitride carrier barrier layer 154, that is, the aluminum gallium nitride carrier barrier layer 154 is between the gallium nitride carrier channel layer 152 and the intrinsic gallium nitride layer 156. In some embodiments, the carbon doping concentration of the intrinsic gallium nitride layer 156 is less than or equal to about 6×10 ¹⁶ cm ^-3 .

In some embodiments, the gallium nitride power device 140 further includes a p-type doped semiconductor layer 160 on the semiconductor heterostructure 150, that is, the semiconductor heterostructure 150 is located between the gallium nitride base layer 145 and the p-type doped semiconductor layer 160.

FIG. 2 and FIG. 3 are cross-sectional views of a semiconductor epitaxial wafer 200 and a semiconductor epitaxial wafer 300 according to other embodiments of the present invention. Referring to FIG. 2 , the semiconductor epitaxial wafer 200 has a similar configuration to the semiconductor epitaxial wafer 100 in FIG. 1 , except that the first flat layer 120 in FIG. 2 is formed on the two-dimensional material layer 130. In other words, the two-dimensional material layer 130 of the semiconductor epitaxial wafer 200 is located between the growth substrate 110 and the first flat layer 120. Since the two-dimensional material layer 130 is only a two-dimensional material of no more than 6 layers, the first flat layer 120 can grow according to the lattice of the growth substrate 110. In some embodiments, the thickness of the first flat layer 120 can be about 50 nm. The gallium nitride base layer 145 is directly grown on the first planar layer 120, and in some embodiments, the thickness of the gallium nitride base layer 145 is not more than about 5μm, preferably not more than 3μm, such as about 2.5μm.

Referring to FIG. 3 , the semiconductor epitaxial wafer 300 has a similar configuration to the semiconductor epitaxial wafer 100 , except that the semiconductor epitaxial wafer 300 has a second flat layer 125 on the two-dimensional material layer 130 in addition to the first flat layer 120 between the growth substrate 110 and the two-dimensional material layer 130 , that is, the two-dimensional material layer 130 is located between the first flat layer 120 and the second flat layer 125 . The gallium nitride power element 140 is formed on the second flat layer 125 .

In some embodiments, the second planar layer 125 and the first planar layer 120 may have the same material, lattice, and formation method. For example, the second planar layer 125 also includes aluminum nitride or aluminum gallium nitride (Al _x Ga _(1-x) N, where x>0), preferably aluminum nitride, and the second planar layer 125 and the first planar layer 120 may be formed by sputtering. In some embodiments, the thickness of the first planar layer 120 is about 100 nm, and the thickness of the second planar layer 125 is about 50 nm. In this embodiment, the thickness of the gallium nitride base layer 145 is not more than about 5 μm, preferably not more than 3 μm, for example, about 3 μm.

Since the number of the two-dimensional material layer 130 is not more than 6 layers, the gallium nitride base layer 145 can be grown according to the lattice of the second flat layer 125. In addition, since the second flat layer 125 and the first flat layer 120 have the same lattice, the gallium nitride base layer 145 on the second flat layer 125 is actually grown according to the lattice of the first flat layer 120.

It should be understood that both the semiconductor epitaxial wafer 200 and the semiconductor epitaxial wafer 300 have a first flat layer 120 (or a second flat layer 125) on the two-dimensional material layer 130, so the first flat layer 120 (or the second flat layer 125) will be retained in the semiconductor device manufactured after the stripping process, which will be described in detail below.

4A and 4B are cross-sectional views showing the intermediate stages of the process of transferring the semiconductor epitaxial wafer 100 to the non-native substrate 510 according to some embodiments of the present invention. Referring to FIG. 4A , a metal stress layer 410 is deposited on the gallium nitride power element 140 of the semiconductor epitaxial wafer 100. Thereafter, a layer of tape 420 is placed on the metal stress layer 410. In some embodiments, the metal stress layer 410 comprises nickel or titanium-nickel alloy, which can be formed by deposition or electroplating to a thickness of about 25 μm. In other embodiments, the metal stress layer 410 comprises a polymer. In some embodiments, a wafer substrate (such as a silicon wafer, not shown) can be selectively connected to the tape layer 420 to facilitate subsequent stripping and connection processes. Therefore, the tape layer 420 can also be a double-sided tape adhered to the wafer substrate and the metal stress layer 410.

Next, referring to FIG. 4A and FIG. 4B , the gallium nitride power device 140 of the semiconductor epitaxial wafer 100 in FIG. 4A is peeled off from the two-dimensional material layer 130 and transferred to the non-native substrate 510. Since the two-dimensional material layer 130 has only a weak van der Waals force in the vertical direction, it is easy to separate the gallium nitride power device 140 from the first flat layer 120 on the growth substrate 110. It should be noted that after the gallium nitride power device 140 is peeled off, the remaining growth substrate 110 can be reused to save costs. In some embodiments, the non-native substrate 510 includes materials with good thermal conductivity such as tungsten copper (WCu) alloy, molybdenum copper (MoCu) alloy, silicon (Si), molybdenum (Mo), tungsten (W) or silicon carbide.

The non-native substrate 510 and the gallium nitride power device 140 must be connected via an intermediate bonding layer 520, and the intermediate bonding layer 520 includes metal bonding (such as copper-copper metal bonding), oxide bonding (such as silicon dioxide bonding), metal eutectic bonding (such as gold-tin eutectic) or metal sintering (such as nano-copper sintering) to bond the non-native substrate 510 and the gallium nitride base layer 145. It should be noted that if the metal has a higher mobility, such as silver sintering, it is not suitable for the intermediate bonding layer 520 of the specific embodiment of the present invention, because the silver may diffuse into the gallium nitride power device 140. Therefore, before the gallium nitride power device 140 is transferred to the non-native substrate 510, a bonding process must be performed on the non-native substrate 510 according to the bonding type of the intermediate bonding layer 520. According to the bonding bonding type of the intermediate bonding layer 520, metal or oxide is deposited or electroplated on the non-native substrate 510 and under the gallium nitride base layer 145 of the gallium nitride power device 140, and then the two are bonded using appropriate temperature and pressure.

For example, if the non-native substrate 510 is a silicon substrate, silicon dioxide with a thickness of, for example, about 100 nm can be first deposited or thermally oxidized on the non-native substrate 510, and silicon dioxide with a thickness of, for example, about 60 nm can be deposited under the gallium nitride base layer 145 of the stripped gallium nitride power element 140, so that the two are bonded by oxide bonding.

Please refer to FIG. 5, which is a cross-sectional view of a semiconductor device 500 according to some embodiments of the present invention. The tape layer 420 and the metal stress layer 410 in FIG. 4B are removed in sequence to obtain the semiconductor device 500. The semiconductor device 500 includes a non-native substrate 510, an intermediate bonding layer 520 on the non-native substrate 510, and a gallium nitride power device 140 on the intermediate bonding layer 520. As described above, the gallium nitride power device 140 includes a gallium nitride base layer 145, a gallium nitride carrier channel layer 152, an aluminum gallium nitride carrier barrier layer 154, an intrinsic gallium nitride layer 156, and a p-type doped semiconductor layer 160.

Please refer to FIG. 6, which is a cross-sectional view of a semiconductor device 600 according to other embodiments of the present invention. The semiconductor device 600 is formed by transferring the semiconductor epitaxial wafer 200 or the semiconductor epitaxial wafer 300 to the non-native substrate 510, and the transfer method is the same as the method described above with reference to FIG. 4A and FIG. 4B. The semiconductor device 600 is substantially the same as the semiconductor device 500, and the difference is that the semiconductor device 600 further includes a first planar layer 120 (or a second planar layer 125) between the intermediate bonding layer 520 and the gallium nitride base layer 145. Since the semiconductor epitaxial wafer 200 and the semiconductor epitaxial wafer 300 respectively have the first flat layer 120 and the second flat layer 125 on the two-dimensional material layer 130, when the gallium nitride power element 140 is peeled off, the first flat layer 120 (or the second flat layer 125) above the two-dimensional material layer 130 will be attached to the gallium nitride base layer 145. Therefore, the intermediate bonding layer 520 of the semiconductor element 600 is bonded by metal or oxide deposited or electroplated on the non-native substrate 510 and under the first flat layer 120 (or the second flat layer 125).

Please refer to FIG. 7, which is a cross-sectional view of a semiconductor device 700 according to some embodiments of the present invention. The semiconductor device 700 is a Schottky Barrier Diode (SBD), which has an extremely high breakdown electrode and can withstand a voltage of about 3000 volts or more. The semiconductor device 700 has a similar configuration to the semiconductor device 600, that is, the semiconductor device 700 also includes a non-native substrate 510, an intermediate bonding layer 520, a first flat layer 120, a gallium nitride base layer 145 and a semiconductor heterostructure 750, but the intrinsic gallium nitride layer 756 in the semiconductor heterostructure 750 does not completely cover the aluminum gallium nitride carrier barrier layer 154.

The p-type doped semiconductor layer 760 of the semiconductor device 700 includes a first p-type nitride layer 761 and a second p-type nitride layer 762 on the first p-type nitride layer 761. In some embodiments, the chemical formulas of the first p-type nitride layer 761 and the second p-type nitride layer 762 may be _{AlxInyGa (1-xy) N} , and 1≧x≧0, 1≧y≧0, so at least one of the first p-type nitride layer 761 and the second p-type nitride layer 762 may include indium gallium nitride, gallium nitride or aluminum indium gallium nitride. The functions of the second p-type nitride layer 762 include energy level adjustment and charge balance under reverse bias. In some embodiments, the second P-type nitride layer 762 does not completely cover the first P-type nitride layer 761.

In addition, the semiconductor device 700 further includes a first electrode 790a and a second electrode 790c. The first electrode 790a is disposed on the gallium nitride carrier channel layer 152 and passes through the p-type doped semiconductor layer 760, the intrinsic gallium nitride layer 756 and a portion of the aluminum gallium nitride carrier barrier layer 154; and the second electrode 790c is disposed on the aluminum gallium nitride carrier barrier layer 154. The first electrode 790a is an anode, and the second electrode 790c is a cathode. The first electrode 790a can form a Schottky barrier with the gallium nitride carrier channel layer 152, and the second electrode 790c can form an ohmic contact with the aluminum gallium nitride carrier barrier layer 154.

Please refer to FIG. 8 , which is a cross-sectional view of a semiconductor device 800 according to some embodiments of the present invention. The semiconductor device 800 is a high electron mobility transistor (HEMT) that can withstand a breakdown voltage of at least about 1800 volts. The semiconductor device 800 has a similar configuration to the semiconductor device 500, that is, the semiconductor device 800 also includes a non-native substrate 510, an intermediate bonding layer 520, a gallium nitride base layer 145, and a semiconductor heterostructure 850, but the intrinsic gallium nitride layer 856 in the semiconductor heterostructure 850 does not completely cover the aluminum gallium nitride carrier barrier layer 154. The semiconductor device 800 includes a p-type doped semiconductor layer 860 disposed on an intrinsic gallium nitride layer 856.

In addition, the semiconductor device 800 further includes a gate insulating layer 865, a gate 890g, a source 890s, and a drain 890d. The gate insulating layer 865 is disposed on the p-type doped semiconductor layer 860, and the gate 890g is disposed on the gate insulating layer 865. The source 890s and the drain 890d are both disposed on the aluminum gallium nitride carrier barrier layer 154, and are respectively disposed on both sides of the gate 890g, that is, the p-type doped semiconductor layer 860 and the gate 890g are located between the source 890s and the drain 890d.

The gallium nitride power element 740 in the semiconductor element 700 and the gallium nitride power element 840 in the semiconductor element 800 are both formed on a growth substrate such as a sapphire substrate, and then peeled off to be transferred to the non-native substrate 510, and bonded to the non-native substrate 510 using an intermediate bonding layer 520 to improve its thermal conductivity.

Based on the above, the present invention provides a semiconductor epitaxial wafer and a semiconductor device made using the semiconductor epitaxial wafer, which uses a two-dimensional material layer to peel off the gallium nitride power device formed on the growth substrate and transfer it to a non-native substrate with thermal conductivity to achieve a power semiconductor device with high voltage characteristics. Furthermore, the peeling method of the two-dimensional material layer can avoid device defects, and the growth substrate left after peeling can be reused, so the production cost can be reduced.

Although the present invention has been disclosed as above with several embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the patent application attached hereto.

140: Gallium nitride power element

145: Gallium nitride base layer

152: Gallium nitride carrier channel layer

154: Aluminum-gallium nitride carrier barrier layer

156: Intrinsic gallium nitride layer

160: p-type doped semiconductor layer

500:Semiconductor components

510: Non-native substrate

520: Middle bonding layer

Claims (8)

A semiconductor device comprises: a non-native substrate; an intermediate bonding layer disposed on the non-native substrate; a gallium nitride base layer disposed on the intermediate bonding layer, wherein the gallium nitride base layer has an average carbon doping concentration of 8×10 ¹⁶ cm ^-3 to 1×10 ¹⁸ cm ^-3 ; and a semiconductor heterostructure formed on the gallium nitride base layer and comprising: a gallium nitride carrier channel layer; and an aluminum gallium nitride carrier barrier layer formed on the gallium nitride carrier channel layer, wherein a two-dimensional electron gas (2DEG) is formed between the gallium nitride carrier channel layer and the aluminum gallium nitride carrier barrier layer. The semiconductor device as described in claim 1 further comprises: a p-type doped semiconductor layer formed on the semiconductor heterostructure, wherein the semiconductor heterostructure is located between the gallium nitride base layer and the p-type doped semiconductor layer. The semiconductor device as described in claim 2 further comprises: an intrinsic gallium nitride layer formed on the aluminum gallium nitride carrier barrier layer, wherein the intrinsic gallium nitride layer is located between the p-type doped semiconductor layer and the semiconductor heterostructure. A semiconductor device as described in claim 1, wherein the non-native substrate is selected from a group consisting of molybdenum, tungsten, molybdenum-copper alloy, tungsten-copper alloy, silicon and silicon carbide. The semiconductor device as described in claim 1 further comprises: a first planar layer formed between the intermediate bonding layer and the gallium nitride base layer, wherein the first planar layer comprises aluminum nitride or aluminum gallium nitride. A semiconductor device as described in claim 1, wherein the intermediate bonding layer comprises bonding two adjacent layers using metal bonding, oxide bonding, metal eutectic bonding or metal sintering. A semiconductor device as described in claim 1, wherein the thickness of the gallium nitride base layer is not greater than 5μm. A semiconductor device as described in claim 2 or 3, wherein the semiconductor device is a Schottky Barrier Diode (SBD) or a High Electron Mobility Transistor (HEMT).

Images