TWI732925B - Electronic power devices integrated with an engineered substrate - Google Patents

Abstract

A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.

Description

Power components integrated with engineering substrates

The present invention generally relates to power components formed on an engineered substrate structure. More specifically, the present invention relates to a method and system suitable for manufacturing power devices using an epitaxial growth process. As described herein, some embodiments of the present invention have been applied to methods and systems for manufacturing power components and semiconductor diodes on a substrate structure by epitaxial growth, wherein the substrate structure is characterized by the coefficient of thermal expansion (CTE) and The epitaxial layer forming the power element is substantially matched. The methods and techniques can be applied to a variety of semiconductor processing operations.

GaN-based power components are usually epitaxially grown on sapphire substrates. The growth of gallium nitride-based power components on a sapphire substrate is a heterogeneous epitaxial growth process, because the substrate and the epitaxial layer are composed of different materials. Due to the heteroepitaxial growth process, the epitaxially grown material may exhibit various adverse effects, including reduced uniformity and reduced measurements related to the electronic/optical properties of the epitaxial layer. Therefore, there is a need for improved methods and systems related to the epitaxial growth process and substrate structure in the technical field.

According to an embodiment of the present invention, a power element is provided. The power element includes: a substrate including a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesive layer, a bonding layer coupled to the barrier layer, and a substance coupled to the bonding layer上单晶层。 On the single crystal layer. The power element further includes: a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel area includes: a first end, a second end, and a central part disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power element further includes: a source contact provided at the first end of the channel region, a drain contact provided at the second end of the channel region, and a gate contact coupled to the channel region.

According to another embodiment of the present invention, a method of forming a power element is provided. The method includes the following steps: forming a substrate by providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core with a first adhesive shell; encapsulating the first adhesive shell with a barrier layer; forming a bonding layer on the barrier layer; and The single crystal layer is substantially connected to the bonding layer. The method further includes the steps of forming a buffer layer on the substantially single crystal layer and forming a channel region on the buffer layer by forming an epitaxial channel region barrier layer on the buffer layer. The channel area has a first end and a second end, and a central portion between the first end and the second end. The method further includes the steps of: forming a source contact on the first end of the channel region; forming a drain contact on the second end of the channel region; and forming a gate contact on the channel region.

According to a particular embodiment of the present invention, a semiconductor diode is provided. The semiconductor diode includes a substrate including a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesive layer, a bonding layer coupled to the barrier layer, and a bonding layer coupled to the bonding layer The essentially single crystal layer. The semiconductor diode further includes: a buffer layer coupled to the substantially single crystal layer, a semi-insulating layer coupled to the buffer layer, and a first N-type gallium nitride layer coupled to the semi-insulating layer. The first N-type gallium nitride layer has a first doping concentration. The semiconductor diode further includes: a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. In addition, the semiconductor diode includes: a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a first N-type gallium nitride layer coupled to it. Cathode contact of part of the gallium sulfide layer.

According to another particular embodiment of the present invention, a method of forming a semiconductor diode is provided. The method includes the following steps: forming a substrate by providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core with a first adhesive shell; encapsulating the first adhesive shell with a barrier layer; forming a bonding layer on the barrier layer; and The single crystal layer is substantially bonded to the bonding layer. The method further includes the following steps: forming a buffer layer on the substantially single crystal layer; forming a semi-insulating layer on the buffer layer; and forming a first epitaxial N-type gallium nitride layer on the semi-insulating layer. The first epitaxial N-type gallium nitride layer has a first doping concentration. The method further includes the following steps: forming a second epitaxial N-type gallium nitride layer on the first epitaxial N-type gallium nitride layer. The second epitaxial N-type gallium nitride layer has a second doping concentration less than the first doping concentration. In addition, the method includes the following steps: forming an epitaxial P-type gallium nitride layer on the second epitaxial N-type gallium nitride layer; removing part of the second epitaxial N-type gallium nitride layer and the epitaxial P-type gallium nitride layer Part of the gallium layer to expose the part of the first epitaxial N-type gallium nitride layer; forming an anode contact on the remaining part of the epitaxial P-type gallium nitride layer; and on the first epitaxial N-type gallium nitride layer A cathode contact is formed on the exposed part.

According to a specific embodiment of the present invention, a method of forming a semiconductor diode is provided. The method includes the following steps: forming a substrate by providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core with a first adhesive shell; encapsulating the first adhesive shell with a barrier layer; forming a bonding layer on the barrier layer; and The single crystal layer is substantially bonded to the bonding layer. The method further includes the following steps: forming a first epitaxial N-type gallium nitride layer on the substantially single crystal layer and forming a second epitaxial N-type gallium nitride layer on the first epitaxial N-type gallium nitride layer. The first epitaxial N-type gallium nitride layer has a first doping concentration and the second epitaxial N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The method further includes the following steps: forming an epitaxial P-type gallium nitride layer on the second epitaxial N-type gallium nitride layer; removing part of the substrate to expose the surface of the first epitaxial N-type gallium nitride layer; An anode contact is formed on the epitaxial P-type gallium nitride layer; and a cathode contact is formed on the exposed surface of the first epitaxial N-type gallium nitride layer.

According to another specific embodiment of the present invention, a power element is provided. The power element includes: a substrate including a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesive layer, a bonding layer coupled to the barrier layer, and a substance coupled to the bonding layer上单晶层。 On the single crystal layer. The power element further includes: a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel area includes: a first end, a second end, and a central part arranged between the first end and the second end. The channel region includes: a channel region barrier layer coupled to the buffer layer and a source contact disposed at the first end of the channel region. The element further includes: a drain contact provided at the second end of the channel region and a gate contact coupled to the channel region. As an example, the buffer layer may include at least one of III-V semiconductor materials, silicon germanium, aluminum gallium nitride, indium gallium nitride, or indium aluminum gallium nitride.

Compared with the conventional technology, the present invention can achieve numerous benefits. For example, an embodiment of the present invention provides a power device and a semiconductor diode formed on an engineering substrate, and the engineering substrate has a CTE that substantially matches the coefficient of thermal expansion (CTE) of the epitaxial layer of the device. The thermal expansion properties of the growth substrate are matched with the epitaxial layer, and the stress in the epitaxial layer and/or the engineering substrate is reduced. Stress causes several types of defects. For example, stress may increase the dislocation density in the epitaxial layer, which damages the electrical and optical properties of the epitaxial layer. The stress may also cause residual strain in the epitaxial layer or the substrate, which may cause additional processing considerations in subsequent steps, such as stress cracking, misalignment sliding, slippage, bending, and warping. The bending and warping of the substrate caused by thermal expansion may make material handling in automated equipment difficult and limit the ability to perform the necessary additional photolithography steps for component manufacturing, substrate cracking, and material migration. In addition, the performance life of the components in the stressed material is shortened. Stress relaxation caused by thermal mismatch and stress-induced crack propagation, dislocation sliding, and other lattice movement may cause early failure in a range of modes, from reduced device performance to cracking or peeling of the device and device layer.

These and other embodiments of the present invention and many advantages and features of the present invention are described in detail through the following embodiments and accompanying drawings.

The present invention generally relates to power components formed on an engineered substrate structure. More specifically, the present invention relates to a method and system suitable for manufacturing power devices using an epitaxial growth process. For example only, the invention has been applied to a method and system for manufacturing power devices on a substrate structure by epitaxial growth, wherein the substrate structure is characterized in that the coefficient of thermal expansion (CTE) substantially matches the epitaxial layer forming the power device. The methods and techniques can be applied to a variety of semiconductor processing operations.

Figure 1 is a simplified schematic cross-sectional view illustrating an engineering substrate structure according to an embodiment of the present invention. The engineering substrate 100 illustrated in Figure 1 is suitable for various electronic and optical applications. The engineering substrate 100 includes a core 110, and the core 110 may have a coefficient of thermal expansion (CTE) substantially matching the coefficient of thermal expansion (CTE) of the epitaxial material to be grown on the engineering substrate 100. The illustrated epitaxial material 130 is optional because it is not required as a requirement of the engineering substrate 100, but it will usually be grown on the engineering substrate 100.

For applications including the growth of gallium nitride (GaN)-based materials (including GaN-based epitaxial layers), the core 110 may be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN), which may include a bonding material , Such as yttrium oxide. Other materials that can be used in the core 110 include polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), and polycrystalline gallium trioxide (Ga ₂ O ₃ ) and so on.

The thickness of the core can be on the order of 100 to 1500 µm, for example 725 µm. The core 110 is encapsulated in an adhesive layer 112, and the adhesive layer may be called a shell or an encapsulating shell. In one embodiment, the adhesion layer 112 includes an ethylene orthosilicate (TEOS) oxide layer with a thickness of 1000 Å. In other embodiments, the thickness of the adhesive layer is different, such as 100 Å to 2000 Å. Although TEOS oxide is used in the adhesion layer in some embodiments, according to an embodiment of the present invention, other materials that provide adhesion between the subsequently deposited layer and the underlying layer or material (such as ceramics, especially polycrystalline ceramics) can be used. Material. For example, SiO ₂ or other silicon oxide _{(Si x O y} ) adheres well to the ceramic material and provides a suitable surface for subsequent, such as the deposition of conductive materials. In some embodiments, the adhesive layer 112 completely surrounds the core 110 to form a completely encapsulated core. The adhesion layer 112 can be formed using an LPCVD process. The adhesive layer provides a surface, and a subsequent layer is adhered on the surface to form an element of the engineering substrate 100 structure.

In addition to using an LPCVD process, a furnace-based process, etc., to form the encapsulated first adhesive layer, other semiconductor processes may be used according to embodiments of the present invention, including CVD processes or similar deposition processes. As an example, a deposition process that coats part of the core can be used, the core can be turned over, and the deposition process can be repeated to coat another part of the core. Therefore, although LPCVD technology is used in some embodiments to provide a completely encapsulated structure, other film formation techniques may be used depending on the particular application.

The conductive layer 114 is formed around the adhesive layer 112. In one embodiment, the conductive layer 114 is a polysilicon (ie, polycrystalline silicon) shell formed around the first adhesive layer 112 because polysilicon may exhibit poor adhesion to ceramic materials. In the embodiment where the conductive layer 114 is polysilicon, the thickness of the polysilicon layer may be 500-5000 Å, for example, 2500 Å. In some embodiments, a polysilicon layer may be formed as a shell to completely surround the first adhesive layer 112 (eg, TEOS oxide layer), thereby forming a completely encapsulated first adhesive layer, and may be formed using an LPCVD process. In other embodiments discussed below, the conductive material may be formed on a portion of the adhesive layer, such as the lower half of the substrate structure. In some embodiments, the conductive material may be formed as a thorough encapsulation layer and then removed on one side of the substrate structure.

In one embodiment, the conductive layer 114 may be a doped polysilicon layer to provide a highly conductive material, such as boron doped to provide a P-type polysilicon layer. In some embodiments, the degree of doping with boron is 1 x 10 ¹⁹ cm ^-3 to 1 x 10 ²⁰ cm ^-3 to provide high conductivity. Other dopants with different dopant concentrations (for example, ^{phosphorus, arsenic, bismuth, etc., with a dopant concentration ranging from 1 x 10 16} cm ^-3 to 5 x 10 ¹⁸ cm ^-3 ) can be used to provide the conductive layer 114 N-type or P-type semiconductor materials. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

During the electrostatic clamping of the engineering substrate 100 to a semiconductor processing tool, such as a tool with an electrostatic discharge (ESD) fixture, the presence of the conductive layer 114 is useful. The conductive layer 114 enables rapid dechucking after processing in a semiconductor processing tool. Therefore, the embodiments of the present invention provide a substrate structure that can be processed in a manner that can be used with conventional silicon wafers. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

The second adhesive layer 116 (eg, a TEOS oxide layer with a thickness of 1000 Å) is formed around the conductive layer 114. In some embodiments, the second adhesive layer 116 completely surrounds the conductive layer 114 to form a completely encapsulated structure. An LPCVD process, a CVD process, or any other suitable deposition process including spin-on dielectric deposition can be used to form the second adhesion layer 116.

The barrier layer 118, such as a silicon nitride layer, is formed around the second adhesion layer 116. In one embodiment, the barrier layer is a silicon nitride layer 118 with a thickness of 4000 Å to 5000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 116 to form a completely encapsulated structure, and can be formed using an LPCVD process. In addition to the silicon nitride layer, amorphous materials including SiCN, SiON, AlN, SiC, etc. can be used as the barrier layer. In some implementations, the barrier layer is composed of several sub-layers, which are built up to form the barrier layer. Therefore, the term "barrier layer" does not mean a single layer or a single material, but includes one or more materials laminated in a composite manner. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

In some embodiments, a barrier layer, such as a silicon nitride layer, prevents the diffusion and/or outgassing of components present in the core 110 into the environment of the semiconductor processing chamber where the engineered substrate 100 may exist, such as at high temperature ( For example, 1000°C) during the epitaxial growth process. The components present in the core 110 may include, for example, yttrium oxide (ie, yttria), oxygen, metal impurities, other trace components, and the like. The components diffused from the core 110 may cause unintentional doping in the engineered layer 120/122. The components outgassed from the core 110 may travel through the chamber and be adsorbed on other parts of the wafer to cause impurities in the engineering layer 120/122 and the epitaxial material 130. Using the encapsulation layer described herein, ceramic materials including polycrystalline AlN designed for use in non-clean room environments can be used in semiconductor manufacturing processes and clean room environments.

Figure 2A is a secondary ion mass spectrometer (SIMS) data diagram illustrating the species concentration as a function of depth for engineering structures according to an embodiment of the present invention. The X axis represents the depth 202 from the surface of the engineered layer 120/122 to the core 110. Line 208 represents the interface between the engineering layer 120/122 and the core 110. The first y-axis represents the species concentration 204 of atoms per cubic centimeter. The second y-axis represents the signal intensity 206 of the ions counted per second. The engineering structure in Figure 2A does not include the barrier layer 118. Referring to Figure 2A, several species (eg, yttrium, calcium, and aluminum) present in the ceramic core 110 are reduced to negligible concentrations in the engineered layer 120/122. The concentration of calcium 210, yttrium 220, and aluminum 230 decreased by three, four, and six orders of magnitude, respectively.

Figure 2B is a SIMS data diagram illustrating the species concentration as a function of depth for an engineered structure without a barrier layer after annealing according to an embodiment of the present invention. As discussed above, during semiconductor processing operations, such as during the epitaxial growth of a GaN-based layer, the engineered substrate structure provided by the embodiments of the present invention can be exposed to high temperature (~1100° C.) for several hours. For the data illustrated in Figure 2B, the engineered substrate structure was annealed at 1100°C for four hours. As shown in Figure 2B, calcium 210, yttrium 220, and aluminum 230 originally present in low concentrations in the engineering layer 120/122 have diffused into the engineering layer 120/122 to reach a concentration similar to other components.

Therefore, the embodiment of the present invention integrates a barrier layer (e.g., silicon nitride layer) to prevent the background component from diffusing out of the polycrystalline ceramic material (e.g., AlN) into the engineering layer 120/122 and the epitaxial material 130, Such as selective GaN layer. The silicon nitride layer encapsulating the underlying layer and material provides the desired barrier layer 118 functionality.

Figure 2C is a SIMS data diagram illustrating the species concentration as a function of depth for an engineered structure with a barrier layer 118 (represented by a dashed line 240) after annealing according to an embodiment of the present invention. Integrating the diffusion barrier layer 118 (eg, silicon nitride layer) into the engineering substrate structure prevents calcium, yttrium, and aluminum from diffusing into the engineering layer during the annealing process, and diffusion occurs when the diffusion barrier layer is not present. As illustrated in Figure 2C, after annealing, the calcium 210, yttrium 220, and aluminum 230 present in the ceramic core maintain a low concentration in the engineered layer. Therefore, the use of the barrier layer 118 (eg, a silicon nitride layer) prevents the components from diffusing through the diffusion barrier and thus prevents the components from being released into the environment surrounding the engineering substrate. Similarly, any other impurities contained in the bulk ceramic material will be limited by the barrier layer.

Typically, the ceramic material used to form the core 110 is sintered at a temperature in the range of 1800°C. It is expected that this process will drive out a large amount of impurities in the ceramic material. The impurities may include yttrium, calcium and other components and compounds obtained by using yttrium oxide as a sintering agent. Next, during the epitaxial growth process performed at a temperature much lower in the range of 800° C. to 1100° C., it is expected that subsequent diffusion of these impurities will be very small. However, contrary to conventional expectations, the inventor of the present case determined that even during the epitaxial growth process at a temperature much lower than the sintering temperature of the ceramic material, there is still a large amount of component diffusion through the layers of the engineered substrate. Therefore, the embodiment of the present invention integrates the barrier layer 118 into the engineering substrate 100 to prevent such undesired diffusion.

Referring again to FIG. 1, the bonding layer 120 (eg, a silicon oxide layer) is deposited on a portion of the barrier layer 118, such as the top surface of the barrier layer, and is subsequently used during bonding of the single crystal layer 122. In some embodiments, the thickness of the bonding layer 120 may be about 1.5 µm. The single crystal layer 122 may include, for example, Si, SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga ₂ O ₃ , AlGaN, InGaN, InN, and/or ZnO. In some embodiments, the thickness of the single crystal layer may be 0-0.5 µm. The single crystal layer 122 is suitable for use as a growth layer during the epitaxial growth process for forming the epitaxial material 130. The crystalline layer of the epitaxial material 130 is an extension of the underlying semiconductor lattice related to the single crystalline layer 122. The unique CTE matching property of the engineering substrate 100 can grow thicker epitaxial material 130 than in the prior art. In some embodiments, the epitaxial material 130 includes a gallium nitride layer with a thickness of 2 µm to 10 µm, which can be used as one of a plurality of layers used in optoelectronic devices, power devices, and the like. In one embodiment, the bonding layer 120 includes a single crystal silicon layer attached to the silicon oxide barrier layer 118 using a layer transfer process.

Figure 3 is a simplified schematic cross-sectional view illustrating an engineering substrate structure according to an embodiment of the present invention. The engineering substrate 300 illustrated in FIG. 3 is suitable for various electronic and optical applications. The engineering substrate 300 includes a core 110, which may have a CTE that substantially matches the coefficient of thermal expansion (CTE) of the epitaxial material to be grown on the engineering substrate 300. The illustrated epitaxial material 130 is optional, because it is not required as an essential part of the engineering substrate structure, but it will usually grow on the engineering substrate structure.

For applications including the growth of gallium nitride (GaN)-based materials (including GaN-based epitaxial layers), the core 110 may be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core can be in the order of 100 µm to 1500 µm, for example 725 µm. The core 110 is encapsulated in an adhesive layer 112, which may be referred to as a shell or an encapsulating shell. In this implementation, the adhesive layer 112 completely encapsulates the core, but this is not necessary for the present invention, as discussed in the additional details related to FIG. 4.

In one embodiment, the adhesion layer 112 includes an ethylene orthosilicate (TEOS) oxide layer with a thickness of 1000 Å. In other embodiments, the thickness of the adhesive layer is different, for example, from 100 Å to 2000 Å. Although TEOS oxide is used in the adhesion layer in some embodiments, according to one embodiment of the present invention, other materials that provide adhesion between the subsequently deposited layer and the underlying layer or material may be used. For example, SiO ₂ , SiON, etc. adhere well to ceramic materials and provide suitable surfaces for subsequent deposition, such as conductive materials. In some embodiments, the adhesive layer 112 completely surrounds the core 110 to form a completely encapsulated core and can be formed using an LPCVD process. The adhesive layer 112 provides a surface, and subsequent layers are adhered to the surface to form an essential part of the engineered substrate structure.

In addition to using an LPCVD process, a furnace-based process, etc., to form the encapsulation adhesive layer 112, other semiconductor processes can be used according to embodiments of the present invention. As an example, a deposition process such as CVD, PECVD, etc. may be used to coat a part of the core 110, the core 110 may be turned over, and the deposition process may be repeated to coat another part of the core 110.

The conductive layer 314 is formed on at least part of the adhesive layer 112. In one embodiment, the conductive layer 314 includes polysilicon (ie, polycrystalline silicon), which is formed by a deposition process on the lower part (ie, lower half of the structure formed by the core 110 and the adhesion layer 112). Or dorsal) on. In the embodiment where the conductive layer 314 is polysilicon, the thickness of the polysilicon layer may be in the order of thousands of angstroms, such as 3000 angstroms. In some embodiments, an LPCVD process can be used to form the polysilicon layer.

In one embodiment, the conductive layer 314 may be a doped polysilicon layer to provide a highly conductive material. For example, the conductive layer 314 may be doped with boron to provide a P-type polysilicon layer. In some embodiments, the degree of boron doping ranges from about 1 x 10 ¹⁹ cm ^-3 to 1 x 10 ²⁰ cm ^-3 to provide high conductivity. The presence of the conductive layer 314 is used for electrostatic clamping of the engineering substrate to a semiconductor processing tool, such as a tool with an electrostatic discharge (ESD) fixture. The conductive layer 314 enables rapid release after processing. Therefore, embodiments of the present invention provide substrate structures that can be processed in conjunction with the use of conventional silicon wafers. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

The second adhesive layer 316 (eg, the second TEOS oxide layer) is formed around the conductive layer 314 (eg, a polysilicon layer). The thickness of the second adhesive layer 316 is on the order of 1000 Å. In some embodiments, the second adhesive layer 316 completely surrounds the conductive layer 114 to form a completely encapsulated structure and can be formed using an LPCVD process.

The barrier layer 118 (eg, a silicon nitride layer) is formed around the second adhesion layer 316. In some embodiments, the thickness of the barrier layer 118 is on the order of 4000 Å to 5000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 112 to form a completely encapsulated structure and can be formed using an LPCVD process.

In some embodiments, the barrier layer 118 including silicon nitride is used to prevent the components present in the core 110 from diffusing and/or outgassing into the environment of the semiconductor processing chamber where the engineered substrate may exist, such as at high temperatures (e.g., 1000 ℃) during the epitaxial growth process. The components present in the core include, for example, yttrium oxide (ie, yttria), oxygen, metal impurities, other trace components, and the like. Using the encapsulation layer as described herein, ceramic materials, including polycrystalline AlN designed for use in non-clean room environments, can be used in semiconductor manufacturing processes and clean room environments.

In some embodiments, the engineered substrate 100 can comply with the International Semiconductor Equipment and Materials (SEMI) standard specifications. Because the engineered substrate 100 can comply with SEMI specifications, the engineered substrate 100 can be used with existing semiconductor manufacturing tools. For example, the wafer diameter of the engineered substrate can be 4-inch, 6-inch, or 8-inch. In some embodiments, the thickness of the 8-inch engineering substrate wafer may be 725-750 µm. In contrast, the silicon substrates currently used to manufacture gallium nitride epitaxial layers do not comply with SEMI specifications because the thickness of the silicon substrates is 1050-1500 µm. Due to this non-compliance, silicon substrates cannot be used in devices that comply with SEMI specifications.

FIG. 4 is a simplified schematic cross-sectional view illustrating an engineering substrate structure 400 according to another embodiment of the present invention. In the embodiment illustrated in FIG. 4, the adhesive layer 412 is formed on at least part of the core 110, but the core 110 is not encapsulated. In this implementation, the adhesion layer 412 is formed on the lower surface of the core (the back side of the core) to enhance the adhesion of the subsequently formed conductive layer 414, as described in more detail below. Although only the adhesion layer 412 is illustrated on the lower surface of the core in Figure 4, it will be understood that depositing the adhesion layer material on other parts of the core will not adversely affect the performance of the engineered substrate structure and that such materials may exist in various forms. In the embodiment. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

The conductive layer 414, instead of being formed as a shell as illustrated in FIG. 3, does not encapsulate the adhesive layer 412 and the core 110, but is substantially aligned with the adhesive layer 412. Although the illustrated conductive layer 414 extends upward along the bottom or back side of the side portion of the adhesive layer 412, this is not required by the present invention. Therefore, embodiments may use deposition on one side of the substrate structure, masking one side of the substrate structure, and so on. The conductive layer 414 may be formed on one side of the adhesive layer 412, such as the bottom/back side. The conductive layer 414 provides electrical conduction on one side of the engineered substrate structure 400, which can be beneficial for RF and high power applications. The conductive layer 414 may include doped polysilicon as discussed in relation to the conductive layer 114 in FIG. 1. In addition to the semiconductor-based conductive layer, in other embodiments, the conductive layer 414 is a metal layer, such as 500 Å titanium or the like.

The part of the core 110, the part of the adhesive layer 412, and the conductive layer 414 are covered with a second adhesive layer 416 to improve the adhesion of the barrier layer 418 to the underlying material. The barrier layer 418 forms an encapsulation structure to prevent diffusion from the underlying layer as discussed above with respect to FIGS. 2A, 2B, and 2C.

Referring again to Figure 4, depending on the implementation situation, one or more layers can be removed. For example, layers 412 and 414 can be removed, leaving only a single adhesive shell 416 and barrier layer 418. In other embodiments, only the layer 414 may be removed, leaving a single adhesive layer 412 under the barrier layer 416. In this embodiment, the adhesion layer 412 can also balance the stress caused by the bonding layer 120 deposited on top of the barrier layer 418 and wafer bending. A configuration with a substrate structure with an insulating layer on the top side of the core 110 (eg, having only an insulating layer between the core 110 and the bonding layer 120) will provide benefits for power/RF applications, where highly insulating substrates are desired.

In another embodiment, the barrier layer 418 may directly encapsulate the core 110, followed by the conductive layer 414 and the subsequent adhesive layer 416. In this embodiment, the bonding layer 120 may be directly deposited on the adhesion layer 416 from the top side. In yet another embodiment, the adhesion layer 416 may be deposited on the core 110, followed by the barrier layer 418, then the conductive layer 414, and another adhesion layer 412.

Although some embodiments have been discussed in terms of a layer, it should be understood that a layer may include several sublayers, which are combined to form the layer of interest. Therefore, the term layer does not mean a single layer composed of a single material, but includes one or more materials laminated in a composite manner to form the desired structure. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

FIG. 5 is a simplified flowchart illustrating a method of manufacturing an engineering substrate according to an embodiment of the present invention. The method can be used to manufacture a substrate, the CTE of the substrate is matched and grown on one or more epitaxial layers on the substrate. The method 500 includes the following steps: forming a support structure by the following steps: providing a polycrystalline ceramic core (510); encapsulating the polycrystalline ceramic core in a first adhesive layer to form a shell (512) (e.g., TEOS ) Oxide shell); and encapsulating the first adhesive layer in the conductive shell (514) (eg, polysilicon shell). The first adhesive layer can be formed as a single layer of TEOS oxide. The conductive shell can be formed as a single layer of polysilicon.

The method also includes the following steps: encapsulating the conductive shell in the second adhesive layer (eg, the second TEOS oxide shell) (516) and encapsulating the second adhesive layer in the barrier layer shell (518). The second adhesive layer can be formed as a single layer of TEOS oxide. The barrier shell can be formed as a single layer of silicon nitride.

Once the support structure is formed through the process steps 510-518, the method further includes the following steps: bonding a bonding layer (eg, a silicon oxide layer) to the support structure (520) and bonding a substantially single crystal layer, such as a single crystal silicon layer, to the silicon oxide Layer (522). According to embodiments of the present invention, other substantially single crystal layers may be used, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga ₂ O ₃ , ZnO, and so on. The bonding of the bonding layer may include a bonding material deposition and subsequent planarization process as described herein. In an embodiment described below, a layer transfer process is used to bond a substantially single crystal layer (eg, a single crystal silicon layer) to the bonding layer, where the layer is a single crystal silicon layer transferred from a silicon wafer.

Referring to FIG. 1, the bonding layer 120 can be formed by depositing a thick (for example, 4 µm thick) oxide layer and then performing a chemical mechanical polishing (CMP) process to thin the oxide to a thickness of about 1.5 µm. The thick initial oxide is used to fill the voids and the surface features existing on the support structure. The surface features may exist after the polycrystalline core is manufactured and continue to exist when the encapsulation layer is formed as described in Figure 1. The CMP process provides a substantially flat surface without voids, particles, or other features, which can then be used during a wafer transfer process to bond the single crystal layer 122 (eg, a single crystal silicon layer) to the bonding layer 120. It will be understood that the bonding layer does not necessarily have the characteristics of an atomically flat surface, but should provide a substantially flat surface that will support a single crystal layer with the desired reliability (eg, single crystal Silicon layer) bonding.

The layer transfer process is used to bond the single crystal layer 122 (eg, a single crystal silicon layer) to the bonding layer 120. In some embodiments, a silicon wafer including a substantially single crystal layer 122 (eg, a single crystal silicon layer) is implanted to form a crack. In this embodiment, after wafer bonding, the silicon substrate can be removed along the part of the single crystal silicon layer below the crack surface, resulting in a delamination of the single crystal silicon layer. The thickness of the single crystal layer 122 can be changed to meet the specifications of various applications. In addition, the crystal orientation of the single crystal layer 122 can be changed to meet the specifications of the application. In addition, the degree of doping and profile in the single crystal layer can be varied to meet the specifications of a particular application. In some embodiments, the depth of implantation can be adjusted to be greater than the desired final thickness of the single crystal layer 122. This additional thickness allows for the removal of the transferred thin portion of the substantially damaged single crystal layer, leaving the undamaged portion of the desired final thickness. In some embodiments, the surface roughness can be modified for high-quality epitaxial growth. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

In some embodiments, the single crystal layer 122 may be thick enough to provide a high-quality lattice template for the subsequent growth of one or more epitaxial layers, but the single crystal layer 122 is thin enough to be highly compliant. When the single crystal layer 122 is relatively thin so that its physical properties are less restricted and can imitate the surrounding materials without the tendency to produce crystalline defects, the single crystal layer 122 can be said to be "compliant." The compliance of the single crystal layer 122 may be negatively related to the thickness of the single crystal layer 122. Higher compliance can result in a lower defect density in the epitaxial layer grown on the template and enable the growth of a thicker epitaxial layer. In some embodiments, the thickness of the single crystal layer 122 can be increased by epitaxial growth of silicon on the delaminated silicon layer.

In some embodiments, the final thickness of the single crystal layer 122 can be adjusted by thermal oxidation of the top of the delaminated silicon layer followed by stripping of the oxide layer with hydrofluoric (HF) acid. For example, a delaminated silicon layer with an initial thickness of 0.5 µm can be thermally oxidized to produce a silicon dioxide layer with a thickness of about 420 nm. After removing the generated thermal oxide, the remaining silicon thickness in the transferred layer may be about 53 nm. During thermal oxidation, the implanted hydrogen can move towards the surface. Therefore, the subsequent stripping of the oxide layer can remove some damage. Also, thermal oxidation is usually performed at a temperature of 1000°C or higher. Elevated temperature can also repair lattice damage.

HF acid etching can be used to strip the silicon oxide layer formed on top of the single crystal layer during thermal oxidation. The etching selectivity between _{silicon oxide and silicon (SiO 2} :Si) via HF acid can be adjusted by adjusting the temperature and concentration of the HF solution and the chemical dose and density of silicon oxide. Etching selectivity refers to the etch rate of one material relative to another. For SiO2:Si, the selectivity of the HF solution can range from about 10:1 to about 100:1. The high etch selectivity can reduce the surface roughness by a similar factor from the initial surface roughness. However, the surface roughness of the obtained single crystal layer 122 may still be greater than desired. For example, when scanning with a 2 µm × 2 µm atomic force microscope (AFM) before performing additional processing, the root mean square (RMS) surface roughness of the bulk Si (111) surface can be less than 0.1 nm. In some embodiments, the desired surface roughness for epitaxial growth of gallium nitride material on Si (111) can be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm, at 30 µm × 30 On the scanning area of µm AFM.

If the surface roughness of the single crystal layer 122 after thermal oxidation and oxide layer stripping exceeds the desired surface roughness, another surface smoothing treatment may be performed. There are several ways to smooth the surface of silicon. Such methods may include hydrogen annealing, laser trimming, and contact polishing (e.g., CMP). These methods may involve preferential attacks on high aspect ratio surface peaks. Therefore, high aspect ratio features on the surface can be removed faster with lower aspect ratio features, resulting in a smoother surface.

It should be understood that the specific steps illustrated in Figure 5 provide a specific method for manufacturing an engineering substrate according to an embodiment of the present invention. According to alternative embodiments, other sequence of steps can also be performed. For example, alternative embodiments of the present invention may perform the steps in a different order than the foregoing outline. In addition, the individual steps illustrated in FIG. 5 may include multiple sub-steps, and the sub-steps may be executed in various sequences suitable for the individual steps. In addition, depending on the particular application, additional steps can be added or removed. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

FIG. 6 is a simplified flowchart illustrating a method of manufacturing an engineering substrate according to another embodiment of the present invention. The method includes the following steps: forming a support structure by providing a polycrystalline ceramic core (610); forming an adhesive layer (612) coupled to at least part of the polycrystalline ceramic core. The first adhesion layer may include a TEOS oxide layer. The first adhesive layer may be formed as a single layer of TEOS oxide. The method also includes the step of forming a conductive layer coupled to the first adhesive layer (614). The conductive layer may be a polysilicon layer. The conductive layer can be formed as a single layer of polysilicon.

The method further includes the following steps: forming a second adhesive layer (616) coupled to at least part of the first adhesive layer and forming a barrier shell (618). The second adhesive layer may be formed as a single layer of TEOS oxide. The barrier shell can be formed as a single layer of silicon nitride, or the barrier shell can be formed from a series of sub-layers.

Once the support structure is formed by the process steps 610-618, the method further includes the following steps: bonding the bonding layer (eg, silicon oxide layer) to the support structure (620) and bonding the single crystal silicon layer or substantially single crystal layer to the silicon oxide Layer (622). The bonding of the bonding layer may include the deposition of bonding material as described herein followed by a planarization process. In an embodiment described below, a layer transfer process is used to bond a single crystal layer (eg, a single crystal silicon layer) to the bonding layer, wherein the single crystal silicon layer is transferred from the silicon wafer.

It should be understood that the specific steps illustrated in Figure 6 provide a specific method for manufacturing an engineering substrate according to another embodiment of the present invention. According to alternative embodiments, other sequence of steps can also be performed. For example, alternative embodiments of the present invention may perform the steps in a different order than the foregoing outline. In addition, the individual steps illustrated in FIG. 6 may include multiple sub-steps, and the sub-steps may be executed in various sequences suitable for the individual steps. In addition, depending on the particular application, additional steps can be added or removed. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

Figure 7 is a simplified schematic cross-sectional view illustrating an epitaxial/engineered substrate structure 700 for RF and power applications according to an embodiment of the present invention. In some LED applications, the engineered substrate structure provides a growth substrate, which enables the growth of a high-quality GaN layer, and the engineered substrate structure is subsequently removed. However, for RF and power component applications, the engineered substrate structure forms part of the final component, and therefore the electrical, thermal, and other properties of the engineered substrate structure or the components of the engineered substrate structure are important for special applications.

Referring to FIG. 1, the single crystal layer 122 may be a delamination single crystal silicon layer separated from the silicon donor wafer using implantation and exfoliation techniques. Typical implants are hydrogen and boron. For power and RF component applications, the electrical properties of the layers and materials in the engineered substrate structure are important. For example, some device architectures use a highly insulating silicon layer with a resistance greater than 103 Ohm-cm to reduce or eliminate leakage through the substrate and the interface layer. Other applications include the design of a conductive silicon layer with a predetermined thickness (eg, 1 µm) to connect the source of the device to other elements. Therefore, in these applications, it is desirable to control the size and properties of the single crystal silicon layer. In designs that use implantation and delamination techniques during layer transfer, residual implanted atoms such as hydrogen or boron are present in the silicon layer, thus changing the electrical properties. In addition, it is difficult to control the thickness, conductivity, and other properties of the thin silicon layer, such as adjusting the implant dose (which may affect the conductivity) and adjusting the implant depth (which may affect the layer thickness).

According to the embodiment of the present invention, the silicon epitaxy on the engineered substrate structure is used to obtain the desired properties of the single crystal silicon layer suitable for the special device design.

Referring to FIG. 7, the epitaxial/engineered substrate structure 700 includes an engineered substrate structure 710 and an epitaxial single crystal layer 720 formed thereon. In some embodiments, the epitaxial single crystal layer 720 may be a single crystal silicon layer. The engineering substrate structure 710 may be similar to the engineering substrate structure illustrated in FIGS. 1, 3 and 4. Typically, after the layer transfer, the single crystal layer 122 (for example, a single crystal silicon layer) is on the order of 0.5 µm. In some manufacturing processes, a surface conditioning process may be used to reduce the thickness of the single crystal layer 122 to about 0.3 µm. In order to increase the thickness of the single crystal layer 122 to about 1 µm for manufacturing reliable ohmic contacts, for example, an epitaxial process is used to grow the epitaxial single crystal layer 720 on the single crystal layer 122 formed by the layer transfer process. Variations in the epitaxial growth process can be used to grow the epitaxial single crystal layer 720, including CVD, LPCVD, ALD, MBE, and so on. The epitaxial single crystal layer 720 may include, for example, Si, SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga ₂ O ₃ , and/or ZnO. The thickness of the epitaxial single crystal layer 720 may range from about 0.1 µm to about 20 µm, for example, between 0.1 µm and 10 µm.

FIG. 8A is a simplified schematic cross-sectional view illustrating a III-V epitaxial layer on an engineering substrate structure according to an embodiment of the present invention. The structure illustrated in FIG. 8A can be regarded as the double epitaxial structure 800 described below. As illustrated in FIG. 8A, the engineering substrate structure 810 including the epitaxial single crystal layer 720 has the III-V epitaxial layer 820 formed thereon. In one embodiment, the III-V epitaxial layer includes gallium nitride (GaN). In order to provide conductivity between the parts of the III-V epitaxial layer (which may include multiple sublayers), in this example, a set of through holes 824 are formed to penetrate from the top surface of the III-V epitaxial layer 820 to the epitaxial layer. Crystalline single crystal layer 720. FIG. 8A shows that the through hole 824 extends through the epitaxial layer 820 to the epitaxial single crystal layer 720. As an example, by providing ohmic contacts through the through holes 824, the through holes can be used to connect the electrodes of the diode or transistor to the underlying layer, thereby alleviating the charge accumulated in the device. In some embodiments, one or more through holes 824 may be insulated on the sidewalls thereof so that they are not electrically connected to the III-V epitaxial layer 820. The electrical contacts can promote the removal of parasitic charges, thereby enabling faster switching of power components.

In some embodiments, the through hole 826 may extend to the single crystal layer 122. In order to solve the difficulty of manufacturing the through hole 826 to contact the single crystal layer 122, an additional conductive epitaxial layer 822 can be grown on the single crystal layer 122 and the single crystal layer 720 to increase the size of the target conductive layer for the through hole 826. That is, the thickness of the layer in which the through hole ends. Due to the unique CTE and diffusion properties of the engineered substrate structure 810, the epitaxial single crystal layer 720 and the III-V epitaxial layer 820 can be formed thicker than conventional substrates. Therefore, the existing substrate technology cannot support the growth of a defect-free epitaxial layer to include the conductive epitaxial layer 822 in the device. In some embodiments, the conductive epitaxial layer 822 may be AlN, AlGaN, GaN or a fully doped semiconductor material. In a particular embodiment, the thickness of the conductive epitaxial layer 822 may be 0.1-10 µm. In other embodiments, the thickness of the conductive epitaxial layer 822 may vary depending on the requirements of the semiconductor device. In some embodiments, the engineered substrate structure and the single crystal layer 122 can be removed, exposing the epitaxial single crystal layer 720 and/or the conductive epitaxial layer 822. After the substrate is removed, contacts can be formed on the exposed epitaxial layer. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

In some embodiments, the III-V epitaxial layer can be grown on the single crystal layer 122. In order to terminate the through hole in the single crystal layer 122, an ohmic contact using the through hole can be made in the 0.3 µm single crystal layer of the entire wafer. Using the embodiments of the present invention, a single crystal layer several micrometers thick can be provided. It is difficult to use implantation and delamination processes to reach a thickness of several microns, because large implantation depths require high implantation energy. The thick epitaxial single crystal layer enables applications such as the illustrated through hole to enable a wide range of device designs.

In addition to increasing the thickness of the "layer" by epitaxially growing the epitaxial single crystal layer 720 on the single crystal layer 122, other adjustments can be made to the original properties of the single crystal layer 122, including conductivity, crystallinity, etc. Retouching. For example, if the desired silicon layer before the epitaxial growth of additional III-V family layers or other materials is of the order of 10 µm, this thick layer can be grown according to the embodiment of the present invention.

The implantation process may affect the properties of the single crystal layer 122. For example, residual boron/hydrogen atoms may cause defects that affect the electrical properties of the silicon crystal layer. In some embodiments of the present invention, part of the single crystal layer 122 may be removed before the epitaxial growth of the epitaxial single crystal layer 720. For example, by removing most or all of the remaining boron/hydrogen atoms, the single crystal silicon layer can be thinned to form a layer with a thickness of 0.1 µm or less. Subsequent growth of the single crystal silicon layer is then used to provide a single crystal material whose electrical and/or other properties are substantially independent of the corresponding characteristics of the layer formed using the layer transfer process.

In addition to increasing the thickness of the single crystal silicon material coupled to the engineering substrate structure, the electrical properties of the epitaxial single crystal layer 720 include conductivity, which may be different from the electrical properties of the single crystal layer 122. The doping of the epitaxial single crystal layer 720 during the growth period can produce P-type silicon by doping with boron and produce N-type silicon by doping with phosphorus. Undoped silicon can be grown to provide high-resistance silicon for use in devices with insulating regions. In particular, the insulating layer can be used in RF components.

The lattice constant of the epitaxial single crystal layer 720 can be adjusted during growth to be different from the lattice constant of the single crystal layer 122 to produce a strained epitaxial material. In addition to silicon, other components that can be epitaxially grown to provide a layer including a strained layer include silicon germanium and the like. In addition, the crystal orientation of the crystal plane, such as the growth of (111) silicon on (100) silicon, can be used to introduce strain. For example, a buffer layer can be grown on the single crystal layer 122, on the epitaxial single crystal layer 720, or between layers to promote subsequent epitaxial growth. The buffer layers may include III-V semiconductor materials, such as aluminum gallium nitride, indium gallium nitride, and indium aluminum gallium nitride, silicon germanium strained layers, and so on. The strain of the III-V semiconductor material layer can be adjusted for the desired material properties. In addition, the molar fraction, dopants, polarity, etc. of the buffer layer and other epitaxial layers can be graded. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

In some embodiments, during the subsequent growth of the epitaxial layer including the III-V epitaxial layer, the strain existing in the single crystal layer 122 or the epitaxial single crystal layer 720 may be relaxed.

FIG. 8B is a simplified schematic plan view illustrating four double epitaxial structures according to an embodiment of the present invention. The dual epitaxial structures illustrated in FIG. 8B each include a set of through holes 824. The first double epitaxial structure 830 shows a tight through hole configuration. The second double epitaxial structure 840 shows a dispersed through hole configuration. The dispersed through-hole configuration using through-holes 824 in the active area of the device is more likely to experience charge accumulation. The third double epitaxial structure 850 shows a patterned through hole configuration. The patterned through hole configuration can separate the through holes 824 on the dual epitaxial structure 850 by an equal distance. The fourth double epitaxial structure 860 illustrates the lateral through hole 828. The lateral through hole 828 may be manufactured to run substantially parallel to the epitaxial layer of the double epitaxial structure 860 and contact the single crystal layer 122 at, for example, the edge 862. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

The engineering substrate as described above can withstand the epitaxial growth of a gallium nitride device layer on which it is substantially lattice-matched with the engineering substrate and is characterized by a coefficient of thermal expansion (CTE) substantially matching the thermal expansion coefficient of the engineering substrate. Therefore, the engineered substrate can provide excellent thermal stability and shape control. Engineered substrates can also enable wafer diameter scaling with reusability capabilities. A relatively thick (eg, greater than 20 µm) high-quality epitaxial gallium nitride layer can be formed on an engineering substrate that has no cracks and is characterized by low defect density and low post-epitaxial bending and stress. It can be implemented on a single platform, such as multiple applications such as power components, radio frequency (RF) components, monolithic microwave integrated circuits (MMIC), displays, light emitting diodes (LED), and so on. This engineering substrate is also suitable for various component architectures, such as lateral components, vertical components, chip scale package (CSP) components, and so on.

Gallium nitride (GaN) and similar wide band gap semiconductor materials provide better physical properties than those formed from silicon, allowing power semiconductor components based on these materials to withstand high voltages and temperatures. These properties also allow for higher frequency response, higher current density and faster switching. However, before the wide band gap device can be accepted by the market, its reliability must be proven and the demand for higher reliability is growing. The continued demand for greater power density at the component and package level has the consequence of higher temperatures and temperature gradients across the package. The use of engineered substrates to form a CTE-matched epitaxial device layer can alleviate the common thermal-related failure mechanism of many wide band gap devices, as explained below.

Compound semiconductor devices, such as gallium nitride (GaN)-based high electron mobility transistors (HEMT), can withstand high electric fields and high currents (eg, large signal RF) while becoming deeply saturated. Contact deterioration, inverse piezoelectric effect, hot electron effect, and self-heating are some of the common problems. For example, when the temperature is greater than about 300°C, Schottky and ohmic contacts may exhibit increased contact resistance and passivation cracking. Inter-diffusion within the gate metal stack and out-diffusion of gallium into the metal layer may occur. When electrons accelerate in a large electric field to obtain very high kinetic energy, the hot electron effect may occur. The hot electron effect may cause trap formation in the aluminum gallium nitride (AlGaN) layer, the AlGaN/GaN interface, the passivation layer/GaN cap layer interface, and the buffer layer.

The well formation may then cause current collapse and gate delay, and thus cause reversible degradation of the mutual conductance and saturation of the drain current. Even if the drain voltage or the gate voltage changes suddenly, a slow transient current is observed. The transient response of the slow drain current during pulsed drain-source voltage is called drain lag, or gate lag in the case of gate-source voltage. When the voltage in the pulse is higher than the static bias point, the buffer trap traps free charge. Compared with the pulse length, this phenomenon is very fast. When the voltage in the pulse is lower than the static bias point, the trap releases its charge. This process may be very slow, and may even take a few seconds. When free carriers are captured and released, they will not immediately contribute to the output current. This phenomenon is at the beginning of the transient current.

The combined effect of slow drain and slow gate leads to current collapse (decreased density of two-dimensional electron gas [2-DEG]). When the deep-acceptor density in the buffer layer is higher, the gate delay caused by the buffer well becomes more obvious. When the high reverse bias on the gate leads to the generation of crystal defects, the reverse piezoelectric effect may occur. When a certain threshold voltage is exceeded, irreversible damage to the component may occur, which may provide a leakage path through the defect. Self-heating may occur under high electrical stress and may cause thermal stress-strain. Compound semiconductor devices may also suffer from electric field-driven degradation, such as gate metallization and degradation of contacts, surfaces, and interfaces. Deterioration of the gate may lead to increased leakage current and dielectric breakdown.

The high temperature reverse bias (HTRB) test is one of the most common reliability tests used for power components. The HTRB test evaluates long-term stability under high drain-source bias. The HTRB test attempts to accelerate the failure mechanism thermally activated by operating conditions using bias voltage. During the HTRB test, the component sample is stressed at the maximum stage reverse breakdown voltage or slightly less than the maximum stage reverse breakdown voltage, and at an ambient temperature close to its maximum stage junction temperature for an extended period of time (eg, 1000 hours). According to the Arrhenius equation, the high-temperature accelerated failure mechanism of this test, the Arrhenius equation indicates that the reaction rate depends on temperature. During the HTRB test, delamination, bursting, component expansion and other mechanical problems may occur.

A failure mechanism similar to time-dependent dielectric breakdown (TDDB) is also observed in the gate dielectric of wide band gap semiconductor devices such as GaN power devices. TDDB is a common failure mechanism in MOSFETs. TDDB occurs when the gate dielectric collapses because of the long-term application of a relatively low electric field (as opposed to immediate breakdown, which is caused by a strong electric field). In addition, failure during temperature cycling (TMCL) may be related to package stress, bond pad metallization, mold compounding, moisture sensitivity, and other package level issues.

As discussed above, the engineered substrate may have a CTE that matches the CTE of the epitaxial GaN device layer grown thereon. The epitaxial GaN device layer can also be lattice-matched with the engineering substrate. Therefore, the epitaxial GaN device layer can have lower defect density and better quality. A relatively thick drift region can be formed through epitaxial growth. In addition, large-diameter wafers can be made from engineered substrates, thereby reducing manufacturing costs. Engineering substrates can improve component reliability. For example, having a CTE that matches an epitaxial GaN device can help alleviate thermal stress, which is a key factor in device reliability. Component failures related to thermal stress may include thermally activated drain-source collapse, punch-through effects, collapse along the channel, and collapse through the buffer layer. It can also reduce self-heating. In addition, a high-quality epitaxial GaN layer with a low defect density can help improve the reliability of the device, because some defects may be caused by voltage stress and may cause lateral and vertical leakage. High-quality epitaxial GaN layers can also solve problems such as local non-stoichiometric regions that can affect field distribution and dislocation density.

Traditional silicon-based MOSFET technology has almost reached the physical limits of performance and switching speed. Lateral GaN-based high electron mobility transistors (HEMT) provide opportunities to go beyond the range of silicon-based MOSFETs in medium to low power systems, such as solar inverters and small power supplies (PFC) , Switching Mode Power Supply (SMPS), Motor Driver, RF Power Amplifier, Solid State Lighting (SSL), Smart Grid, and Automotive Motor Drive System. Among many other advantages, lateral GaN-based HEMTs can support high efficiency, high frequency operation, and low switching and conduction losses.

FIG. 9 is a simplified schematic cross-sectional view illustrating a lateral power element 900 formed on an engineering substrate 910 according to an embodiment of the present invention. The power element 900 can be used as a depleted (usually ON) HEMT. The power element 900 includes an engineered substrate 910. In some embodiments, as described above with reference to FIGS. 1, 3, and 4, the engineering substrate 910 may include a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, and a barrier coupled to the first adhesive layer Layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. According to an embodiment, the engineering substrate 910 may further include a substantially single crystal layer 912 coupled to the bonding layer. For example, the substantially single crystal layer 912 may include a substantially single layer of crystalline silicon. In some embodiments, the engineering substrate 910 may further include a nucleation layer 914 coupled to the substantially single crystal layer 912 to facilitate the formation of a GaN material-based epitaxial device layer including a substantially single crystal. In some embodiments, the nucleation layer 914 may be doped to an extent equal to, smaller than, or larger than the surrounding layers. In other embodiments, the composition of the nucleation layer can be designed and implemented with a predetermined composition.

In another embodiment, the polycrystalline ceramic core of the substrate 910 includes aluminum nitride. In some embodiments, as discussed above with reference to FIG. 1, the substrate 910 may further include a conductive layer coupled to the first adhesive layer, and a second adhesive layer coupled to the conductive layer, wherein the conductive layer and the second adhesive layer It is arranged between the first adhesive layer and the barrier layer. In some embodiments, the first adhesion layer may include a first TEOS oxide layer, and the second adhesion layer may include a second TEOS oxide layer. The barrier layer may include a silicon nitride layer. The conductive layer may include a polysilicon layer.

According to an embodiment, the power device 900 further includes a buffer layer 920 (eg, a gallium nitride (GaN) buffer layer) coupled to the nucleation layer 914 and the substantially single crystal layer 912. The buffer layer 920 may be formed on the nucleation layer 914 or the substantially single crystal layer 912 by epitaxial growth. According to an embodiment, the thickness of the buffer layer 920 may be greater than about 20 microns. In some embodiments, useful aluminum gallium nitride _{(i.e., Al x Ga 1-x N} ) substituted buffer layer a buffer layer 920, buffer layer 920, or may be combined as GaN and AlGaN layers. It should be noted that in some embodiments, the layer discussed with the GaN layer may be _{replaced with an Al x} Ga _1-x N layer. As an example, the buffer layer 920 having a first available group of Al _x Ga _1-x mole fraction of the unsubstituted N, and the barrier layer 932 may have a mole fraction of a second group of Al _x Ga _1-x N. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

A thicker buffer layer can provide the power device 900 with lower leakage current and higher breakdown voltage. In some embodiments, the buffer layer 920 may include a plurality of layers. For example, the buffer layer 920 may include an aluminum nitride layer, an aluminum gallium nitride layer, and a gallium nitride layer. In some embodiments, the buffer layer 920 may include a maximum of 150 layers of superlattices, and each layer has a thickness of about 2-3 nm. The superlattice is an artificial lattice produced by periodic epitaxial growth. A periodic superlattice is achieved by growing alternating layers of two semiconductors on top of each other, each semiconductor growing to the same thickness and molar fraction each time. According to some embodiments of the present invention, the advantage of using a superlattice instead of other buffer layer designs is that the superlattice can be grown to reduce sheet resistance, such as an AlGaN/GaN superlattice layer above the channel region, and can be Reduce the height of the potential energy barrier at the hetero-interface. In other embodiments, the superlattice does not reduce the height of the potential energy barrier at the hetero-interface. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

According to an embodiment, the power element 900 further includes a channel region 930 coupled to the buffer layer 920. The channel area 930 has a first end 924, a second end 926, and a central portion 928 disposed between the first end and the second end. The central portion of the channel region 930 may include a channel region barrier layer. In some embodiments, the channel region barrier layer may be a barrier layer 932 (eg, aluminum gallium nitride (Al _x Ga _1-x N) barrier layer) coupled to the buffer layer 920, and coupled to the barrier layer 932 capping layer 934 (eg, gallium nitride capping layer). The cap layer helps reduce the reverse leakage through the Schottky contact and reduces the peak electric field. It also protects the barrier layer 932 and prevents nitrogen outgassing during the manufacturing process. In addition, the cap layer 934 also has a positive effect on device performance, such as increased gain, increased power added efficiency, and improved DC stability.

The power element 900 further includes a source contact 940 disposed at the first end of the channel region 930, a drain contact 950 disposed at the second end of the channel region 930, and coupled to the cap layer 934 and disposed at the center of the channel region 930 Part of the gate contact 960. In some embodiments, the through hole 902 can connect the source contact 940 to the single crystal layer 912 to remove parasitic charges in the power device. In contrast to GaN-on-silicon that can pass through the backside contacts of the conductive silicon substrate, the insulating engineering substrate used in the embodiment of the present invention can utilize through holes such as through holes 902 to provide electrical connections to the single crystal layer 912. According to the embodiment of the present invention, the barrier layer 932 and the cap layer 934 are formed by epitaxial growth. As illustrated in FIG. 9, in operation, a thin layer 936 of two-dimensional electron gas (2DEG) may be formed in the buffer layer 920 at the interface between the buffer layer 920 and the barrier layer 932. The electrons in the two-dimensional electron gas thin layer 936 can move quickly without colliding with any impurities because the buffer layer 920 is undoped. This can give the channel 938 a very low resistance, in other words, a very high electron mobility.

In some embodiments, the power device 900 may further include a passivation layer 970 covering the cap layer 934. The passivation layer 970 may include silicon nitride or other insulating materials. The power device 900 may also include a first field plate metal 980 electrically connected to the source contact 940 to form a source electrode, and a second metal 990 disposed on the drain contact 950 to form a drain electrode.

FIG. 10 is a simplified flowchart illustrating a method 1000 for manufacturing a lateral power component on an engineering substrate according to an embodiment of the present invention. According to an embodiment, the method 1000 includes the following steps: at 1010, the substrate is formed by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core with a first adhesive shell; encapsulating the first adhesive shell with a barrier layer; Forming a bonding layer on the barrier layer; and bonding the substantially single crystal layer to the bonding layer.

The method 1000 further includes the following steps: in 1012, forming an epitaxial buffer layer (eg, a gallium nitride (GaN) buffer layer) on the substrate; and in 1014, forming a channel region on the buffer layer by the following steps: An epitaxial barrier layer (eg, aluminum gallium nitride (Al _x Ga _1-x N) barrier layer) is formed thereon, and an epitaxial cap layer (eg, gallium nitride cap layer) is formed on the barrier layer. The channel area has a first end and a second end, and a central portion between the first end and the second end.

The method 1000 further includes the following steps: at 1016, a source contact is formed at the first end of the channel region; at 1018, a drain contact is formed at the second end of the channel region; and at 1020, in the central part of the channel region A gate contact is formed on the cover layer.

It should be understood that the specific steps illustrated in Figure 10 provide a specific method for manufacturing an engineering substrate according to another embodiment of the present invention. According to alternative embodiments, other sequence of steps can also be performed. For example, alternative embodiments of the present invention may perform the steps in a different order than the foregoing outline. In addition, the individual steps illustrated in FIG. 10 may include multiple sub-steps, and the sub-steps may be executed in various sequences suitable for the individual steps. In addition, depending on the particular application, additional steps can be added or removed. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

FIG. 11A is a simplified schematic cross-sectional view illustrating a lateral power element 1100 formed on an engineering substrate according to another embodiment of the present invention. The power element 1100 may use the recess 1136 in the channel area 1130 as an enhanced (usually OFF) HEMT. The power element 1100 includes an engineered substrate 1110. In some embodiments, as described above with reference to FIGS. 1, 3, and 4, the engineering substrate 1110 may include a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, and a barrier coupled to the first adhesive layer. Layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. In some embodiments, the engineering substrate 1110 may further include a substantially single crystal layer 1112 coupled to the bonding layer. For example, the substantially single crystal layer 1112 may include substantially single crystal silicon. In some embodiments, the engineering substrate 1110 may further include a nucleation layer (not shown) coupled to the substantially single crystal layer 1112 to facilitate the formation of an epitaxial device layer.

In one embodiment, the polycrystalline ceramic core of the substrate 1110 includes aluminum nitride. In some embodiments, as discussed above with reference to FIG. 1, the substrate 1110 may further include a conductive layer coupled to the first adhesive layer, and a second adhesive layer coupled to the conductive layer, wherein the conductive layer and the second adhesive layer It is arranged between the first adhesive layer and the barrier layer. In some embodiments, the first adhesion layer may include a first TEOS oxide layer, and the second adhesion layer may include a second TEOS oxide layer. The barrier layer may include a silicon nitride layer. The conductive layer may include a polysilicon layer.

According to an embodiment, the power device 1100 further includes a buffer layer 1120 (eg, a gallium nitride (GaN) buffer layer) coupled to the substantially single crystal layer 1112. The buffer layer 1120 may be formed on the substantially single crystal layer 1112 by epitaxial growth. According to an embodiment, the buffer layer 1120 may have a thickness greater than about 20 microns. A thicker buffer layer can provide the power device 1100 with a lower leakage current and a higher breakdown voltage. In some embodiments, the buffer layer 1120 may include a plurality of layers. For example, the buffer layer 1120 may be a superlattice including an aluminum nitride layer, an aluminum gallium nitride layer, and a gallium nitride layer. It will be understood that one or more nucleation layers may be used in the growth process of the buffer layer 1120.

According to an embodiment, the power element 1100 further includes a channel region 1130 coupled to the buffer layer 1120. The passage area 1130 has a first end 1124, a second end 1126, and a central portion 1128 disposed between the first end 1124 and the second end 1126. The central portion of the channel region 1130 may include an epitaxial channel region barrier layer. In some embodiments, the epitaxial channel region barrier layer may be a barrier layer 1132 (eg, an aluminum gallium nitride (Al _x Ga _1-x N) barrier layer) coupled to the buffer layer 1120. According to an embodiment of the present invention, the barrier layer 1132 is formed by epitaxial growth. The barrier layer 1132 includes a recess 1136 in the central portion of the channel region 1130. The recess may be formed by removing a part of the barrier layer 1132 using etching or other suitable techniques. The power element 1100 further includes an insulating layer 1134 disposed in the recess and coupled to the barrier layer 1132.

The power element 1100 further includes a source contact 1140 disposed at the first end of the channel region 1130, a drain contact 1140 disposed at the second end of the channel region 1130, and coupled to the insulating layer 1134 and disposed at the center of the channel region 1130 Part of the gate contact 1160. In some embodiments, a through hole 1102 may be used to connect the source contact 1140 to the single crystal layer 1112 to remove parasitic charges in the power element 1100. As illustrated in FIG. 11, a two-dimensional electron gas (2DEG) thin layer 1138 may be formed in the buffer layer 1120 at the interface between the buffer layer 1120 and the barrier layer 1132. The electrons in the 2DEG thin layer 1138 can move quickly without colliding with any impurities because the buffer layer 1120 is undoped. This gives the channel region 1130 very low resistance, in other words, very high electron mobility. In the depletion type (usually OFF), when the gate voltage is zero, the recess 1136 and the insulating layer 1134 block part of the 2DEG.

In some embodiments, the buffer layer 1120 can be implemented as an aluminum gallium nitride (AlGaN) buffer layer. The AlGaN buffer layer may include multiple layers. The power device using the Al _x Ga _1-x N buffer layer can be manufactured to extend from the engineering substrate at a first predetermined molar fraction (x) and to be close to the source, gate, and drain contacts as the second predetermined gram _{The Al x} Ga _1-x N buffer layer of molecular fraction (x) is introduced into the channel region 1130. The first predetermined molar fraction (x) can be low, for example, less than 10% to provide the desired carrier limitation. In other embodiments, the aluminum molar fraction (x) ranges from 10% to 30%. The Al _x Ga _1-x N epitaxial layer can be doped with iron or carbon to further increase the resistance of the epitaxial layer as an insulating or barrier layer. Additional descriptions regarding the materials used for the epitaxial buffer layer and the manufacture of the epitaxial buffer layer are provided in U.S. Provisional Application No. 62/447,857, which is incorporated herein by reference in its entirety for all purposes.

FIG. 11B is a simplified schematic cross-sectional view illustrating a lateral power element 1190 with an epitaxial gate structure formed on an engineering substrate according to another embodiment of the present invention. By using, for example, a P-type gallium nitride-based structure 1162 to deplete the charge in the channel region under zero bias, the power device can be used as an enhanced (usually OFF) HEMT. The power element 1190 includes an engineered substrate 1110. In some embodiments, the engineering substrate 1110 may include the elements described above with reference to FIGS. 1, 3, and 4. According to an embodiment, the engineering substrate 1110 may further include a substantially single crystal layer 1112 coupled to the bonding layer.

In some embodiments, the power device 1190 further includes a buffer layer 1120 coupled to the substantially single crystal layer 1112. In some embodiments, the buffer layer may be another single crystal epitaxial layer, such as other III-V group materials, such as AlGaN, InGaN, InAlGaN, combinations of these, and so on. The power element 1190 may include a channel region 1130 coupled to the buffer layer 1120. The central part of the channel region may include a barrier layer 1132 coupled to the buffer layer 1120. According to the embodiment of the present invention, the barrier layer 1132 is formed by epitaxial growth.

The power element 1190 further includes a source contact 1140 provided at the first end of the channel region 1130, a drain contact 1150 provided at the second end of the channel region, and a gate contact 1164. In some embodiments, the gate contact 1164 may be a partial or half-ohm contact, such as titanium nitride. The partial ohmic gate contact 1164 can be coupled to the P-type GaN structure 1162. The partial ohmic gate contact 1164 is used to block the leakage current flowing if it is a full ohmic contact. The P-type gallium nitride structure 1162 can be formed by selectively etching the P-type gallium nitride epitaxial layer. In some embodiments, multiple epitaxial layers may be used to form the P-type gallium nitride structure 1162. When multiple epitaxial layers are used, one or more layers may include materials having a composition different from that of the barrier layer 1132 or materials different from each other, such as AlGaN or the like.

The properties related to the P-type gallium nitride structure 1162, such as stress and piezoelectric properties, can be adjusted to reduce or limit leakage current. The layers of the P-type gallium nitride structure can have different dopant concentrations. In some embodiments, when the gate voltage is zero, the P-type gallium nitride structure 1162 consumes part of the channel region 1130. The depleted area allows the power element 1190 to be used as an enhanced (usually OFF) HEMT.

Figure 11C is a simplified schematic cross-sectional view illustrating an exploded view of the P-type gallium nitride structure 1162. In some embodiments, the first layer 1170 may have a first dopant concentration and/or material composition. The second layer 1172 may have a second dopant concentration and/or material composition. The third layer 1174 may have a third dopant concentration and/or material composition. The unique CTE matching properties of the engineered substrate 1110 provide a substrate capable of supporting thicker and more complex epitaxial layer growth compared with the existing substrate technology. In some embodiments, the epitaxial gate structure may include at least one P-type gallium nitride epitaxial layer. The leakage current of the power element 119 can be controlled by the specific dopant concentration and/or material composition of the layer. Although Figure 11C illustrates a three-layer epitaxial layer, those with ordinary knowledge in the art will understand many changes, modifications, and options.

FIG. 12 is a simplified flowchart illustrating a method 1200 for manufacturing a lateral power component on an engineering substrate according to an embodiment of the present invention. According to an embodiment, the method 1200 includes the following steps: at 1210, the substrate is formed by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core with a first adhesive shell; encapsulating the first adhesive shell with a barrier layer; Forming a bonding layer on the barrier layer; and bonding the substantially single crystal layer to the bonding layer.

The method 1200 further includes the following steps: at 1212, forming an epitaxial buffer layer (e.g., gallium nitride (GaN) buffer layer) on the substrate; and at 1214, by forming an epitaxial barrier layer (e.g., Aluminum gallium nitride (Al _x Ga _1-x N) barrier layer) to form a channel region on the buffer layer. The channel area has a first end and a second end, and a central portion between the first end and the second end. According to an embodiment, the method 1200 further includes the following steps: at 1216, forming a recess in the barrier layer in the central portion of the channel region; and at 1218, forming an insulating layer in the recess. The insulating layer is coupled to the barrier layer. The method 1200 further includes the following steps: at 1220, forming a source contact at the first end of the channel region; at 1222, forming a drain contact at the second end of the channel region; and at 1224, in the central part of the channel region A gate contact is formed.

It should be understood that the specific steps illustrated in Figure 12 provide a specific method for manufacturing an engineering substrate according to another embodiment of the present invention. According to alternative embodiments, other sequence of steps can also be performed. For example, alternative embodiments of the present invention may perform the steps in a different order than the foregoing outline. In addition, the individual steps illustrated in FIG. 12 may include multiple sub-steps, and the sub-steps may be executed in various sequences suitable for the individual steps. In addition, depending on the particular application, additional steps can be added or removed. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

High power modules for vertical components (p-n diodes and HEMT) can have many applications. For example, they can be used to drive main motors and industrial motors in hybrid vehicle power systems. This type of device poses a particular challenge because it requires both high voltage and high current. Currently, these systems usually use SiC-based components. Due to their switching performance, the interest in using GaN-based devices continues to grow, and GaN-based devices provide a smaller bottom area. The engineering substrates described above can provide the potential for large-scale manufacturing of GaN-based components in CMOS-compatible Si wafer fabs.

FIG. 13 is a simplified schematic cross-sectional view illustrating a vertical semiconductor diode 1300 formed on an engineering substrate according to an embodiment of the present invention. The semiconductor diode 1300 includes an engineering substrate 1310. In some embodiments, as described above with reference to FIGS. 1, 3, and 4, the engineering substrate 1310 may include a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, and a barrier coupled to the first adhesive layer Layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. According to an embodiment, the engineering substrate 1310 may further include a substantially single crystal layer 1312 coupled to the bonding layer. For example, the substantially single crystal layer 1312 may include substantially single crystal silicon. In some embodiments, the engineering substrate 1310 may further include a nucleation layer (not shown) coupled to the substantially single crystal layer 1312 to facilitate the formation of the epitaxial device layer.

In one embodiment, the polycrystalline ceramic core of the substrate 1310 includes aluminum nitride. In some embodiments, as discussed above with reference to FIG. 1, the substrate 1310 may further include a conductive layer coupled to the first adhesive layer, and a second adhesive layer coupled to the conductive layer, wherein the conductive layer and the second adhesive layer It is arranged between the first adhesive layer and the barrier layer. In some embodiments, the first adhesion layer may include a first TEOS oxide layer, and the second adhesion layer may include a second TEOS oxide layer. The barrier layer may include a silicon nitride layer. The conductive layer may include a polysilicon layer.

According to an embodiment, the semiconductor diode 1300 further includes a buffer layer 1320 coupled to the substantially single crystal layer 1312. In some embodiments, the buffer layer 1320 may be a superlattice including a plurality of layers. For example, the buffer layer 1320 may include an aluminum nitride layer coupled to a single crystal silicon layer, an aluminum gallium nitride layer coupled to the aluminum nitride layer, and a gallium nitride layer coupled to the aluminum gallium nitride layer. The semiconductor diode 1300 further includes a semi-insulating layer 1330 coupled to the buffer layer 1320. In one embodiment, the semi-insulating layer 1330 includes gallium nitride.

According to some embodiments, the semiconductor diode 1300 further includes a first N-type gallium nitride layer 1342 coupled to the semi-insulating layer 1330, a second N-type gallium nitride layer 1344 coupled to the first N-type gallium nitride layer 1342 , And a P-type gallium nitride layer 1346 coupled to the second N-type gallium nitride layer 1344. The first N-type gallium nitride layer 1342 can be used as the N region of the P-N diode and can have a relatively high N-type doping concentration. The second N-type gallium nitride layer 1344 can be used as a drift region and has a relatively lower doping concentration than the first N-type gallium nitride layer 1342. The P-type gallium nitride layer 1346 can be used as the P region of the P-N diode and can have a relatively high P-type doping concentration.

In one embodiment, the portion of the second N-type gallium nitride layer 1344 and the portion of the P-type gallium nitride layer 1346 are removed to expose the portion of the first N-type gallium nitride layer 1342, so that the cathode contact 1370 can be Formed on it. In some embodiments, the cathode contact 1370 may include a titanium-aluminum (Ti/Al) alloy or other suitable metal materials. By etching or other suitable techniques, the portion of the second N-type gallium nitride layer 1344 and the portion of the P-type gallium nitride layer 1346 can be removed. The anode contact 1360 is formed on the remaining part of the P-type gallium nitride layer 1346. In some embodiments, the anode 1360 may include nickel-platinum (Ni/Pt) alloy, nickel-gold (Ni/Au) alloy, and so on. The semiconductor diode 1300 may further include a first field plate 1382 coupled to the anode contact 1360 and a second field plate 1384 coupled to the cathode contact 1370. In some embodiments, the semiconductor diode 1300 may further include a passivation layer covering the exposed surfaces of the P-type gallium nitride layer 1346 and the first N-type gallium nitride layer 1342, and the second N-type gallium nitride layer 1344 1390. The passivation layer 1390 may include silicon nitride or other insulating materials.

In some embodiments, the second N-type gallium nitride layer 1344 may have a thickness greater than 20 μm. The unique CTE matching properties of the engineered substrate 1310 provide the ability to deposit relatively thick drift regions with low dislocation density, provide the semiconductor diode 1300 with low leakage current and much higher breakdown voltage, as well as many other benefits.

FIG. 14 is a simplified flowchart illustrating a method 1400 of manufacturing a vertical semiconductor diode on an engineering substrate according to an embodiment of the present invention. The method 1400 includes the following steps: at 1410, the substrate is formed by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core with a first adhesive shell; encapsulating the first adhesive shell with a barrier layer; on the barrier layer Forming a bonding layer; and bonding the substantially single crystal layer to the bonding layer.

The method 1400 further includes the following steps: at 1412, a buffer layer is formed on the single crystal silicon layer; and at 1414, a semi-insulating layer is formed on the buffer layer. The method 1400 further includes the following steps: at 1416, forming a first epitaxial N-type gallium nitride layer on the semi-insulating layer; at 1418, forming a second epitaxial N-type gallium nitride layer on the first epitaxial N-type gallium nitride layer And at 1420, an epitaxial P-type gallium nitride layer is formed on the second epitaxial N-type gallium nitride layer. According to some embodiments, the first N-type gallium nitride layer has a first doping concentration. The second epitaxial N-type gallium nitride layer has a second doping concentration less than the first doping concentration.

According to some embodiments, the method 1400 further includes the following steps: at 1422, removing part of the second epitaxial N-type gallium nitride layer and part of the epitaxial P-type gallium nitride layer to expose the first epitaxial N-type gallium nitride layer Part of the gallium layer. The method 1400 further includes the following steps: at 1424, forming an anode contact on the remaining part of the epitaxial P-type gallium nitride layer; and at 1426, forming a cathode on the exposed part of the first epitaxial N-type gallium nitride layer contact.

It should be understood that the specific steps illustrated in Figure 14 provide a specific method for manufacturing an engineering substrate according to another embodiment of the present invention. According to alternative embodiments, other sequence of steps can also be performed. For example, alternative embodiments of the present invention may perform the steps in a different order than the foregoing outline. In addition, the individual steps illustrated in FIG. 14 may include multiple sub-steps, and the sub-steps may be executed in various sequences suitable for the individual steps. In addition, depending on the particular application, additional steps can be added or removed. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

FIG. 15 is a simplified schematic cross-sectional view illustrating a vertical semiconductor diode 1500 formed on an engineering substrate according to another embodiment of the present invention. The vertical semiconductor diode may include a first N-type gallium nitride layer 1542 coupled to the cathode contact 1570 (which may include a Ti/Al material) and a second N-type nitride layer 1542 coupled to the first N-type gallium nitride layer 1542. The gallium nitride layer 1544 and the P-type gallium nitride layer 1546 coupled to the second N-type gallium nitride layer 1544. The first N-type gallium nitride layer can be used as the N region of the P-N diode and can have a relatively high N-type doping concentration. The second N-type gallium nitride layer 1544 may serve as a drift region and may have a relatively low doping concentration compared with the doping concentration of the first N-type gallium nitride layer 1542. The P-type gallium nitride layer 1546 can be used as the P region of the P-N diode and can have a relatively high P-type doping concentration. In some embodiments, an epitaxial layer may be used to grow the first N-type gallium nitride layer 1542, the P-type gallium nitride layer 1546, and the second N-type gallium nitride layer 1544. The epitaxial layer can be grown on the engineering substrate as described above with reference to FIGS. 1, 3, and 4. The thickness of the epitaxial layer can be at least 10 µm and a diameter of 6 inches.

The vertical semiconductor diode 1500 is similar to the semiconductor diode 1300, except that the substrate 1310, the buffer layer 1320, and the semi-insulating layer 1330 are removed after the PN diode is formed, resulting in a "true" vertical device structure. The opposite side has an anode 1560 and a cathode 1584. In an alternative embodiment, part of the substrate 1310, the buffer layer 1320, and the semi-insulating layer 1330 form contact windows. The contact window can be used to create a vertical element structure with anode 1560 and cathode 1584 on opposite sides of the wafer.

In some embodiments, by removing the engineering substrate 1310, the buffer layer 1320, and the semi-insulating layer 1330 from the structure illustrated in FIG. 13, the thermal resistance of the semiconductor diode 1500 can be reduced. In some embodiments, the vertical semiconductor diode 1500 can be transferred to copper, which can serve as a cathode electrical contact. The plated copper can also be used as a heat sink for the vertical semiconductor diode 1500. The thickness of copper may be 30 µm and the thickness combined with the first N-type gallium nitride layer 1542, the second N-type gallium nitride layer 1544, and the P-type gallium nitride layer 1546 may be less than or equal to 150 µm. In this embodiment, the thermal resistance of the vertical semiconductor diode may be less than or equal to 0.2 K*mm ² /W. In this embodiment, the thermal resistance can be less than 4 times that of a diode formed by using an epitaxial gallium nitride layer on a gallium nitride substrate.

In other embodiments, a deposited diamond layer may be formed to provide electrical connection to the first N-type gallium nitride layer 1542, to improve thermal resistance, and/or to provide a cathode electrical contact 1584. Chemical vapor deposition can be used to form the deposited diamond layer. The deposited diamond layer may be doped to form an N-type diamond layer. The deposited diamond layer can be a heat sink for power components. In some embodiments, the thickness of the deposited diamond layer may be 20 µm-50 µm. It should be understood that a combination of materials can be used to form the cathode electrical contacts, including copper and deposited diamond layers.

In some configurations, the epitaxial layer of the adjacent substrate has a higher defect rate than the epitaxial layer further grown from the interface of the substrate. Defects can include, for example, impurities, crystal mismatch, and dislocation. Defects in these initial layers can result in a high percentage of device resistance. The unique CTE matching property of the engineering substrate 1310 illustrated in Figure 13 allows the first N-type gallium nitride layer 1542 of the adjacent engineering substrate 1310 to be thicker than the epitaxial layer grown on the conventional substrate. In some embodiments, in addition to removing the engineering substrate 1310, the first N-type gallium nitride layer 1542 of the adjacent engineering substrate 1310 can also be removed. In some embodiments, after the substrate and the initial higher defect epitaxial layer are removed, the cathode electrical contact 1584 can be directly formed on the high-quality gallium nitride epitaxial layer.

Although removing the engineering substrate adds an additional process step, since the power-operating contacts are formed on two different sides of the wafer, it can reduce metallization, improve current propagation and heat dissipation, and reduce electrical resistance. In some embodiments, in order to provide low resistance, the dopant concentration of the first N-type gallium nitride layer 1542 may be on the order of 3 x 10 ¹⁸ cm ^-3 to 5 x 10 ¹⁸ cm ^-3 . In some embodiments, the resistance may be less than or equal to 0.1 Ohm*mm ² . Moreover, for the vertical semiconductor diode 1300 illustrated in FIG. 13, the anode contact 1360 should not be too close to the sidewall of the adjacent cathode contact 1370, because otherwise there may be a breakdown between the anode contact 1360 and the cathode contact 1370. The vertical semiconductor diode 1500 eliminates this consideration.

FIG. 16 is a simplified flowchart illustrating a method 1600 for manufacturing a vertical semiconductor diode on an engineering substrate according to an embodiment of the present invention. The method 1600 includes the following steps: at 1610, a substrate is formed by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core with a first adhesive shell; encapsulating the first adhesive shell with a barrier layer; on the barrier layer Forming a bonding layer; and bonding the substantially single crystal layer to the bonding layer.

The method 1600 further includes the following steps: at 1612, a buffer layer is formed on the single crystal silicon layer; and at 1614, a semi-insulating layer is formed on the buffer layer. The method 1600 further includes the following steps: at 1616, forming a first epitaxial N-type gallium nitride layer on the semi-insulating layer; at 1618, forming a second epitaxial N-type gallium nitride layer on the first epitaxial N-type gallium nitride layer And at 1620, an epitaxial P-type gallium nitride layer is formed on the second epitaxial N-type gallium nitride layer. According to some embodiments, the first N-type gallium nitride layer has a first doping concentration. The second epitaxial N-type gallium nitride layer has a second doping concentration less than the first doping concentration.

According to some embodiments, the method 1600 further includes the following steps: at 1622, removing the substrate, the buffer layer, and the semi-insulating layer to expose the bottom surface of the first N-type gallium nitride layer. In some embodiments, the initial layer of the first N-type gallium nitride layer may be removed. Several techniques can be used to remove engineered substrates, buffer layers, and semi-insulating layers. For example, a chemical substance such as hydrofluoric acid (HF) can be injected into the side of the wafer that maintains the vertical semiconductor diode to etch away one or more of the buffer layer and the semi-insulating layer, and the ceramic core and the vertical semiconductor The diode epitaxial stack remains intact. Etching away one or more of the buffer layer and the semi-insulating layer separates the vertical semiconductor diode epitaxial stack from the remaining engineering substrate, while retaining the ceramic core for reuse. By eliminating the polishing process, this chemical lift-off process also reduces the overall stress on the vertical semiconductor diode epitaxial stack. If a gallium nitride substrate is used, the substrate cannot be selectively removed. In addition, the gallium nitride substrate includes defects that affect the quality of the epitaxial layer grown thereon, such as face flipping, residual stress, fragility, and miscutting planes. In some embodiments, when using a gallium nitride substrate, 75% of the resistance may come from defects in the substrate. The embodiment of the present invention in which the substrate is removed to expose the epitaxial layer for contact formation can thus reduce electrical resistance and thermal resistance.

In some embodiments, a sacrificial layer may be used in a chemical lift-off process. The sacrificial layer may use a metal, such as titanium (Ti), which is easily dissolved when exposed to HF. In some embodiments, the sacrificial layer may include titanium (Ti), vanadium (V), chromium (Cr), tantalum (Ta), tungsten (W), rhenium (Re), silicon oxide, silicon nitride, silicon oxynitride Or one of their combinations. In addition to the sacrificial layer, a protective layer can be used. The protective layer can prevent the diffusion of the material such as Ti from the sacrificial layer 200 to the GaN epitaxial layer during the growth of the epitaxial GaN. Additional descriptions regarding the removal of the substrate, the buffer layer, and the semi-insulating layer are provided in US Application No. 15/288,506, which is incorporated herein by reference in its entirety for all purposes. The described substrate removal process for vertical semiconductor diodes can be used for any of the components described herein. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

The method further includes the following steps: at 1624, an anode contact is formed on the epitaxial P-type gallium nitride layer; and at 1626, a cathode contact is formed on the bottom surface of the first epitaxial N-type gallium nitride layer.

It should be understood that the specific steps illustrated in Figure 16 provide a specific method for manufacturing an engineering substrate according to another embodiment of the present invention. According to alternative embodiments, other sequence of steps can also be performed. For example, alternative embodiments of the present invention may perform the steps in a different order than the foregoing outline. In addition, the individual steps illustrated in FIG. 16 may include multiple sub-steps, and the sub-steps may be executed in various sequences suitable for the individual steps. In addition, depending on the particular application, additional steps can be added or removed. Those with ordinary knowledge in the technical field will understand many changes, modifications and choices.

It is possible to operate electrical components in severe thermal conditions. For example, power components can withstand thermal cycles of up to hundreds of degrees Celsius. Some local hot spots can reach up to 250°C. Thermal cycling and inherent stress may cause reliability failures, such as delamination, dielectric breakdown, and so on. Therefore, forming a GaN device layer on an engineering substrate characterized by a CTE that substantially matches the CTE of the power device can eliminate or alleviate this reliability failure because the GaN device layer can expand and contract at the same rate as the engineering substrate.

FIG. 17 is a simplified schematic cross-sectional view illustrating a semiconductor device 1700 formed on an engineering substrate 1710 according to an embodiment of the present invention. The semiconductor element 1700 includes a substrate 1710. In some embodiments, as described above with reference to FIGS. 1, 3, and 4, the engineering substrate 1710 may include a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, and a barrier coupled to the first adhesive layer. Layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. According to an embodiment, the engineering substrate 1710 may further include a substantially single crystal layer coupled to the bonding layer. For example, the substantially single crystal layer may include substantially single crystal silicon.

In one embodiment, the polycrystalline ceramic core of the substrate 1710 includes aluminum nitride. In some embodiments, as discussed above with reference to FIG. 1, the substrate 1710 may further include a conductive layer coupled to the first adhesive layer, and a second adhesive layer coupled to the conductive layer, wherein the conductive layer and the second adhesive layer It is arranged between the first adhesive layer and the barrier layer. In some embodiments, the first adhesion layer may include a first TEOS oxide layer, and the second adhesion layer may include a second TEOS oxide layer. The barrier layer may include a silicon nitride layer. The conductive layer may include a polysilicon layer.

The semiconductor device 1700 includes a device structure 1720 formed on an engineering substrate 1710. According to some embodiments, the element structure 1720 may include a plurality of epitaxial gallium nitride-based layers grown on the substantially single crystal layer of the substrate 1710, wherein the thermal expansion coefficient of the plurality of epitaxial gallium nitride layers is the same as the thermal expansion of the substrate 1710 The coefficients are essentially equal.

It is also understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes in view of them will be suggested to those with ordinary knowledge in the technical field, and such modifications or changes are included in this application. And the spirit and scope of the scope of patent application attached hereto.

100‧‧‧Engineering substrate 110‧‧‧Core 112‧‧‧Adhesive layer 114‧‧‧Conductive layer 116‧‧‧Adhesive layer 118‧‧‧Barrier layer 120‧‧‧Engineering layer 122‧‧‧Single crystal layer 130 ‧‧‧Epitaxial material 202‧‧‧Depth 204‧‧‧Species concentration 206‧‧‧Ion signal intensity 208‧‧‧Line 210‧‧‧Calcium 220‧‧‧Yttrium 230‧‧‧Aluminum 240‧‧‧Dotted line 300 ‧‧‧Engineering substrate 314‧‧‧Conductive layer 316‧‧‧Adhesive layer 400‧‧‧Engineering substrate structure 412‧‧‧Adhesive layer 414‧‧‧Conductive layer 416‧‧‧Adhesive layer 418‧‧‧Barrier layer 500 ‧‧‧Method 510, 512, 514, 516, 518, 520, 522‧‧‧ (step) 600‧‧‧ Method 610, 612, 614, 616, 618, 620, 622‧‧‧ (step) 700‧‧ ‧Epitaxial/engineering substrate structure 710‧‧‧Engineering substrate structure 720‧‧‧Epitaxial single crystal layer 800‧‧‧Double epitaxial structure 810‧‧‧Engineering substrate structure 820‧‧‧III-V epitaxial layer 822 ‧‧‧Conductive epitaxial layer 824‧‧‧Through hole 826‧‧‧Through hole 828‧‧‧Lateral through hole 830‧‧‧Double epitaxial structure 840‧‧‧Double epitaxial structure 850‧‧‧Double epitaxial Structure 860‧‧‧Double epitaxial structure 862‧‧‧Edge 900‧‧‧ Lateral power element 902‧‧‧Through hole 910‧‧‧Engineering substrate 912‧‧‧Essential single crystal layer 914‧‧‧ Nucleation layer 920‧‧‧Buffer layer 924‧‧‧First end 926‧‧‧Second end 928‧‧‧Central part 930‧‧‧Passage area 932‧‧‧Barrier layer 934‧‧‧Cover layer 936‧‧‧Two Dimensional electron gas thin layer 938‧‧‧channel 940‧‧‧source contact 950‧‧‧drain contact 960‧‧‧gate contact 970‧‧‧passivation layer 980‧‧‧metal 990‧‧‧ Bimetal 1000‧‧‧Methods 1010, 1012, 1014, 1016, 1018, 1020‧‧‧ (Steps) 1100‧‧‧Power components 1102‧‧‧Through hole 1110‧‧‧Engineering substrate 1112‧‧‧Essentially single crystal Layer 1120‧‧‧Buffer layer 1124‧‧‧First end 1126‧‧‧Second end 1128‧‧‧Central part 1130‧‧‧Passage area 1132‧‧‧Barrier layer 1134‧‧‧Insulation layer 1136‧‧‧ Recess 1138‧‧‧Two-dimensional electron gas (2DEG) thin layer 1140‧‧‧Source contact 1150‧‧‧Drain contact 1160‧‧‧Gate contact 1162‧‧‧P-type gallium nitride structure 1164‧ ‧‧Gate contact 1170‧‧‧First layer 1172‧‧‧Second layer 1174‧‧‧Third layer 1190‧‧‧Power components 1200‧‧‧Methods 1210, 1212, 1214, 1216, 1218, 1220, 1222, 12 24‧‧‧(Step) 1300‧‧‧Semiconductor diode 1310‧‧‧Engineering substrate 1312‧‧‧Essentially a single crystal layer 1320‧‧‧Buffer layer 1330‧‧‧Semi-insulating layer 1342‧‧‧N-type nitrogen Gallium layer 1344‧‧‧N-type gallium nitride layer 1346‧‧‧P-type gallium nitride layer 1360‧‧‧Anode contact 1370‧‧‧Cathode contact 1382‧‧‧First field plate 1384‧‧‧ Second field board 1390‧‧‧Passivation layer 1400‧‧‧Method 1410, 1412, 1414, 1416, 1418, 1420, 1422, 1424, 1426‧‧‧ (Step) 1500‧‧‧Vertical semiconductor diode 1542‧‧‧ N-type gallium nitride layer 1544‧‧‧N-type gallium nitride layer 1546‧‧‧P-type gallium nitride layer 1560‧‧‧Anode 1570‧‧‧Cathode contact 1584‧‧‧Cathode 1600‧‧‧Method 1610, 1612, 1614, 1616, 1618, 1620, 1622, 1624, 1626‧‧‧(Step)1700‧‧‧Semiconductor component 1710‧‧‧Engineering substrate 1720‧‧‧Component structure

Figure 1 is a simplified schematic cross-sectional view illustrating an engineering substrate structure according to an embodiment of the present invention.

Figure 2A is a SIMS data diagram illustrating the species concentration as a function of depth for an engineering structure according to an embodiment of the present invention.

Figure 2B is a SIMS data diagram illustrating the species concentration as a function of depth for an engineered structure after annealing according to an embodiment of the present invention.

Figure 2C is a SIMS data diagram illustrating the species concentration as a function of depth for an engineered structure with a silicon nitride layer after annealing according to an embodiment of the present invention.

Figure 3 is a simplified schematic cross-sectional view illustrating an engineering substrate structure according to another embodiment of the present invention.

Figure 4 is a simplified schematic cross-sectional view illustrating an engineering substrate structure according to another embodiment of the present invention.

FIG. 5 is a simplified flowchart illustrating a method of manufacturing an engineering substrate according to an embodiment of the present invention.

FIG. 6 is a simplified flowchart illustrating a method of manufacturing an engineering substrate according to another embodiment of the present invention.

Figure 7 is a simplified schematic cross-sectional view illustrating an epitaxial/engineered substrate structure for RF and power applications according to an embodiment of the present invention.

FIG. 8A is a simplified schematic diagram illustrating a III-V epitaxial layer on an engineering substrate structure according to an embodiment of the present invention.

FIG. 8B is a simplified schematic plan view illustrating a through hole configuration of a semiconductor device formed on an engineering substrate according to another embodiment of the present invention.

Figure 9 is a simplified schematic cross-sectional view illustrating a lateral power component formed on an engineering substrate according to an embodiment of the present invention.

FIG. 10 is a simplified flowchart illustrating a method of manufacturing a lateral power component on an engineering substrate according to an embodiment of the present invention.

Figure 11A is a simplified schematic cross-sectional view illustrating a lateral power element formed on an engineering substrate according to another embodiment of the present invention.

Figure 11B is a simplified schematic cross-sectional view illustrating a lateral power element formed on an engineering substrate according to another embodiment of the present invention.

FIG. 11C is a simplified schematic cross-sectional view illustrating an exploded view of a P-type gallium nitride structure according to an embodiment of the present invention.

FIG. 12 is a simplified flowchart illustrating a method of manufacturing a lateral power component on an engineering substrate according to another embodiment of the present invention.

Figure 13 is a simplified schematic cross-sectional view illustrating a vertical semiconductor diode formed on an engineering substrate according to an embodiment of the present invention.

FIG. 14 is a simplified flowchart illustrating a method of manufacturing a vertical semiconductor diode on an engineering substrate according to another embodiment of the present invention.

Figure 15 is a simplified schematic cross-sectional view illustrating a vertical semiconductor diode formed on an engineering substrate according to another embodiment of the present invention.

FIG. 16 is a simplified flowchart illustrating a method of manufacturing a vertical semiconductor diode on an engineering substrate according to another embodiment of the present invention.

Figure 17 is a simplified schematic cross-sectional view illustrating a semiconductor device formed on an engineering substrate according to an embodiment of the present invention.

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900‧‧‧Side power element

902‧‧‧Through hole

910‧‧‧Engineering substrate

912‧‧‧essentially single crystal layer

914‧‧‧nucleation layer

920‧‧‧Buffer layer

924‧‧‧First end

926‧‧‧Second end

928‧‧‧Central part

930‧‧‧Access area

932‧‧‧Barrier layer

934‧‧‧Cover

936‧‧‧Two-dimensional electron gas thin layer

938‧‧‧Channel

940‧‧‧source contact

950‧‧‧Dip pole contact

960‧‧‧Gate contact

970‧‧‧Passivation layer

980‧‧‧Metal

990‧‧‧Second Metal

Claims (40)

A power element, the power element comprising: a substrate comprising: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a barrier layer coupled to the first adhesive layer; coupling A bonding layer to the barrier layer; and a substantially single crystal layer coupled to the bonding layer; a buffer layer coupled to the substantially single crystal layer; a channel region coupled to the buffer layer, wherein the channel The region includes a first end, a second end, and a central portion disposed between the first end and the second end, the channel region includes a barrier layer of a channel region coupled to the buffer layer; A source contact at the first end of the channel region; a drain contact at the second end of the channel region; and a gate contact coupled to the channel region. The power device according to claim 1, further comprising: a cap layer coupled to the barrier layer of the channel region; and the gate contact coupled to the cap layer and disposed in the central portion of the channel region. The power device according to claim 1, further comprising: an insulating layer coupled to the barrier layer of the channel region, wherein the gate contact is coupled to the insulating layer; and a recess in the central portion of the channel region , Wherein the insulating layer and the gate contact are arranged in the recess. The power device according to claim 1, further comprising: an epitaxial gate structure coupled to the barrier layer of the channel region, wherein the gate contact is coupled to the epitaxial gate structure and disposed in the channel region Of that central part. The power device according to claim 4, wherein the epitaxial gate structure includes a P-type gallium nitride epitaxial layer. The power device according to claim 4, wherein the epitaxial gate structure includes a plurality of epitaxial layers, wherein each layer of the plurality of epitaxial layers is related to a layer of a specific dopant concentration. The power device according to claim 1, wherein the buffer layer and the channel region barrier layer are characterized by a CTE that is substantially equal to a coefficient of thermal expansion (CTE) of the substrate. The power device according to claim 1, further comprising: a conductive epitaxial layer coupled to the substantially single crystal layer. The power device according to claim 8, further comprising: a through hole connected between the source contact and at least one of the conductive epitaxial layer and the substantially single crystal layer. The power device according to claim 8, further comprising: a backside contact coupled to the conductive epitaxial layer, wherein the substrate is removed from the power device. The power device according to claim 1, wherein the buffer layer is formed by epitaxial growth. The power device according to claim 11, wherein a thickness of the buffer layer is greater than about 20 micrometers (µm). The power device according to claim 1, wherein the substrate further includes a nucleation layer coupled to the substantially single crystal layer. A method of forming a power element, the method comprising the following steps: forming a substrate by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core with a first adhesive shell; encapsulating with a barrier layer The first adhesive shell; forming a bonding layer on the barrier layer; and bonding a substantially single crystal layer to the bonding layer; forming a buffer layer on the substantially single crystal layer; A channel region is formed on the buffer layer: an epitaxial channel region barrier layer is formed on the buffer layer; wherein the channel region has a first end and a second end, and between the first end and the second end Forming a source contact at the first end of the channel region; forming a drain contact at the second end of the channel region; and forming a gate contact on the channel region . The method according to claim 14, further comprising the steps of: forming a cap layer on the barrier layer of the epitaxial channel region; and forming the gate contact on the cap layer in the central portion of the channel region . The method according to claim 14, further comprising the steps of: forming a recess in the barrier layer of the epitaxial channel region; forming an insulating layer in the recess, the insulating layer being coupled to the barrier layer of the epitaxial channel region And forming the gate contact on the insulating layer in the recess in the central portion of the channel region. The method according to claim 14, further comprising the steps of: forming an epitaxial gate structure coupled to the barrier layer of the epitaxial channel region in the central portion of the channel region; and in the center of the channel region The gate contact is formed on the epitaxial gate structure in the part. The method according to claim 17, wherein the epitaxial gate structure includes a P-type gallium nitride epitaxial layer. The method according to claim 17, wherein the step of forming the epitaxial gate structure includes the following steps: forming a plurality of epitaxial layers, wherein each layer of the plurality of epitaxial layers is related to a layer of a specific dopant concentration. The method according to claim 14, wherein the buffer layer and the epitaxial channel region barrier layer are characterized by a CTE that is substantially equal to a coefficient of thermal expansion (CTE) of the substrate. A semiconductor diode comprising: a substrate comprising: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a resistor coupled to the first adhesive layer Barrier layer; a bonding layer coupled to the barrier layer; and a substantially single crystal layer coupled to the bonding layer; a buffer layer coupled to the substantially single crystal layer; a half insulating layer coupled to the buffer layer ; A first N-type gallium nitride layer coupled to the semi-insulating layer, the first N-type gallium nitride layer having a first doping concentration; a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer N-type gallium nitride layer, the second N-type gallium nitride layer having a second doping concentration less than the first doping concentration; a P-type gallium nitride coupled to the second N-type gallium nitride layer Layer; an anode contact coupled to the P-type gallium nitride layer; and a cathode contact coupled to a portion of the first N-type gallium nitride layer. The semiconductor diode of claim 21, wherein the buffer layer comprises: an aluminum nitride layer coupled to the substantially single crystal layer; an aluminum gallium nitride layer coupled to the aluminum nitride layer; and coupling A gallium nitride layer to the aluminum gallium nitride layer. The semiconductor diode according to claim 21, wherein the semi-insulating layer includes gallium nitride. The semiconductor diode of claim 21, wherein the substrate further comprises: a conductive layer coupled to the first adhesive layer; and a second adhesive layer coupled to the conductive layer, wherein the conductive layer and the first adhesive layer Two adhesive layers are arranged between the first adhesive layer and the barrier layer. The semiconductor diode according to claim 21, wherein the first N-type gallium nitride layer, the second N-type gallium nitride layer, and the P-type gallium nitride layer are formed by epitaxial growth. The semiconductor diode according to claim 25, wherein one of the second N-type gallium nitride layers has a thickness greater than about 20 μm. The semiconductor diode according to claim 25, wherein the first N-type gallium nitride layer, the second N-type gallium nitride layer, and the P-type gallium nitride layer are characterized by a thermal expansion with the substrate The coefficient (CTE) is substantially equal to a CTE. A method of forming a semiconductor diode, the method comprising the following steps: forming a substrate by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core with a first adhesive shell; using a barrier layer Encapsulating the first adhesive shell; forming a bonding layer on the barrier layer; and bonding a substantially single crystal layer to the bonding layer; forming a buffer layer on the substantially single crystal layer; on the buffer layer A semi-insulating layer is formed on the semi-insulating layer; a first epitaxial N-type gallium nitride layer is formed on the semi-insulating layer, and the first epitaxial N-type gallium nitride layer has a first doping concentration; A second epitaxial N-type gallium nitride layer is formed on the N-type gallium nitride layer, and the second epitaxial N-type gallium nitride layer has a second doping concentration less than the first doping concentration; An epitaxial P-type gallium nitride layer is formed on the two epitaxial N-type gallium nitride layer; a part of the second epitaxial N-type gallium nitride layer and a part of the epitaxial P-type gallium nitride layer are removed to expose A portion of the first epitaxial N-type gallium nitride layer; forming an anode contact on a remaining portion of the epitaxial P-type gallium nitride layer; and exposing the first epitaxial N-type gallium nitride layer A cathode contact is formed on the part. The method according to claim 28, wherein the step of forming the substrate further comprises the following steps: encapsulating the first adhesive shell with a conductive shell; and encapsulating the conductive shell with a second adhesive shell, wherein the barrier layer Encapsulate the conductive shell. The method of claim 28, wherein a thickness of the second epitaxial N-type gallium nitride layer is greater than about 20 microns. The method according to claim 28, wherein the first epitaxial N-type gallium nitride layer, the second epitaxial N-type gallium nitride layer, and the epitaxial P-type gallium nitride layer are characterized by being in contact with the substrate A coefficient of thermal expansion (CTE) of is substantially equal to a CTE. The method of claim 28, wherein the polycrystalline ceramic core comprises aluminum nitride. The method of claim 28, wherein the substantially single crystal layer comprises a substantially single crystal silicon layer. A method of forming a semiconductor diode, the method comprising the following steps: forming a substrate by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core with a first adhesive shell; using a barrier layer Encapsulating the first adhesive shell; forming a bonding layer on the barrier layer; and bonding a substantially single crystal layer to the bonding layer; forming a first epitaxial N-type nitrogen on the substantially single crystal layer A gallium nitride layer, the first epitaxial N-type gallium nitride layer has a first doping concentration; a second epitaxial N-type gallium nitride layer is formed on the first epitaxial N-type gallium nitride layer, the The second epitaxial N-type gallium nitride layer has a second doping concentration lower than the first doping concentration; an epitaxial P-type gallium nitride layer is formed on the second epitaxial N-type gallium nitride layer; Removing a portion of the substrate to expose a surface of the first epitaxial N-type gallium nitride layer; forming an anode contact on the epitaxial P-type gallium nitride layer; and forming an anode contact on the first epitaxial N-type gallium nitride layer A cathode contact is formed on the exposed surface of the gallium layer. The method of claim 34, wherein the step of removing the portion of the substrate to expose the surface of the first epitaxial N-type gallium nitride layer further comprises the following steps: removing the first epitaxial N-type nitrogen Part of the gallium oxide layer. The method according to claim 34, wherein the step of forming the substrate further comprises the steps of: encapsulating the first adhesive shell with a conductive shell; and encapsulating the conductive shell with a second adhesive shell, wherein the barrier layer Encapsulate the conductive shell. The method of claim 34, wherein a thickness of the second epitaxial N-type gallium nitride layer is greater than about 20 microns. The method according to claim 34, wherein the first epitaxial N-type gallium nitride layer, the second epitaxial N-type gallium nitride layer, and the epitaxial P-type gallium nitride layer are characterized by being in contact with the substrate A coefficient of thermal expansion (CTE) of is substantially equal to a CTE. The method of claim 34, wherein the polycrystalline ceramic core comprises aluminum nitride. The method of claim 34, wherein the substantially single crystal layer comprises a substantially single crystal silicon layer.

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