JP7198195B2 - nitride semiconductor substrate - Google Patents

Description

The present invention particularly relates to nitride semiconductor substrates suitable for high frequency devices.

A nitride semiconductor substrate in which a nitride semiconductor layer is formed on an insulating substrate is used to fabricate a nitride semiconductor element for a high frequency device. For example, U.S. Pat. No. 5,300,003 discloses a top surface region having a resistivity greater than 10 ² Ω·cm and a maximum free carrier concentration less than 10 ¹⁷ /cm ³ , which is said to be suitable for high frequency applications with low parasitic losses. There is disclosed a semiconductor structure comprising a silicon substrate comprising a silicon substrate and a III-nitride material region formed overlying the top surface of the silicon substrate.

In recent years, high-frequency devices using nitride semiconductor substrates with a large diameter (6 inches or more) have been attracting attention. However, it cannot be said that the conventional nitride semiconductor substrate using silicon (Si) as the underlying substrate is sufficiently compatible with the increase in diameter and the increase in thickness of the nitride semiconductor layer.

In this respect, for example, in Patent Document 2, a compound semiconductor layer is provided on one main surface of an underlying substrate via a seed layer, the underlying substrate is made of a sintered body, and the seed layer is made of a single crystal. ,
The compound semiconductor layer has a structure in which a buffer layer crystal-grown on the seed layer and an active layer are sequentially laminated, and the thermal expansion coefficient of the sintered body is 0.0 of the average thermal expansion coefficient of the entire compound semiconductor layer. A compound semiconductor substrate is disclosed in which the ratio is 7 times or more and 1.4 times or less and the half width of the X-ray diffraction peak of the buffer layer is 800 arcsec or less. It is considered that such a technique can sufficiently cope with an increase in the diameter and an increase in the thickness of the nitride semiconductor layer.

Japanese Patent Publication No. 2008-522447 JP 2017-76687 A

However, in the invention described in Patent Document 2, simply applying the Si single crystal described in Patent Document 1 to the seed layer did not always provide sufficient characteristics other than the parasitic capacitance.

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a nitride semiconductor substrate suitable as a higher frequency device, particularly in a structure comprising a seed layer made of Si single crystals on a polycrystalline inorganic material substrate.

In the present invention, a substrate, a buffer layer made of a Group 13 nitride semiconductor, and an operating layer made of a Group 13 nitride semiconductor are laminated in this order, the substrate being a first substrate made of polycrystalline aluminum nitride; The second substrate is composed of a Si single crystal having a specific resistance of 100 Ω·cm or more provided on the first substrate, and the first substrate has an average grain size of 4.0 to 7.0 μm. .

By having such a configuration, a nitride semiconductor substrate suitable for manufacturing a high frequency device can be obtained.

According to the present invention, a nitride having a seed layer made of Si single crystal on a polycrystalline inorganic material is particularly suitable for fabricating high-frequency devices in response to a larger diameter and a thicker nitride semiconductor layer. A semiconductor substrate can be provided.

Schematic cross-sectional view showing a layer structure of a nitride semiconductor according to one embodiment of the present invention

The present invention will be described in detail below with reference to the drawings as well. In the nitride semiconductor substrate of the present invention, a substrate, a buffer layer made of a Group 13 nitride semiconductor, and an operating layer made of a Group 13 nitride semiconductor are laminated in this order, and the substrate is made of polycrystalline aluminum nitride. It is composed of a first substrate and a second substrate made of Si single crystal having a specific resistance of 100 Ω·cm or more provided on the first substrate, and the average grain size of AlN forming the first substrate is 3 to 9 μm. .

FIG. 1 is a schematic cross-sectional view showing a layer structure of a nitride semiconductor according to one embodiment of the present invention. It should be noted that the schematic diagrams shown in the present invention are schematic simplifications and exaggerated shapes for the sake of explanation, and the shapes, dimensions, and proportions of details differ from the actual ones. Reference numerals are omitted for the same configurations, and other configurations unnecessary for explanation are not described.

As shown in FIG. 1, the nitride semiconductor substrate Z is obtained by sequentially stacking a buffer layer B and an operating layer G on one main surface of a substrate W serving as a base. When used as a semiconductor element, an electrode E is provided. The substrate W further comprises a first substrate 1 made of polycrystalline aluminum nitride (AlN) and a second substrate 2 made of Si single crystal on the first substrate 1 .

The basic structure of the nitride semiconductor substrate Z is the same as that of the compound semiconductor substrate Z of the invention described in Patent Document 2, but the structure of the substrate W of the present invention has a feature not found in the prior art. . The details will be described later.

The nitride semiconductor in the present invention consists of at least one of group 13 elements such as Ga, Al, and indium (In), and nitrogen (N). Various elements such as oxygen (O), Si, and magnesium (Mg) may be doped as necessary.

A well-known structure can be appropriately applied to the buffer layer B depending on the application and purpose. In the present invention, the buffer layer B having a high resistance is suitable in consideration of its use in high-frequency devices. A high resistance is achieved by doping the nitride semiconductor layer with C or iron (Fe).

The operating layer G is illustrated in FIG. 1 by the electron transit layer 3 and the electron supply layer 4 having a larger bandgap than this, but is not particularly limited to these. , a p-type layer, etc., may be added as appropriate, and the layer thickness and impurity concentration of each of the layers described above are also appropriately designed according to the purpose.

In the present invention, as a large-diameter nitride semiconductor substrate suitable for high-frequency devices, the total thickness of the buffer layer B and the operating layer G is in the range of 5 to 20 μm. With a substrate made of a single material, it is difficult to obtain the levels of warpage and dislocation density required in recent years, even with a stack of nitride semiconductor layers of 5 μm, for example. Stacking is possible.

Increasing the thickness of the nitride semiconductor layer is preferable because it also contributes to the reduction of parasitic capacitance in high-frequency devices. However, the controllability of warpage is greatly deteriorated, and the manufacturing cost does not correspond to the improvement of the characteristics.

The substrate W is composed of a first substrate 1 made of polycrystalline AlN and a second substrate 2 made of Si single crystal provided on the first substrate 1 and having a specific resistance of 100 Ω·cm or more.

First, the first substrate 1 is made of polycrystalline AlN, and its basic configuration conforms to the compound semiconductor substrate Z described in Patent Document 2. The first substrate 1 may be a single AlN, but if necessary, at least one layer or more layers made of Si oxide film, Si nitride film, and other various inorganic materials are formed on the front and back surfaces of the substrate made of AlN. Complexes may be applied.

In particular, the thermal conductivity of the first substrate 1 should be higher than that of the second substrate 2 in order to effectively obtain the high heat dissipation required of the nitride semiconductor substrate. Si has a thermal conductivity of over 100 W/mK, whereas AlN can achieve a thermal conductivity in the range of 100 to 250 W/mK by optimizing the material design. However, AlN, which has high thermal conductivity, requires sufficient sintering to expel the grain boundary phase, resulting in large grain size and low mechanical strength. Considering the balance between heat dissipation and strength, the thermal conductivity of the first substrate 1 when Si is used for the second substrate 2 is preferably 150 to 200 W/mK.

In view of the above, the first substrate 1 has an average grain size of 3 to 9 μm. This average particle size is measured by the code method.

If the thermal conductivity of the first substrate 1 is to be 150 to 200 W/mK as described above, the particle size must be of a certain size. . Therefore, in the present invention, as an index for determining the average grain size of the first substrate 1, the balance between thermal conductivity and strength is taken into consideration.

If the average grain size is less than 3 μm, sufficient sintering cannot be completed, sufficient strength cannot be obtained, and a large amount of the grain boundary phase remains. mK becomes difficult. However, when the average grain size exceeds 9 μm through a sintering process, the grain boundary phase is reduced and sufficient thermal conductivity is obtained, but on the other hand, there is concern about a decrease in strength.

Considering the above circumstances, the average grain size of the first substrate 1 is set to 3 to 9 μm. More preferably, the average grain size of the first substrate 1 is 4.0-7.0 μm. Incidentally, the average particle size is appropriately adjusted by changing the particle size distribution of the raw material powder, the firing temperature, the type of binder, and other known techniques.

The second substrate 2 is a Si single crystal substrate provided on the first substrate 1 and having a specific resistance of 100 Ω·cm or more. From the viewpoint of being suitable as a high-frequency device, the second substrate 2 has a high resistance following the technical idea described in Patent Document 1, and has a specific resistance of at least 100 Ω·cm.

In the present invention, it is preferable that the second substrate 2 is manufactured by the MCZ method. Generally, when a Si single crystal is used for a high-frequency device substrate, a Si single crystal substrate (FZ wafer) manufactured by the FZ method is used for the purpose of obtaining high resistance. On the other hand, there is a Si single crystal substrate (MCZ wafer) manufactured by the MCZ method, which is not as high resistance as the FZ method but can be manufactured relatively inexpensively, and this MCZ wafer is applied in the present invention.

However, when high-resistance Si is used for the second substrate 2 for the purpose of reducing parasitic capacitance, compared with the first substrate 1 made of polycrystalline AlN, the buffer layer B made of a nitride semiconductor, and the operation layer G, Then, Si, which has a high resistance, is inferior in strength to both.

In particular, in a structure in which layers having higher strength than the second substrate 2 are formed above and below the second substrate 2, the stress due to warping and strain generated in the entire nitride semiconductor substrate Z is the second substrate with the lowest strength. Concentrate on 2. If the second substrate 2 is an FZ wafer, there arises a concern that this stress concentration cannot be endured.

Therefore, as a preferred aspect of the present invention, the second substrate 2 is an MCZ wafer that has high resistance, high oxygen concentration, and excellent strength, although it is inferior in the effect of reducing parasitic capacitance compared to the FZ wafer. be.

When an MCZ wafer is used for the second substrate 2, the effect of reducing parasitic capacitance is relatively inferior to when an FZ wafer is used. In the present invention, the thickness of the buffer layer B can be increased by using the polycrystalline AlN of the present invention (average grain size: 3 to 9 μm) for the first substrate 1 .

More preferably, the second substrate 2 of the present invention has an oxygen concentration of 1E+18 to 9E+18 atoms/cm ³ and a specific resistance of 100 to 1000 Ω·cm. If the specific resistance of the second substrate 2 is less than 100 Ω·cm, the effect of reducing the parasitic capacitance cannot be sufficiently obtained, and if it exceeds 1000 Ω·cm, the oxygen concentration cannot be made higher than 1E+18 atoms/cm ³ . There is a concern that the required strength cannot be maintained as a whole. However, if the oxygen concentration exceeds 9E+18 atoms/cm ³ , although the strength (hardness) is sufficient, the material becomes brittle, which is not preferable.

If the second substrate 2 is too thick, its strength is insufficient compared to the first substrate 1 and each nitride semiconductor layer, so there is a risk of warping or peeling of the outer peripheral film. Therefore, especially when the diameter of the substrate W is 6 inches or more, the thickness is preferably 0.1 to 1.0 μm.

The substrate W is obtained by bonding the first substrate 1 and the second substrate 2 together using a known substrate bonding technique. At that time, for example, a silicon oxide film (about 500 to 1000 nm thick) may be interposed at the interface between the first substrate 1 and the second substrate 2 .

As described above, the nitride semiconductor substrate Z using the substrate W of the present invention has an appropriate thermal conductivity (achieved with an average grain size of 3 to 9 μm of the first substrate 1) and secures the strength of the substrate (the thickness of the first substrate 1 (Average grain size + second substrate 2 achieved by combining MCZ wafer) and sufficient parasitic capacitance reduction effect (achieved by increasing the thickness of the buffer layer B due to the above-mentioned improvement in substrate strength) can be obtained at the same time. be able to.

EXAMPLES The present invention will be specifically described below based on experimental examples, but the present invention is not limited to these.

(Preparation of first substrate 1)
A substrate made of AlN sintered body having a diameter of 6 inches and a thickness of 1000 μm was prepared as the first substrate 1 . One main surface of the base substrate was mirror-finished by a known polishing method so as to have an arithmetic mean roughness Ra of 100 nm or less. The average grain size of AlN on this mirror surface was 5 μm.

(Preparation of second substrate 2)
An MCZ wafer having a diameter of 6 inches, a thickness of 675 μm, a plane orientation of (111), a resistivity of 500 Ω·cm, and an oxygen concentration of 3E+18 atoms/cm ³ was prepared. After mirror-finishing this one side to an arithmetic mean roughness Ra of 50 nm, this was subjected to oxidation treatment at 1000° C. for 2 hours in a 100% oxygen atmosphere using a heat treatment furnace for semiconductors to form an oxide film on the mirror surface. .

(Fabrication of Substrate W ~ Bonding and Polishing of First Substrate 1 and Second Substrate 2)
After bonding the mirror surface of the first substrate 1 and the mirror surface of the second substrate 2 prepared as described above by thermocompression bonding by a known method, the surfaces are polished until the thickness of the second substrate 2 reaches 0.5 μm. It was ground and finally mirror-finished with an arithmetic mean roughness Ra of 50 nm. A substrate W was obtained as described above.

[Conditions for manufacturing buffer layer B]
Next, using trimethylaluminum (TMAl), trimethylgallium (TMGa), and ammonia (NH ₃ ) as raw materials, an initial layer in which an Al _0.2 Ga _0.8 N layer of 150 nm is laminated on an AlN layer of 100 nm, an AlN layer of 5 nm and an Al A buffer layer B was formed by stacking a multi-layer stack of 30 nm _0.2 Ga _0.8 N layers repeated 20 times and a single GaN layer of 7300 nm thickness in the order described above. Here, the layer thickness of the buffer layer B is 8000 nm.

[Manufacturing Conditions for Operating Layer G]
Next, in the active layer G, the electron transit layer 3 is a GaN layer of 100 nm, and the electron supply layer 4 is an Al _0.22 Ga _0.78 N layer of 20 nm, which are laminated in this order. Here, the growth conditions for the buffer layer B and the operating layer G were changed as appropriate when growing each layer, using a growth temperature of 1050° C. and a growth pressure of 60 hPa as approximate reference values. As described above, the nitride semiconductor substrate Z of Experimental Example 1 was produced.
Nitride semiconductor substrates Z of Experimental Examples 2 to 10 were produced according to Experimental Example 1, except that the average grain size of the first substrate 1 and the oxygen concentration and resistivity of the second substrate 2 were changed as shown in Table 1. was made.

(Reference example)
The first substrate 1 is not applied to the substrate W, and the second substrate 2 is manufactured by the FZ method with a diameter of 4 inches, a thickness of 525 μm, a plane orientation of (111), a specific resistance of 2000 Ω·cm, and an oxygen concentration of 1E+17 atoms/cm ³ . A nitride semiconductor substrate of Reference Example was fabricated according to Experimental Example 1, except that the Si single-crystal substrate was used as a single-crystal Si substrate, and the GaN layer of the buffer layer B was 500 nm. And this was used as a benchmark for parasitic capacitance.

(Evaluation 1 to high frequency characteristics)
The high-frequency characteristics are obtained by forming a pair of aluminum electrodes on the surface of the samples of Experimental Examples 1 to 10 and Reference Example, measuring the reflection coefficient between the electrodes using a vector network analyzer, and converting the resulting impedance. was evaluated by regarding the reactance component of the parasitic capacitance. The measurement frequency was 5 GHz. Comparison between samples was performed using relative values normalized by the measured values of Experimental Example 1.

(Evaluation 2 to substrate strength)
The substrate strength was evaluated by the warp of the nitride semiconductor substrate Z. That is, the warp (BOW value) of the entire substrate was measured and compared using a known semiconductor wafer warp measuring device. Then, -70 μm or more and +50 μm or less were evaluated as acceptable (◯), and those outside this range were evaluated as unacceptable (x).

(Evaluation 3 ~ thermal conductivity)
The thermal conductivity in the thickness direction of the samples was compared by the laser flash method using the nitride semiconductor substrates Z of Experimental Examples 1 to 10 and Reference Example. In the laser flash method, the thermal conductivity can be obtained by measuring the thermal diffusivity and multiplying it by the specific heat and density of the sample. It is difficult to In this experiment, since the shape parameters of the samples were common, the measured value of the thermal diffusion coefficient obtained by assuming a certain parameter was used as an index representing the difference in thermal conductivity between the samples. Similar to the parasitic capacitance, comparison between samples was performed using relative values normalized by the measured values of Experimental Example 1.

A plurality of experimental examples in which the average grain size of the first substrate 1 and the oxygen concentration or specific resistance of the second substrate 2 were changed were produced as shown in Table 1 below. At this time, all of them were produced according to Experimental Example 1 except for the changed parameters.

Table 1 summarizes the above-described reference examples, the conditions of each experimental example, and the evaluation results thereof.

As is clear from the results in Table 1, Experimental Examples 1 to 7 within the scope of the present invention have good warpage and thermal conductivity, and the parasitic capacitance exceeds the reference example using the FZ wafer. I can say. On the other hand, Experimental Examples 8, 9, and 10, which are outside the scope of the present invention, are inferior to Experimental Examples 1 to 7 in any of parasitic capacitance, warpage, and thermal conductivity. , a crack occurred in the substrate.

W substrate 1 first substrate (polycrystalline AlN)
2 Second substrate (Si single crystal)
B buffer layer E electrode G operation layer 3 electron transit layer 4 electron supply layer

Claims (1)

A substrate, a buffer layer made of a Group 13 nitride semiconductor, and an operating layer made of a Group 13 nitride semiconductor are laminated in this order, and the substrates are a first substrate made of polycrystalline aluminum nitride, and the first substrate. The second substrate is composed of a Si single crystal having a specific resistance of 100 Ω·cm or more provided on the second substrate, and the average grain size of AlN forming the first substrate is 4.0 to 7.0 μm. nitride semiconductor substrate.

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