CN113658859A - Preparation method of gallium nitride power device - Google Patents
Preparation method of gallium nitride power device Download PDFInfo
- Publication number
- CN113658859A CN113658859A CN202110743594.5A CN202110743594A CN113658859A CN 113658859 A CN113658859 A CN 113658859A CN 202110743594 A CN202110743594 A CN 202110743594A CN 113658859 A CN113658859 A CN 113658859A
- Authority
- CN
- China
- Prior art keywords
- substrate
- gallium nitride
- power device
- region
- type gan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 58
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000005516 engineering process Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- KRHYYFGTRYWZRS-UHFFFAOYSA-N hydrofluoric acid Substances F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000001704 evaporation Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 229910001020 Au alloy Inorganic materials 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 2
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 2
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910052593 corundum Inorganic materials 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 6
- 230000002441 reversible effect Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 239000000243 solution Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000008020 evaporation Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a gallium nitride power device. Longitudinal conduction of the device is realized through a substrate stripping technology, dependence on the GaN self-supporting substrate can be effectively relieved in the middle and low voltage application field, and the manufacturing cost of the device is greatly reduced; the terminal structure is manufactured by adopting a selective area epitaxial p-type GaN method, so that lattice damage caused by ion injection or etching is avoided, p-type GaN with high carrier concentration is obtained, the electric field concentration effect existing below a device electrode under reverse bias is relieved, and the breakdown voltage of the device is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a gallium nitride power device.
Background
The power semiconductor device can realize power conversion and circuit control of the power equipment through high-speed switching. Wherein the power diode mainly comprises a pn diode and a Schottky diode. Compared with a pn junction diode, the Schottky diode has the characteristics of low starting voltage and high switching speed, can exert the advantages of low power loss and high working frequency in a power electronic system, and has wide application prospects in the fields of power supplies, driving circuits and the like. In the past decades, Si materials have been widely used in the field of power electronic devices due to their advantages of low cost, simple process, easy integration, etc. However, Si materialThe narrow energy gap (1.12eV) and low critical breakdown field (0.3MV/cm) of the material make Si devices unable to meet the continuously increasing performance requirements in the market. As a representative third-generation semiconductor material, GaN has a wide forbidden band width (3.4eV), a high critical breakdown electric field (3.4MV/cm), and a high saturated electron drift rate (2.5X 10)7cm/s), high thermal conductivity and the like, and has great development space in the field of high-temperature, high-frequency and high-power electronic devices.
When reverse bias is applied to the schottky diode, an electric field concentration effect occurs below the electrode edge where the electric field is much higher than at the surface of the schottky junction, leading to premature breakdown of the device. It is therefore often desirable to employ termination structures to mitigate the effects of electric field concentration. One commonly used termination structure is a pn junction formed by ion implantation or etching of a p-type GaN epitaxial layer under an electrode, and a pn junction depletion region extends under a reverse bias, which can effectively alleviate an electric field concentration effect. However, there are still some difficulties in forming p-type GaN by ion implantation at present. In GaN materials, Mg is generally used as an acceptor impurity, but high-temperature annealing at 1300 ℃ or higher is required to activate Mg in GaN, which results in decomposition of n-type GaN, and the current activation efficiency and hole concentration after activation are still low. In addition, ion implantation of Mg also causes some lattice damage. However, the method for etching the p-type GaN epitaxial layer requires precise control of the etching depth, and certain etching damage also exists on the side wall and the bottom surface of the etched groove, which affects the performance of the device.
On the other hand, from the viewpoint of device structure, the GaN schottky diode mainly has a vertical type and a quasi-vertical type structure. For a vertical device, the device has the characteristics of uniform current distribution, small occupied area, good heat dissipation and the like, but generally a homogeneous substrate is required, and the current GaN self-supporting substrate is expensive and small in wafer size, so that the commercialization is not facilitated. The quasi-longitudinal device can adopt a Si substrate and a sapphire substrate which are low in price, but the quasi-longitudinal device also has the problems of uneven current distribution, need of deep side wall etching, low wafer utilization rate and the like.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a preparation method of a gallium nitride power device, which can effectively reduce the preparation cost of the device, effectively relieve the electric field concentration effect below a lower electrode under a reverse bias and improve the breakdown voltage of the device.
In order to solve the technical problems, the invention adopts the technical scheme that: a preparation method of a gallium nitride power device comprises the following steps:
s1, epitaxially growing a device drift region on a substrate through MOCVD;
s2, isolating devices through an ICP etching table;
s3, depositing a dielectric layer SiO on the drift region of the device through PECVD2As a mask, removing SiO at the position of the p-type GaN region2A mask layer;
s4, epitaxially growing a p-type GaN region and removing SiO2A mask layer;
s5, growing a dielectric layer on the device formed in the step S4, and removing the dielectric layer at the Schottky contact area of the device;
s6, bonding the device formed in the step S5 to a temporary substrate through a bonding layer;
s7, stripping the original substrate from the device formed in the step S6 by using a substrate stripping technology;
s8, evaporating Ti/Al/Ni/Au on the drift region of the device by adopting an electron beam evaporation method or a magnetron sputtering method to form an ohmic contact electrode as a diode cathode;
s9, electroplating metal Ni on the ohmic contact electrode to form a metal substrate;
s10, removing the bonding layer and the temporary substrate;
s11, adopting an electron beam evaporation method or a magnetron sputtering method to evaporate Ni/Au on the p-type GaN region and the drift region of the device to form a Schottky electrode, and adopting a stripping method to selectively leave the electrode to be used as a diode anode.
Further, the step S3 specifically includes:
s31, depositing SiO 0.1-10 mu m on the drift region of the device through PECVD2A mask layer;
s32, in the p-type GaN region to be grownSiO of the position of the domains2Opening a window on the mask layer through photoetching;
s33, removing SiO uncovered by the photoresist through buffered hydrofluoric acid2And (5) masking the layer.
The method for manufacturing a gallium nitride power device according to claim 2, wherein the step S5 specifically comprises:
s51, depositing a dielectric layer of 10 nm-500 nm on the device formed in the step S4;
s52, opening a window on the dielectric layer at the position where the Schottky contact is to be formed through photoetching;
and S53, removing the dielectric layer which is not covered by the photoresist through a buffered hydrofluoric acid solution.
Furthermore, the drift region of the device is an unintentional doped GaN epitaxial layer, a Si doped epitaxial layer or an As doped epitaxial layer with low dislocation density; the thickness of the drift region of the device is 1-50 μm, and the carrier concentration is 1 × 1014cm-3～5×1017cm-3。
Further, the p-type GaN region has a hole concentration of 1 × 1016cm-3～1×1019cm-3The thickness is 0.1-10 μm.
Further, the dielectric layer material is Al2O3、SiN、SiO2Any of them, the thickness is 10nm to 500 nm.
Furthermore, the metal substrate material is one of Cu and Ni, and the thickness is 40-100 μm.
Furthermore, the cathode of the diode is made of any one of Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy.
Further, the anode of the diode is made of one of metals of Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, TiN, Ta, TaN, ZrN, VN and NbN or a stacked structure thereof.
Further, the substrate in step S1 includes a sapphire substrate, a SiC substrate, or a Si substrate.
Compared with the prior art, the beneficial effects are: according to the preparation method of the gallium nitride power device, the longitudinal conduction of the device is realized through the substrate stripping technology, the dependence on the GaN self-supporting substrate can be effectively relieved in the middle and low voltage application field, and the manufacturing cost of the device is greatly reduced; the terminal structure is manufactured by adopting a selective area epitaxial p-type GaN method, so that lattice damage caused by ion injection or etching is avoided, p-type GaN with high carrier concentration is obtained, the electric field concentration effect existing below a device electrode under reverse bias is relieved, and the breakdown voltage of the device is improved.
Drawings
Fig. 1 to 7 are schematic views of a device process flow of embodiment 1 of the present invention, wherein fig. 7 is a schematic view of an overall structure of the device manufactured in embodiment 1.
Fig. 8 to 12 are process flow diagrams of the device of example 2 of the present invention, in which the overall structural diagram of the device prepared in example 2 is the same as that of example 1.
Reference numerals: 1. a substrate; 2. a device drift region; 3. a mask layer; 4. a p-type GaN region; 5. a dielectric layer; 6. a bonding layer; 7. a temporary substrate; 8. a diode cathode; 9. a metal substrate; 10. and an anode of the diode.
Detailed Description
The drawings are for illustration purposes only and are not to be construed as limiting the invention; for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the invention.
Example 1:
fig. 7 is a schematic view of the device structure of this embodiment, and the structure thereof sequentially includes, from bottom to top: a metal substrate 9 covering the cathode of the device; an ohmic electrode-diode cathode 8 covering the device drift region 2; n-type low carrier concentration region-device drift region 2; junction terminal-p-type GaN region 4; a dielectric layer 5 covering the p-type GaN region 4; the electrode forming a schottky contact with the drift region-the diode anode 10.
A preparation method of a gallium nitride power device comprises the following steps:
step 1.1 epitaxial Structure
A device drift region 2 of n-type conductivity is epitaxially grown on a substrate 1, and the epitaxial structure of the material after this step is completed is shown in fig. 1.
Step 1.2 device isolation
S21, coating photoresist on the drift region 2 of the n-type conductive device, and exposing a region to be etched after exposure and development;
s22, etching the area which is not covered by the photoresist through ICP;
and S23, removing the photoresist by using acetone.
Step 1.3 preparation of mask layer 3
S31, depositing SiO on the drift region 2 of the device2As a mask layer 3;
s32, in SiO2Coating photoresist on the mask layer 3, exposing and developing to expose the position of a p-type region needing epitaxial growth;
and S33, selectively etching the mask layer 3 which is not covered by the photoresist by using a buffer hydrofluoric acid solution, wherein the structure of the finished device is shown in figure 2.
Step 1.4 epitaxial growth of p-type GaN
S41, placing the device prepared in the step 1.3 into an MOCVD chamber to epitaxially grow p-type GaN to form a p-type GaN region 4;
s42, removing SiO by using buffer hydrofluoric acid solution2And a mask layer 3, wherein the structure of the finished device is shown in FIG. 3.
Step 1.5, growing a dielectric layer 5;
s51, placing the device prepared in the step 1.4 into a chamber to grow a medium layer 5;
s52, coating photoresist on the dielectric layer 5, exposing and developing to expose an area where the dielectric layer 5 needs to be removed;
s53, selectively etching the dielectric layer 5 which is not covered by the photoresist by using a buffer hydrofluoric acid solution;
s54, removing the photoresist by using acetone, wherein the finished structure is shown in FIG. 4.
Step 1.6 substrate 1 lift-off
S61, bonding the device prepared in the step 5 to a temporary substrate 7 through a bonding layer 6;
s62, stripping the substrate 1 from the device prepared in the step S1.5 by using a substrate stripping technology, wherein the structure of the finished device is shown in FIG. 5.
Step 1.7 Evaporation of cathode Metal
S71, evaporating Ti/Al/Ni/Au on the back surface of the device prepared in the step S1.6 to form ohmic contact to be used as a diode cathode 8;
and S72, electroplating metal Ni on the ohmic contact electrode to form a metal substrate 9, wherein the structure of the finished device is shown in figure 6.
Step 1.8 Evaporation of Anode Metal
S81, removing the bonding layer 6 and the temporary substrate 7;
s82, coating photoresist on the device prepared in the step 1.7, evaporating Ni/Au after exposure and development, forming Schottky contact with the drift region 2 and the p-type GaN region 4 of the device, and forming a diode anode 10 after stripping;
s83, the process flow of the embodiment 1 is completed, and the final device structure is shown in FIG. 7.
Example 2
The final device structure of this embodiment is the same as that of embodiment 1, except that in embodiment 1, the device needs to be transferred onto the temporary substrate 7, and after the original substrate 1 is peeled, the temporary substrate 7 is removed, but the temporary substrate 7 is not used in this embodiment. In this embodiment, after the growth of the drift region 2 of the n-type device is completed in embodiment 1, the following process flow is performed:
step 2.1 Evaporation of cathode Metal
S11, evaporating Ti/Al/Ni/Au to form ohmic contact on the front surface of the device after the growth of the drift region 2 of the n-type device is completed in the embodiment 1 to be used as a diode cathode 8;
s12, electroplating metal Ni on the ohmic contact electrode to form a metal substrate 9, wherein the structure of the finished device is shown in figure 8.
Step 2.2 substrate 1 lift-off
The substrate 1 is stripped from step 2.1 by a substrate 1 stripping technique and the finished device structure is shown in fig. 9.
Step 2.3 device isolation
S31, coating photoresist on the drift region 2 of the n-type conductive device, and exposing a region to be etched after exposure and development;
s32, etching the area which is not covered by the photoresist through ICP;
and S33, removing the photoresist by using acetone.
Step 2.4 preparation of mask layer 3
S41, depositing SiO on the drift region 22As a mask layer 3;
s42, in SiO2Coating photoresist on the mask layer 3, exposing and developing to expose a region needing to form p-type GaN;
s43, selectively etching the mask layer 3 which is not covered by the photoresist by using a buffer hydrofluoric acid solution, wherein the structure of the finished device is shown in FIG. 10;
step 2.6 epitaxial growth of p-type GaN
S61, placing the device prepared in the step 2.5 into an MOCVD chamber to epitaxially grow p-type GaN to form a p-type GaN region 4;
s62, removing SiO by using buffer hydrofluoric acid solution2And a mask layer 3, wherein the structure of the finished device is shown in fig. 11.
Step 2.7 growth of dielectric layer 5
S71, placing the device prepared in the step 2.6 into a chamber to grow a medium layer 5;
s72, coating photoresist on the dielectric layer 5, exposing and developing to expose an area where the dielectric layer 5 needs to be removed;
s73, selectively etching the dielectric layer 5 which is not covered by the photoresist by using a buffer hydrofluoric acid solution;
and S74, removing the photoresist by using acetone, wherein the finished structure is shown in FIG. 12.
Step 2.8 Evaporation of Anode Metal
S81, coating photoresist on the device prepared in the step 2.7, evaporating Ni/Au after exposure and development, forming Schottky contact with the drift region 2 and the p-type GaN region 4 of the device, and forming an anode of the diode after stripping;
s82, the process flow of the embodiment 2 is completed, and the final device structure is shown in FIG. 7.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A preparation method of a gallium nitride power device is characterized by comprising the following steps:
s1, epitaxially growing a device drift region (2) on a substrate (1) through MOCVD;
s2, isolating devices through an ICP etching table;
s3, depositing a dielectric layer (5) SiO on the device drift region (2) through PECVD2As a mask, SiO at the position of the p-type GaN region (4) is removed2A mask layer (3);
s4, epitaxially growing a p-type GaN region (4), and removing SiO2A mask layer (3);
s5, growing a dielectric layer (5) on the device formed in the step S4, and removing the dielectric layer (5) at the position of the Schottky contact region of the device;
s6, bonding the device formed in the step S5 to a temporary substrate (7) through a bonding layer (6);
s7, stripping the original substrate (1) from the device formed in the step S6 by using a substrate stripping technology;
s8, evaporating Ti/Al/Ni/Au on the drift region (2) of the device by adopting an electron beam evaporation method or a magnetron sputtering method to form an ohmic contact electrode as a diode cathode (8);
s9, electroplating metal Ni on the ohmic contact electrode to form a metal substrate (9);
s10, removing the bonding layer (6) and the temporary substrate (7);
s11, evaporating Ni/Au on the p-type GaN region (4) and the drift region of the device by adopting an electron beam evaporation method or a magnetron sputtering method to form a Schottky electrode, and selectively leaving the electrode by adopting a stripping method to be used as a diode anode (10).
2. The method for manufacturing a gallium nitride power device according to claim 1, wherein the step S3 specifically comprises:
s31, depositing SiO 0.1-10 mu m on the drift region (2) of the device through PECVD2A mask layer (3);
s32. SiO in the position where the p-type GaN region (4) is to be grown2Opening a window on the mask layer (3) by photoetching;
s33, removing SiO uncovered by the photoresist through buffered hydrofluoric acid2And (3) a mask layer.
3. The method for manufacturing a gallium nitride power device according to claim 2, wherein the step S5 specifically comprises:
s51, depositing a dielectric layer (5) with the thickness of 10 nm-500 nm on the device formed in the step S4;
s52, opening a window on the dielectric layer (5) at the position where the Schottky contact is to be formed through photoetching;
and S53, removing the dielectric layer (5) which is not covered by the photoresist through a buffered hydrofluoric acid solution.
4. The method for manufacturing a gallium nitride power device according to claim 3, wherein the device drift region (2) is an unintentionally doped GaN epitaxial layer, a Si doped epitaxial layer or an As doped epitaxial layer with low dislocation density; the thickness of the drift region (2) of the device is 1-50 μm, and the carrier concentration is 1 x 1014cm-3～5×1017cm-3。
5. Method for fabricating a gallium nitride power device according to claim 3, wherein the p-type GaN region (4)Hole concentration of 1X 1016cm-3～1×1019cm-3The thickness is 0.1-10 μm, and the thickness is 0.1-10 μm.
6. Method for manufacturing a GaN power device according to any of claims 1-5, characterized in that the material of the dielectric layer (5) is Al2O3、SiN、SiO2Any of them, the thickness is 10nm to 500 nm.
7. The method for manufacturing a gallium nitride power device according to claim 6, wherein the metal substrate (9) is made of one of Cu and Ni, and has a thickness of 40 μm to 100 μm.
8. The method for preparing the gallium nitride power device according to claim 6, wherein the material of the diode cathode (8) is any one of Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy, or Ti/Al/Ti/TiN alloy.
9. The method for manufacturing a GaN power device according to claim 6, wherein the material of the diode anode (10) is one of Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, TiN, Ta, TaN, ZrN, VN, NbN or a stacked structure thereof.
10. The method of manufacturing a gallium nitride power device according to claim 6, wherein the substrate (1) in step S1 comprises a sapphire substrate, a SiC substrate, or a Si substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110743594.5A CN113658859B (en) | 2021-06-30 | 2021-06-30 | Preparation method of gallium nitride power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110743594.5A CN113658859B (en) | 2021-06-30 | 2021-06-30 | Preparation method of gallium nitride power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113658859A true CN113658859A (en) | 2021-11-16 |
| CN113658859B CN113658859B (en) | 2023-09-12 |
Family
ID=78489830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110743594.5A Active CN113658859B (en) | 2021-06-30 | 2021-06-30 | Preparation method of gallium nitride power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113658859B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118198149A (en) * | 2024-05-20 | 2024-06-14 | 山东大学 | Gallium nitride Schottky diode based on energy band regulation junction terminal and preparation method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661985A (en) * | 2009-09-18 | 2010-03-03 | 厦门市三安光电科技有限公司 | Method for manufacturing gallium nitride-based light-emitting diode with vertical structure |
| CN102299226A (en) * | 2010-06-24 | 2011-12-28 | 上海蓝光科技有限公司 | LED (light emitting diode) with vertical structure and manufacturing method thereof |
| CN106611809A (en) * | 2017-01-11 | 2017-05-03 | 东莞市中镓半导体科技有限公司 | Preparing method for GaN growth composite substrate with isolation protection layer |
| US20190140046A1 (en) * | 2016-07-11 | 2019-05-09 | Xiamen Sanan Integrated Circuit Co., Ltd. | Silicon carbide power device employing heterojunction terminal and manufacturing method thereof |
| CN110085518A (en) * | 2019-05-06 | 2019-08-02 | 南京邮电大学 | A kind of preparation method for the transferable GaN film and its device that selective electrochemical method is removed |
| CN110931571A (en) * | 2019-12-18 | 2020-03-27 | 中山大学 | Vertical GaN-based groove junction barrier Schottky diode and manufacturing method thereof |
| CN211017091U (en) * | 2019-12-18 | 2020-07-14 | 中山大学 | Vertical GaN-based groove junction barrier Schottky diode |
-
2021
- 2021-06-30 CN CN202110743594.5A patent/CN113658859B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661985A (en) * | 2009-09-18 | 2010-03-03 | 厦门市三安光电科技有限公司 | Method for manufacturing gallium nitride-based light-emitting diode with vertical structure |
| CN102299226A (en) * | 2010-06-24 | 2011-12-28 | 上海蓝光科技有限公司 | LED (light emitting diode) with vertical structure and manufacturing method thereof |
| US20190140046A1 (en) * | 2016-07-11 | 2019-05-09 | Xiamen Sanan Integrated Circuit Co., Ltd. | Silicon carbide power device employing heterojunction terminal and manufacturing method thereof |
| CN106611809A (en) * | 2017-01-11 | 2017-05-03 | 东莞市中镓半导体科技有限公司 | Preparing method for GaN growth composite substrate with isolation protection layer |
| CN110085518A (en) * | 2019-05-06 | 2019-08-02 | 南京邮电大学 | A kind of preparation method for the transferable GaN film and its device that selective electrochemical method is removed |
| CN110931571A (en) * | 2019-12-18 | 2020-03-27 | 中山大学 | Vertical GaN-based groove junction barrier Schottky diode and manufacturing method thereof |
| CN211017091U (en) * | 2019-12-18 | 2020-07-14 | 中山大学 | Vertical GaN-based groove junction barrier Schottky diode |
Non-Patent Citations (1)
| Title |
|---|
| 周琦;陈万军;张波;: "硅基GaN功率半导体技术", 电力电子技术, no. 12 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118198149A (en) * | 2024-05-20 | 2024-06-14 | 山东大学 | Gallium nitride Schottky diode based on energy band regulation junction terminal and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113658859B (en) | 2023-09-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101478006B (en) | Terahertz GaN Gunn diode based on conducting type SiC substrate and manufacturing process thereof | |
| CN104465748B (en) | A kind of enhanced HEMT device of GaN base and preparation method thereof | |
| CN110379857B (en) | Switching device containing p-type gallium oxide thin layer and preparation method thereof | |
| CN113380623A (en) | Method for realizing enhanced HEMT (high Electron mobility transistor) through p-type passivation | |
| CN104851864A (en) | GaN schottky diode with hanging beam lead structure and manufacturing method thereof | |
| CN111384171B (en) | High-channel mobility vertical UMOSFET device and preparation method thereof | |
| CN112713190B (en) | Preparation method of gallium nitride HEMT device with vertical structure | |
| CN204596798U (en) | A kind of GaN base Schottky diode of vertical stratification | |
| CN113658859B (en) | Preparation method of gallium nitride power device | |
| CN108206220B (en) | Preparation method of diamond Schottky diode | |
| CN116666428A (en) | Gallium nitride Schottky diode and preparation method thereof | |
| CN117457710A (en) | Based on p-type Ga 2 O 3 Schottky diode and preparation method thereof | |
| CN204614773U (en) | With the GaN Schottky diode of unsettled beam leaded structure | |
| CN115394833A (en) | Device structure of complete vertical GaN power diode based on heteroepitaxial substrate and preparation method thereof | |
| WO2023103536A1 (en) | Enhanced gan hemt radio frequency device, and manufacturing method therefor | |
| CN115376919A (en) | Enhanced GaN power device and preparation method thereof | |
| CN114725022A (en) | Based on GaOxPreparation method of-GaN CMOS inverter | |
| CN110808292B (en) | GaN-based complete vertical Schottky varactor based on metal eave structure and preparation method thereof | |
| CN215527733U (en) | Longitudinal conduction type GaN power diode | |
| CN112838006B (en) | Gallium nitride PIN diode and preparation method thereof | |
| CN117219666B (en) | Gallium oxide heterogeneous thyristor with double trigger gate electrodes and preparation method thereof | |
| CN112820644B (en) | Gallium nitride PN diode with high blocking voltage and preparation method thereof | |
| CN111739946B (en) | Homotype heterostructure IMPATT diode and manufacturing method thereof | |
| CN110729351B (en) | High-power cathode and anode annular interdigital GaN quasi-vertical pn junction diode and preparation method thereof | |
| KR100847848B1 (en) | Hetero juction bipolar transistor and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |