CN111106175A - 半导体器件和形成半导体器件的方法 - Google Patents

半导体器件和形成半导体器件的方法 Download PDF

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CN111106175A
CN111106175A CN201911031314.7A CN201911031314A CN111106175A CN 111106175 A CN111106175 A CN 111106175A CN 201911031314 A CN201911031314 A CN 201911031314A CN 111106175 A CN111106175 A CN 111106175A
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source
drain
semiconductor fin
semiconductor device
forming
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万政典
李名镇
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明提供一种半导体器件，包括：衬底上的半导体鳍；沿着所述半导体鳍的侧壁和顶表面的栅极结构，其中所述栅极结构覆盖所述半导体鳍的第一部分；源极/漏极部件；以及与所述源极/漏极部件连接的源极/漏极接触部，其中所述源极/漏极接触部向下延伸到低于所述半导体鳍的第一部分的顶表面的位置。采用该技术方案，有助于电流流过源极部件和漏极部件之间的沟道区域。

Description

半导体器件和形成半导体器件的方法
技术领域
本发明涉及半导体器件及其形成方法，尤其涉及具有改善的源极/漏极接触部(contact)的非平面(non-planar)半导体器件及其形成方法。
背景技术
近年来，高级集成电路(IC)器件已变得具有越来越多功能，并且尺寸缩小了。尽管缩小尺寸的工艺通常会提高生产效率并降低相关成本，但它也增加了加工(processing)和制造IC器件的复杂性。
例如，已经引入了鳍场效应晶体管(Fin Field-Effect Transistor，FinFET)来替代平面晶体管。FinFET的结构和制造FinFET的方法正在开发中。在FinFET的传统结构中，外延(epitaxially)的向上生长且具有大体积(volume)的源极/漏极部件在沟道区域中施加应力(strain)。当减小FinFET的尺寸时，形成大体积源极/漏极部件的复杂性就会增加。用于外延的形成大体积源极/漏极部件的传统工艺需要几个沉积和蚀刻步骤，这是耗时且难以控制的。而且，当缩小半导体器件时，减小了常规的大体积源极/漏极部件对半导体器件的沟道电阻(channel resistance，Rch)的应力效应。因此，期望一种新颖的半导体器件结构及其形成方法。
发明内容
提供了半导体器件及其形成方法。半导体器件的示例性实施例包括：衬底上方的半导体鳍；以及沿着半导体鳍的侧壁和顶表面的栅极结构。栅极结构覆盖半导体鳍的第一部分。半导体器件还包括与栅极结构相邻或者邻近的源极/漏极部件(feature)。半导体器件还包括连接到源极/漏极部件的源极/漏极接触部。源极/漏极接触部向下延伸到低于半导体鳍的第一部分的顶表面的位置。
形成半导体器件的方法的示例性实施例包括在衬底上形成半导体鳍。沿着半导体鳍的第一部分的侧壁和顶表面形成栅极结构。栅极结构暴露半导体鳍的第二部分。在衬底上形成介电层，并且介电层覆盖半导体鳍的暴露的第二部分。移除一部分介电层以形成第一孔，其中第一孔暴露半导体鳍的第二部分。然后移除半导体鳍的第二部分的一部分以形成第二孔。第一孔连接第二孔。在第二孔中形成源极/漏极部件。源极/漏极部件限定了凹陷区域，该凹陷区域低于半导体鳍的第一部分的顶表面。在凹陷区域和第一孔中形成源极/漏极接触部。
在下面的实施例中，参照附图给出详细描述。
本发明实施例提供的半导体器件中源极/漏极接触部向下延伸到低于半导体鳍的第一部分的顶表面的位置，有助于电流流过源极/漏极接触部和源极/漏极部件。
附图说明
通过阅读以下参考附图的详细描述和实施例，可以更全面地理解本发明，其中：
图1是衬底上的半导体鳍的透视图；
图2A是根据一些实施例的半导体器件的中间阶段的透视图；
图2B，图3，图4，图5和图6是根据一些实施例的形成半导体器件的工艺的中间阶段的截面图。
图7，图8，图9和图10是根据一些实施例的形成半导体器件的工艺的中间阶段的截面图；
图11A是根据一些实施例的半导体器件的截面图；
图11B是根据一些实施例的半导体器件的截面图；
图12A是根据一些实施例的半导体器件的截面图；
图12B是根据一些实施例的半导体器件的截面图。
具体实施方式
以下描述是实施本发明的较佳构想模式。进行该描述是为了说明本发明的一般原理，而不应被认为是限制性的。本发明的范围由所附权利要求书确定。
在下文中，参考附图充分描述了本发明概念，在附图中示出了本发明概念的示例性实施例。根据以下示例性实施例，本发明概念的优点和特征以及实现这些优点和特征的方法将变得显而易见，所述示例性实施例将参考附图进行更详细地描述。然而，应当注意，本发明概念不限于以下示例性实施例，并且可以以各种形式实现。因此，提供示例性实施例仅是为了公开发明概念，并且使本领域技术人员知道发明概念的类别。而且，所示的附图仅是示意性的，并且是非限制性的。在附图中，出于说明的目的，一些元件的尺寸可能被放大并且未按比例绘制。在实际应用中，尺寸和相对尺寸不对应于实际尺寸。
本文所使用的术语仅出于描述特定实施例的目的，并不旨在限制本发明。如本文所使用的，单数术语“一”，和“该”也旨在包括复数形式，除非上下文另外明确指出。如本文所使用的，术语“和/或”包括一个或多个相关联的所列项目的任何和所有组合。应当理解，当一个元件被称为“连接”或“接触”到另一个元件时，它可以直接连接或接触到另一个元件，或者可以存在中间元件，该一个元件通过中间元件连接或接触到另一个元件。
类似地，应当理解，当诸如层，区域或衬底的元件被称为在另一元件“上”时，其可以直接在另一元件上，或者可以存在中间元件。相反，术语“直接”是指不存在中间元件。应该理解的是，当在本文中使用时，术语“包括”，“包含”，和/或“具有”规定了存在所述特征，整数，步骤，操作，元件和/或组件，但是不排除存在或增加一个或多个其他特征，整数，步骤，操作，元件，组件和/或其组合。
此外，为了便于描述，在本文中可以使用诸如“在...下方”，“在...下”，“在...上方”，“在...上”之类的空间相对术语，以便于描述图中所示的一个元件或特征相对于另一个元件或者特征的关系。除了在图中描述的方位之外，空间相对术语还意图涵盖设备/器件在使用或操作中的不同方位。应该理解的是，尽管这里可以使用术语第一，第二，第三等来描述各种元件，但是这些元件不应受到这些术语的限制。这些术语仅用于区分一个元件和另一个元件。因此，在不背离本发明教导的情况下，在一些实施例中的第一元件可以在其他实施例中被称为第二元件。本文中解释和说明的本发明概念的方面的示例性实施例包括它们的互补对等物。在整个说明书中，相同或相似的附图标记或参考标记表示相同或相似的元件。
图1是衬底上的半导体鳍的透视图。图2A是根据一些实施例的半导体器件的中间阶段的透视图。图2B，图3至图6是根据一些实施例的用于形成半导体器件的工艺的中间阶段的截面图。图2B是沿着图2A的结构的截面线B-B截取的截面图。图3至图6沿图2A中类似截面线B-B示出的。在一些实施例中，半导体器件是三维或非平面(non-planar)晶体管。
参照图1，提供衬底100，并且半导体鳍102形成在衬底100上。隔离层110形成在衬底100上并且设置为与半导体鳍102相邻。可选的，在一示例中，隔离层110具有上表面110a。在一些实施例中，多个半导体鳍从衬底100突出(protrude)。为了简化该图，这里仅示出了一个半导体鳍。而且，在一些实施例中，半导体鳍102的底表面102b可以被定义为半导体鳍102和衬底100之间的界面。图1中示出从底表面102b到顶表面102a测量的半导体鳍102的高度H。
在一些实施例中，衬底100是块状半导体衬底，例如半导体晶圆(wafer)。例如，衬底100包括硅或诸如锗的其他基本半导体材料。衬底100可以是未掺杂的或掺杂的(例如，p型，n型或其组合)。在一些实施例中，衬底100包括在介电层(dielectric layer)上外延生长的半导体层。外延生长的半导体层可以由硅锗，硅，锗，一种或多种其他合适的材料或它们的组合制成。在一些其他实施例中，衬底100包括多层结构。例如，衬底100包括形成在块状(bulk)硅层上的硅锗层。
在一些实施例中，半导体鳍102是用于形成FinFET的鳍，并且可以通过任何合适的方法来形成/图案化。例如，可以使用一种或多种光刻工艺来图案化鳍，包括双图案化或多图案化工艺。通常，双图案化(double-patterning)或多图案化(multi-patterning)工艺将光刻(photolithography)和自对准工艺相结合，从而允许创建具有例如间距(pitch)小于使用单个直接光刻工艺可获得的间距的图案。在一些实施例中，可以将半导体鳍102进一步图案化为纳米线(nanowire)或纳米片(nanosheet)，以用于全方位栅场效应晶体管(gate-all-around field-effect transistor，GAAFET)。
在一些实施例中，隔离层110暴露半导体鳍102的顶部。隔离层110也可以被称为隔离部件，其被用于限定和电隔离形成在衬底100内部和/或衬底100之上的各种器件元件。在一些实施例中，隔离层110包括浅沟槽隔离(shallow trench isolation，STI)部件，硅的局部氧化(local oxidation of silicon，LOCOS)部件，其他合适的隔离部件或其组合。
在一些实施例中，隔离层110具有多层结构。在一些实施例中，隔离层110由介电材料制成。介电材料可以包括氧化硅，氮化硅，氮氧化硅，掺杂氟化物的硅酸盐玻璃(fluoride-doped silicate glass，FSG)，低K介电材料，一种或多种其他合适的材料或其组合。
图2A是根据一些实施例的半导体器件的中间阶段的透视图。图2B是沿着图2A中结构的截面线B-B截取的截面图。在一些实施例中，执行在衬底100上形成伪栅极和间隔物，随后进行替换金属栅极(metal gate，RMG)工艺(未示出)，例如，将伪栅极替换成金属栅极。为了清楚地说明实施例，图2A和图2B示例性地示出了在替换金属栅极工艺之后形成的栅极结构120。栅极结构120可以被称为金属栅极结构。
在图2A中，一些栅极结构120形成在隔离层110上，并且层间介电层130填充栅极结构120之间的空间。在一些实施例中，每个栅极结构120沿着半导体鳍102的侧壁102s和顶表面102a形成。半导体鳍102可以在第一方向D1上延伸，并且每个栅极结构120可以在第二方向D2上延伸，如图2A所示。另外，在该示例性实施例中，栅极结构120覆盖半导体鳍102的第一部分P1，并且暴露半导体鳍102的第二部分P2。
在一些实施例中，每个栅极结构120包括栅介电层121和在栅介电层121上的栅电极GE。此外，在栅极结构120的侧壁上形成间隔物SP1以分隔栅极结构120和随后形成的源极/漏极部件。
在图2A和图2B中，栅介电层121围绕并覆盖半导体鳍102的第一部分P1。在一些实施例中，栅介电层121是高k栅介电层，其介电常数大于二氧化硅(silicon dioxide)的介电常数。栅介电层121可以由氧化铪(hafnium oxide)，氧化锆(zirconium oxide)，氧化铝(aluminum oxide)，二氧化铪-铝合金(hafnium dioxide-alumina alloy)，氧化铪硅(hafnium silicon oxide)，氮氧化铪硅(hafnium silicon oxynitride)，氧化铪钽(hafnium tantalum oxide)，氧化铪钛(hafnium titanium oxide)，氧化铪锆(hafniumzirconium oxide)，一种或多种其他合适的高K介电材料或其组合。可以使用化学气相沉积(chemical vapor deposition，CVD)工艺，原子层沉积(atomic layer deposition，ALD)工艺，物理气相沉积(physical vapor deposition，PVD)工艺，一种或多种其他适用工艺或其组合来沉积栅介电层121。
在一些实施例中，栅电极GE包括功函数层(work function layer)123和沉积在功函数层123上方的金属填充层125。如图2A和图2B所示，根据一些实施例，功函数层123沉积在栅介电层121上。功函数层123延伸到由栅介电层121限定的凹陷(recess)中。金属填充层125沉积在功函数层123上以填充该凹陷。
栅电极GE的功函数层123可用于为晶体管提供所需的功函数(work function)，以增强器件性能，该器件性能包括改善的阈值电压。在一些实施例中，用于形成NMOS器件的功函数层123包括氮化钛，钽，氮化钽，一种或多种其他合适的材料或其组合。而且，在一些其他实施例中，用于形成NMOS器件的功函数层123是含铝层(aluminum-containing layer)。例如，含铝层包括TiAlC，TiAlO，TiAlN，一种或多种其他合适的材料或其组合。在一些实施例中，用于形成PMOS器件的功函数层123可以包括金属，金属碳化物(carbide)，金属氮化物(nitride)，其他合适的材料或其组合。例如，用于形成PMOS器件的功函数层123包括氮化钽，氮化钨，钛，氮化钛，其他合适的材料或其组合。可以使用ALD工艺，CVD工艺，PVD工艺，电镀工艺(electroplating process)，化学镀工艺(electroless plating process)，一种或多种其他适用工艺或其组合来沉积功函数层123。
在一些实施例中，栅电极GE的金属填充层125围绕半导体鳍102。金属填充层125可以由钨，铝，铜，钴(cobalt)，一种或多种其他合适的材料或它们的组合制成，或者包括钨，铝，铜，钴，一种或多种其他合适的材料或它们的组合。可以使用ALD工艺，PVD工艺，CVD工艺，电镀工艺，化学镀工艺，一种或多种其他适用工艺或其组合来沉积金属填充层125。
在一些实施例中，如图2A和图2B所示，形成在衬底20上的层间介电层(interlayerdielectric layer)130填充相邻的栅极结构120之间的间隙并覆盖半导体鳍102的第二部分P2。根据本发明，应注意的是，在替换金属栅极工艺之后形成源极/漏极部件。因此，图2A与图2B中的层间介电层130覆盖半导体鳍102的第二部分P2，并且不覆盖尚未形成的任何源极/漏极部件。
如下描述用于制造图2A与图2B的结构构造的一个例子。在衬底10上形成伪栅堆叠(gate stack)层(未示出)之后，将介电材料沉积在衬底10上，并且可以通过诸如CVD，等离子体增强CVD(plasma-enhanced CVD，PECVD)或FCVD之类的任何合适方法来沉积。在一些实施例中，介电材料可以包括氮化硅，氧化硅，氮氧化硅等。在一些实施例中，介电材料可包括磷硅酸盐玻璃(phospho-silicate glass，PSG)，硼硅酸盐玻璃(boro-silicate glass，BSG)，掺硼磷硅酸盐玻璃(boron-doped phospho-silicate glass，BPSG)，未掺杂硅酸盐玻璃(undoped silicate glass，USG)等。然后，执行诸如CMP的平坦化工艺，以使介电材料的顶表面与伪栅堆叠的伪栅极(未示出)的顶表面齐平或与伪栅堆叠的掩模(未示出)的顶表面齐平。之后，在蚀刻步骤中移除伪栅极(和掩模，如果存在的话)，从而形成用于容纳栅极结构120的材料的凹陷(未示出)。在沉积栅极结构120的材料之后，执行诸如CMP的平坦化工艺以移除介电材料的顶表面上的栅极结构120的材料的多余部分。因此，如图2A与图2B所示的结构(包括层间介电层130和栅极结构120)被形成。因此，图2A与图2B中的层间介电层130暴露栅极结构120的顶表面，以及层间介电层130的顶表面130a与栅极结构120的顶表面齐平。而且，栅极结构120的剩余部分材料(例如，包括栅介电层121和栅电极GE)形成所得器件的替换栅极。
根据本发明的一些实施例，在通过适当的替换栅极工艺形成栅极结构120之后，执行形成用于形成源极/漏极部件和源极/漏极接触部的孔的步骤。
参照图3，移除层间介电层130的一部分以形成第一孔131和132。可以使用可接受的光刻和蚀刻技术来形成层间介电层130中的第一孔131和132。第一孔131和132形成在相邻的栅极结构120之间，并且沿着在栅极结构120的侧壁上相对的间隔物SP1限定出第一孔131和132。在一些实施例中，第一孔131和132在栅极结构120的相对侧上暴露半导体鳍102的第二部分P2。
之后，使半导体鳍102的暴露的第二部分P2凹陷以限定出用于形成源极/漏极部件并在后续工艺中接收源极/漏极接触部的下部的区域。
参照图4，半导体鳍102的第二部分P2被凹陷以形成第二孔141和142。第二孔141和142形成在栅极结构120的相对侧上并且在第一孔131和132下方。第二孔141和142可以通过沿着第一孔131和132蚀刻半导体鳍102的第二部分P2来形成，而无需进一步的掩膜工艺。在本发明的一些实施例中，用于形成第一孔131和132的蚀刻步骤以及用于形成第二孔141和142的蚀刻步骤在使用合适的蚀刻剂(etchant)的相同蚀刻室(chamber)中原位(in-situ)进行，例如，在同一次进蚀刻室，一起完成了第一孔131和132和第二孔141和142。第一凹部141和第二凹部142越深，在后续工艺中形成的源极/漏极接触部的底表面越低。
在一些实施例中，移除半导体鳍102的第二部分P2的至少一部分，以形成第二孔141和142。图4描绘了第二孔141和142的侧壁与第一孔131和132的侧壁基本对准，但是本发明不限于此。在一些实施例中，第二孔141和142可以通过各向异性(anisotropic)蚀刻或各向同性(isotropic)蚀刻形成以扩大第二孔141和142的尺寸。而且，第二孔141的底表面141b和第二孔142的底表面142b低于半导体鳍102的第一部分P1的顶表面102a。在一些实施例中，底表面141b和142b达到半导体鳍102的底表面102b。然而，本发明不限于此。第二孔141和142的底表面141b和142b可以位于半导体鳍102的底表面102b之上或之下。
参照图5，源极/漏极部件151和152分别形成在第二孔141和142中。源极/漏极部件151和152也可以分别称为半导体器件的源极区和漏极区。源极/漏极部件151和152可以通过外延生长，注入(implantation)或任何合适的方法形成。在一些实施例中，源极/漏极部件151和152是掺杂区。例如，源极/漏极部件151和152是具有杂质(impurity)的重掺杂区域。源极/漏极部件151和152可以具有n型和/或p型杂质，该n型和/或p型杂质的浓度大约在1019cm-3到1021cm-3之间。其中，源极部件和漏极部件的杂质的浓度基本相同。在一些实施例中，源极/漏极部件151和152可以包括用于在应用中形成所需导电类型的半导体器件的任何可接受的材料。例如，NMOS器件(例如，n型FinFET)的源极/漏极部件151和152可以包括SiC，SiCP，SiP等。PMOS器件(例如，p型FinFET)的源极/漏极部件151和152可以包括SiGe，SiGeB，Ge，GeSn等。
此外，随着栅极结构120的间距(pitch)的减小，常规的大体积源极/漏极部件施加在沟道区上的应力的影响显著减小。因此，接触电阻成为减小半导体器件的电阻的最重要的因素之一。与外延的向上生长的常规的大体积源极/漏极部件不同，一些实施例的源极/漏极部件151和152是薄层，分别形成在半导体鳍102的顶表面102a下方的第二孔141和142内。尽管被配置为薄层的实施例的源极/漏极部件不能在栅极结构120下方的沟道区域中施加应力，但是电流将更容易且更快地流过源极/漏极接触部和薄的源极/漏极151和152部件。因此，减小了接触电阻并且提高了电气性能。
在一些实施例中，源极/漏极部件151/152的厚度T在大约1nm至大约10nm的范围内。在一些实施例中，源极/漏极部件151/152的厚度T在大约2nm至大约5nm的范围内。源极/漏极部件151的厚度可以基本上等于源极/漏极部件152的厚度，例如，源极部件151的厚度等于漏极部件152的厚度，或者漏极部件151的厚度等于源极部件152的厚度。
此外，根据一些实施例，源极/漏极部件151和152中的每个具有基本相同的厚度。在一些实施例中，源极/漏极部件151和152中的每一个具有基本相同的厚度，例如图5中所示的基本相同厚度T。在此使用的术语“基本相同”是指源极/漏极部件151/152的厚度变化在厚度值的+/-10％以内。源极/漏极部件151和152的基本相同厚度提高了流过源极/漏极部件151和152的电流的速度。
在图5中，源极/漏极部件151限定出比半导体鳍102的第一部分P1的顶表面102a低的凹陷区域145。类似地，源极/漏极部件152限定出比半导体鳍102的第一部分P1的顶表面102a低的凹陷区域146。在一些实施例中，源极/漏极部件151和152中的每个具有凹形的横截面形状。例如，如图5所示，源极/漏极部件151可以被配置作为第二孔141中的第一衬里(liner)，而源极/漏极部件152可以被配置作为第二孔142中的第二衬里。因此，在一些实施例中，源极/漏极部件151和152可具有U形横截面。
在一些实施例中，源极/漏极部件151的顶表面包括最上表面151a和连接到最上表面151a的凹入的上表面151c，如图5所示。源极/漏极部件151的最上表面151a可以与半导体鳍102的第一部分P1的顶表面102a齐平。类似地，源极/漏极部件152的顶表面包括最上表面152a和连接到最上表面152a的凹入的上表面152c。源极/漏极部件152的最上表面152a可以与半导体鳍102的第一部分P1的顶表面102a齐平。
参照图6，在将源极/漏极部件151和152形成在第二孔141和142内之后，在凹陷区域145和146以及第一孔131和132中分别形成源极/漏极接触部161和162，以物理地和电性连接源极/漏极部件151和152。延伸到半导体鳍102的顶表面下方的位置的源极/漏极接触部161/162有助于电流流过源极/漏极部件151和152之间的沟道区域。
参照图6，根据一些实施例，导电材料沉积在凹陷区域145、146和第一孔131，132中，以便形成源极/漏极接触部161和162。根据实施例，位于栅极结构120的相对侧上的源极/漏极接触部161/162向下延伸至比半导体鳍102的第一部分P1的顶表面102a低的位置。因此，源极/漏极接触部161/162的最下表面161b/162b低于半导体鳍102的第一部分P1的顶表面102a。如图6所示，源极/漏极接触部161/162的低于半导体鳍102的第一部分的顶表面的部分被源极/漏极部件151/152围绕。
在一些其他实施例中，源极/漏极接触部161/162包括在凹陷区域145/146和第一孔131/132中形成的衬里和导电材料。衬里，例如扩散阻挡层(diffusion barrier layer)，可以包括钽，氮化钽，钛，氮化钛等。导电材料可以是钨，铜，铜合金，钴，铝，镍等。执行诸如CMP之类的平坦化工艺以移除层间介电层130的顶表面上的多余材料。在凹陷区域145/146和第一孔131/132中，剩余的导电材料和衬里(如果存在)形成源极/漏极接触部161/162。可以执行退火(anneal)工艺以在源极/漏极部件151/152和源极/漏极接触部161/162之间的界面处形成硅化物(silicide)。
根据实施例，源极/漏极接触部161/162的最低底部(例如最下表面161b/162b)靠近半导体鳍102的底表面102b，这有助于电流流过源极/漏极部件151和152之间的沟道区域。在一些实施例中，源极/漏极接触部161/162的最低底部(例如最下表面161b/162b)与半导体鳍102的底表面102b之间的距离d1等于或小于10nm。
根据一些实施例，源极/漏极接触部161/162包括分别低于和高于半导体鳍102的第一部分Pl的顶表面102a的两个部分。如图6所示，源极/漏极接触部161/162包括在凹陷区域145/146中的一部分和在凹陷区域145/146上方的另一部分。源极/漏极接触部161/162的两个部分在物理上和电气上彼此连接。
在图6中，源极/漏极接触部161/162包括在凹陷区域145/146中的下部161-L/162-L和在第一孔131/132中的上部161-U/162-U。凹陷区域145/146上方的上部161-U/162-U位于下部161-L/162-L之上并与其电连接。在一些实施例中，源极/漏极部件151/152围绕下部161-L/162-L。例如，源极/漏极部件151/152环绕(wrap around)源极/漏极接触部161/162的下部161-L/162-L。如图6所示，下部161-L/162-L直接形成在源极/漏极部件151/152的凹形上表面151c/152c上。在一些实施例中，源极/漏极接触部162和161以相同工艺同时形成。
源极/漏极接触部161/162的下部161-L/162-L和上部161-U/162-U可以包括相同或不同的导电材料。在一些实施例中，下部161-L/162-L和上部161-U/162-U包括相同的导电材料。另外，形成源极/漏极接触部161/162的下部161-L/162-L和上部161-U/162-U的工艺不受特别限制。例如，下部161-L/162-L和上部161-U/162-U可以通过一个金属填充步骤或不同的金属填充步骤形成。
另外，在该示例性实施例中，源极/漏极接触部的下部的顶表面小于源极/漏极接触部的上部的底表面。例如，如图6所示，源极/漏极接触部161的下部161-L的宽度W1L小于源极/漏极接触部161的上部161-U的宽度W1U。如图6所示，源极/漏极接触部162的下部162-L的宽度W2L小于源极/漏极接触部162的上部162-U的宽度W2U。
根据一些实施例的半导体器件具有多个优点。对于先进的半导体技术，制造具有较小鳍间距和较高鳍高度的半导体器件以改善器件的性能和缩小面积。用于外延的形成大体积源极/漏极部件的常规工艺包括沉积和蚀刻的多个步骤，这是耗时且难以控制的。根据本发明的实施例，在第二孔141和142中将源极/漏极部件151和152形成为薄层是简单且容易的。此外，电流更容易且更快地穿过源极/漏极部件的薄层，从而降低了接触电阻。另外，源极/漏极部件151/152围绕并完全覆盖了源极/漏极接触部161/162的下部，从而增大了源极/漏极接触部161/162和源极/漏极部件151/152之间的接触面积，减小了接触电阻。此外，向下延伸至半导体鳍102的顶表面下方的位置的源极/漏极接触部161和162有助于电流流过源极/漏极部件151和152之间的沟道区域。根据本实施例，与常规的在鳍的顶表面上的大体积源极/漏极部件相比，本实施例的结构配置导致电流在源极/漏极接触部161的最低底部(例如最下表面161b)和源极/漏极接触部162的最低底部(例如最下表面162b)之间流动。即，电流趋于流过半导体鳍102的底部。因此，根据一些实施例的半导体器件的源极/漏极部件和源极/漏极接触部的配置不仅显著的降低了器件的接触电阻(resistance)，而且还增加了半导体鳍的底部使用量。根据实施例，可以改善半导体器件的电气性能，特别是栅极长度小的半导体器件(例如7nm，5nm或3nm栅极长度的晶体管)。
尽管图6描绘了根据一些实施例的半导体器件的截面图，本发明不限于此。源极/漏极接触部的构造可以根据用于形成源极/漏极接触部的方法而稍微改变或变化。
图7至图10是根据一些实施例的用于形成半导体器件的工艺的中间阶段的截面图。该实施例类似于图3-图6的先前实施例，除了在该实施例中，在源极/漏极接触部的上部和栅极结构120的侧壁上的间隔物SP1之间设置了附加的介电间隔物171。因此，在栅极结构120的相对侧的源极/漏极接触部161'和162'的上部彼此远离，以防止相邻的源极/漏极接触部161′和162′之间的不希望的电气干扰。本实施例适用于栅极长度小的半导体器件，例如7nm，5nm或3nm栅极长度的晶体管。关于该实施例的与先前描述的实施例相似的细节在此将不再赘述。
图7是与图5中等效的中间处理阶段，在此不再赘述。
在图8中，导电材料沉积在凹陷区域145和146中以形成源极/漏极接触部的下部161-L和162-L。
在图9中，附加的介电间隔物171和172形成在间隔物SP1的侧壁上。在一些实施例中，附加的介电层顺应地(conformably)沉积在栅极结构120上并沿着第一孔131和132的侧壁。在一些实施例中，介电层包括低k介电材料，例如SiCN，SiOCN，SiOC等等。可以通过ALD，CVD等或其组合来沉积介电材料层。然后，通过回蚀(etch-back)工艺移除栅极结构120的顶表面上的介电层的多余材料。因此，介电间隔物171和172分别形成在上部161-U和162-U上。如图9所示，在介电隔离物171和172之间限定有开口1701和1702。开口1701和1702分别暴露出下部161-L和162-L的顶表面的一部分。而且，剩余的介电间隔物171和172分别覆盖下部161-L和162-L的顶表面的其他部分。
可替代地，开口1701和1702可以通过其他合适的工艺形成。例如，对于具有小的栅极长度(例如，小于5nm或3nm的晶体管的栅极长度)的半导体器件，沉积在栅极结构120上的介电层可以填充第一孔131和132。执行平坦化(planarization)工艺(诸如CMP工艺)以移除栅极结构120的顶表面上的介电层的多余部分。然后，使用可接受的光刻和蚀刻技术，部分地移除第一孔131/132中的介电材料以形成开口1701/1702。第一孔131/132中剩余的介电材料形成介电间隔物171/172。
在图10中，在开口1701和1702中形成源极/漏极接触部的上部161-U'和162-U'。例如，导电材料沉积在介电间隔物171和172上并填充开口1701和1702。然后，执行诸如CMP的平坦化工艺以移除在介电间隔物171和172的顶表面上的导电材料的多余部分。将上部161-U'和下部161-L统称为作为源极/漏极接触部161'。上部162-U’和下部162-L被统称为源极/漏极接触部162’。注意，图9中的源极/漏极接触部161’/162’的结构和材料与前述实施例的源极/漏极接触部161/162的结构和材料相似，在此不再赘述。
此外，在该示例性实施例中，源极/漏极接触部的下部的顶表面的面积大于源极/漏极接触部的上部的底表面的面积。例如，如图10所示，源极/漏极接触部161′的上部161-U′的宽度W1U′小于源极/漏极接触部161′的下部161-L的宽度W1L。如图10所示，源极/漏极接触部162'的上部162-U'的宽度W2U'小于源极/漏极接触部162'的下部162-L的宽度W2L。因此，源极/漏极接触部161'和162'的上部161-U'和162-U'被栅极结构120，隔离物SP1和介电隔离物171和172分开，从而减少了在源极/漏极接触部161'和162'的上部161-U'和162-U'之间不希望的干扰。在该示例性实施例中，如图10所示的结构提供了一些优点，例如降低了接触电阻，简化了制造步骤以及增加了半导体鳍(例如鳍)的底部使用量，这与先前描述的实施例相似。它还可以防止相邻的源极/漏极接触部之间的不希望的电气干扰。
此外，可以对本发明的实施例进行许多变化和/或修改。在一些实施例中，衬底100上的半导体鳍102包括用于GAAFET的纳米片或纳米线。
根据本发明的一些实施例，半导体器件的半导体鳍可以包括纳米片。图11A是根据一些实施例的半导体器件的截面图。图11A沿图2A中类似的截面线B-B示出。图11B是根据一些实施例的半导体器件的截面图。沿着在第二方向D2上穿过图2A的栅极结构120的类似截面线示出了图11B。图11A/图11B的半导体器件和图6的半导体器件之间的区别是图11A/图11B的半导体鳍103包含纳米片。需要注意的是，关于该实施例的其他部件的细节与先前描述的实施例的那些相似，在此将不再赘述。
在图11A和图11B中，半导体鳍103沿着第一方向D1延伸，并且每个栅极结构120沿着第二方向D2延伸。在一些实施例中，半导体鳍103包括水平堆叠的纳米片S1，S2，S3和S4。纳米片S1，S2，S3和S4在第三方向D3上彼此间隔开。而且，栅极结构120从纳米片的所有侧面围绕半导体鳍103的纳米片S1，S2，S3和S4，这改善了导通-断开行为并降低了半导体器件的操作电压。在一些实施例中，配置为薄层的源极/漏极部件151和152与纳米片S1，S2，S3和S4直接接触。源极/漏极接触部161/162的下部161-L/162-L被形成为薄层的源极/漏极部件151/152包围。
在一些实施例中，如图11A和图11B所示的结构提供了类似于先前描述的实施例的一些优点。例如，向下延伸至半导体鳍103的顶表面下方的位置的源极/漏极接触部161和162有助于电流流过源极/漏极部件151和152之间的沟道区域。而且，使电流较快的和较容易的地流过源极/漏极接触部161和162以及源极/漏极部件151和152的薄层，从而减小了接触电阻。
另外，半导体器件的半导体鳍可以包括纳米线。图12A是根据一些实施例的半导体器件的截面图。图12A是沿图2中类似的截面线B-B示出的。图12B是根据一些实施例的半导体器件的截面图。在第二方向D2上沿着穿过图2A的栅极结构120的类似截面线示出了图12B。图12A/12B的半导体器件和图6的半导体器件之间的差异是图12A/12B的半导体鳍104包含纳米线。与该实施例有关的其他部件的细节与先前描述的实施例的那些组件的细节相似，在此不再赘述。
在图12A和图12B中，半导体鳍104沿着第一方向D1延伸，并且每个栅极结构120沿着第二方向D2延伸。在一些实施例中，半导体鳍104包括纳米线n1，n2，n3和n4。纳米线n1，n2，n3和n4垂直地堆叠并且在第三方向D3上彼此间隔开。而且，栅极结构120从纳米线的所有侧面围绕半导体鳍103的纳米线n1，n2，n3和n4，这改善了导通-断开行为并降低了半导体器件的操作电压。在一些实施例中，配置为薄层的源极/漏极部件151和152与纳米线n1，n2，n3和n4直接接触。源极/漏极接触部161/162的下部161-L/162-L被形成为薄层的源极/漏极部件151/152围绕。
在一些实施例中，如图12A和图12B所示的结构提供了类似于先前描述的实施例的一些优点。例如，向下延伸至半导体鳍104的顶表面下方的位置的源极/漏极接触部161和162有助于电流流过源极/漏极部件151和152之间的沟道区域。而且，使电流较快的和较容易的地流过源极/漏极接触部161和162以及源极/漏极部件151和152的薄层，从而减小了接触电阻。
应当注意，提供实施例的结构的细节用于示例，并且该实施例描述的细节不旨在限制本发明。应该注意的是，并未示出本发明的所有实施例。可以在不脱离本发明的精神的前提下进行修改和变型以满足实际应用的要求。因此，可能存在未具体示出的本发明的其他实施例。此外，附图被简化以清楚地示出实施例，图中的尺寸和比例可能与实际产品不成正比。因此，说明书和附图应被认为是说明性的而不是限制性的。
尽管已经通过示例的方式并且根据优选实施例描述了本发明，但是应当理解，本发明不限于所公开的实施例。相反，其意图在于涵盖各种修改和类似的布置(对于本领域技术人员而言将是显而易见的)。因此，所附权利要求的范围应被赋予最宽泛的解释，以涵盖所有这样的修改和类似的布置。

Claims (21)

1.一种半导体器件，其特征在于，包括：
衬底上的半导体鳍；
沿着所述半导体鳍的侧壁和顶表面的栅极结构，其中所述栅极结构覆盖所述半导体鳍的第一部分；
源极/漏极部件；以及
与所述源极/漏极部件连接的源极/漏极接触部，其中所述源极/漏极接触部向下延伸到低于所述半导体鳍的第一部分的顶表面的位置。
2.根据权利要求1所述的半导体器件，其特征在于，所述源极/漏极接触部的低于所述半导体鳍的所述第一部分的顶表面的部分被布置在所述源极/漏极部件内。
3.根据权利要求1所述的半导体器件，其特征在于，所述源极/漏极部件具有凹形的横截面形状。
4.根据权利要求1所述的半导体器件，其特征在于，所述源极/漏极部件的最上表面与所述半导体鳍的第一部分的顶表面齐平。
5.根据权利要求1所述的半导体器件，其特征在于，所述源极/漏极部件的厚度在1nm到10nm的范围内，所述源极/漏极部件与所述栅极结构相邻。
6.根据权利要求1所述的半导体器件，其特征在于，所述源极/漏极部件是具有掺杂浓度在1019cm-3和1021cm-3之间的掺杂区域。
7.根据权利要求1所述的半导体器件，其中，在所述源极/漏极接触部的最低底部与所述半导体鳍的底表面之间的距离等于或小于10nm。
8.根据权利要求1所述的半导体器件，其中，所述源极/漏极接触部包括：下部，直接位于所述源极/漏极部件的凹形上表面上；和上部，设置在所述下部之上并电连接到所述下部。
9.根据权利要求8所述的半导体器件，其中，所述下部的宽度小于所述上部的宽度；或者，所述下部的宽度大于所述上部的宽度。
10.根据权利要求1所述的半导体器件，所述半导体鳍包括纳米线或纳米片。
11.一种形成半导体器件的方法，其特征在于，包括：
在衬底上形成半导体鳍；
沿着所述半导体鳍的第一部分的侧壁和顶表面形成栅极结构，其中，所述栅极结构暴露所述半导体鳍的第二部分；
在所述衬底上形成介电层，覆盖所述半导体鳍的所述暴露的第二部分；
移除所述介电层的一部分以形成第一孔，其中所述第一孔暴露出所述半导体鳍的第二部分；
移除所述半导体鳍的第二部分的一部分以在所述第一孔的下方形成第二孔；
在所述第二孔中形成源极/漏极部件，其中，所述源极/漏极部件限定出凹陷区域，所述凹陷区域低于所述半导体鳍的所述第一部分的所述顶表面；以及
在所述凹陷区域和所述第一孔中形成源极/漏极接触部。
12.根据权利要求11所述的方法，其特征在于，所述源极/漏极接触部的底表面低于所述半导体鳍的第一部分的顶表面。
13.根据权利要求11所述的方法，其特征在于，形成源极/漏极部件包括：形成所述源极/漏极部件为具有凹形横截面形状。
14.根据权利要求11所述的方法，其特征在于，所述源极/漏极部件是通过注入或外延的生长形成的。
15.根据权利要求11所述的方法，其特征在于，所述源极/漏极部件被形成具有在1nm到10nm的范围内的厚度。
16.根据权利要求11所述的方法，其特征在于，所述源极/漏极部件是具有掺杂浓度在1019cm-3和1021cm-3之间的掺杂区域。
17.根据权利要求11所述的方法，其特征在于，在形成所述源极/漏极接触部之后，所述源极/漏极接触部的底表面与所述半导体鳍的底表面之间的距离等于或小于10nm。
18.根据权利要求11所述的方法，其特征在于，形成所述源极/漏极部件包括：
将第一导电材料填充到所述凹陷区域中以形成所述源极/漏极接触部的下部；以及
将第二导电材料填充到所述第一孔中以形成所述源极/漏极接触部的上部，
其中，所述上部邻接所述下部。
19.根据权利要求18所述的方法，其特征在于，还包括：在形成所述上部之前，在所述源极/漏极接触部的下部上形成介电部分，其中，所述上部和所述栅极结构被所述介电部分分隔开。
20.根据权利要求18所述的方法，其特征在于，所述第二导电材料与所述第一导电材料相同。
21.根据权利要求11所述的方法，其特征在于，所述栅极结构是金属栅极结构，以及所述源极/漏极部件是在形成所述金属栅极结构之后形成的。
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