CN111081761A - 具有抗辐射加固结构的低功耗晶体管器件及其制备方法 - Google Patents
具有抗辐射加固结构的低功耗晶体管器件及其制备方法 Download PDFInfo
- Publication number
- CN111081761A CN111081761A CN201911294299.5A CN201911294299A CN111081761A CN 111081761 A CN111081761 A CN 111081761A CN 201911294299 A CN201911294299 A CN 201911294299A CN 111081761 A CN111081761 A CN 111081761A
- Authority
- CN
- China
- Prior art keywords
- layer
- oxide layer
- plate metal
- bulk silicon
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003471 anti-radiation Effects 0.000 title claims abstract description 9
- 230000003014 reinforcing effect Effects 0.000 title claims description 10
- 238000002360 preparation method Methods 0.000 title description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 238000005468 ion implantation Methods 0.000 claims abstract description 19
- 239000002245 particle Substances 0.000 claims abstract description 9
- 230000005855 radiation Effects 0.000 claims description 20
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000005510 radiation hardening Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 101
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 230000000694 effects Effects 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 8
- 229910052681 coesite Inorganic materials 0.000 description 7
- 229910052906 cristobalite Inorganic materials 0.000 description 7
- 229910052682 stishovite Inorganic materials 0.000 description 7
- 229910052905 tridymite Inorganic materials 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910000070 arsenic hydride Inorganic materials 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000005621 ferroelectricity Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 229910018516 Al—O Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005865 ionizing radiation Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
一种具有抗辐射加固结构的低功耗晶体管器件，其特征在于，包括衬底，位于衬底之上的埋氧层，位于所述埋氧层之上的体硅层，位于所述体硅层之中、两侧的源区和漏区，位于体硅层之上的栅氧化层，位于所述栅氧化层之上的栅极叠层结构，所述栅极叠层结构自下而上依次为下极板金属层/铁电层/上极板金属层，或者自下而上依次为铁电层/上极板金属层。本发明晶体管器件通过在栅氧化层上制作栅极叠层结构，实现沟道电势大于外部栅极电压，突破热力学限制下的60mV/dec的亚阈值摆幅，降低工作电压从而降低器件的功耗，同时通过多次分步离子注入，获得与体硅层具有相同厚度的源漏结深，使源漏结与底部的埋氧层接触，提高了器件的抗单粒子辐照能力。
Description
技术领域
本发明涉及电子器件技术，属于空间环境效应、核科学与低功耗电路应用技术领域，更具体地，涉及一种具有抗辐射加固结构的低功耗晶体管器件及其制备方法。
背景技术
空间带电辐射粒子主要包括重离子、电子、质子及X射线等。这些带电粒子与晶体管器件发生相互作用，产生电离辐射效应、单粒子效应和位移辐射效应等。传统的对于器件的抗辐照加固方式通常是采用抗辐照涂层或者采用SOI技术，其中，SOI分为全耗尽型SOI和部分耗尽型SOI(PDSOI)，对于部分耗尽型SOI，其存在浮体效应，从而导致寄生二极管放大效应，增加敏感存储节点收集辐射电荷的能力。采用Body Ties结构可以减小寄生二极管效应，但会增加芯片面积。对于全耗尽型SOI，其可以减小敏感存储节点收集辐射电荷的能力，但其对于顶层硅层厚度有较高的要求，工艺上实现难度成本大。
同时，随着集成电路集成度的提高，功耗以及抗辐射性能成为限制其发展的主要问题，因此急需开发具有低功耗的抗辐射晶体管器件。
发明内容
本发明的目的在于，针对背景技术存在的缺陷，提出一种具有抗辐射加固结构的低功耗晶体管器件及其制备方法。
为实现上述目的，本发明采用的技术方案如下：
一种具有抗辐射加固结构的低功耗晶体管器件，包括衬底101，位于衬底101之上的埋氧层102，位于所述埋氧层102之上的体硅层103，位于所述体硅层103之中、两侧的源区108a和漏区108b，位于体硅层103之上的栅氧化层104，位于所述栅氧化层104之上的栅极叠层结构，所述栅极叠层结构自下而上依次为下极板金属层109/铁电层110/上极板金属层111，或者自下而上依次为铁电层110/上极板金属层111；其中，所述下极板金属层109的材料为TiN，厚度为2～5nm；所述铁电层110的材料为掺杂HfO2，厚度为10～30nm；所述上极板金属层111的材料为TiN，厚度为2～5nm。
进一步地，所述掺杂HfO2可以为掺杂Si的HfO2，具体为Hf0.5Si0.5O2，其中Hf:Si＝1:1，在该组分下，掺杂HfO2具有良好的铁电性；所述掺杂HfO2还可以为掺杂Zr的HfO2，具体为Hf0.7Zr0.3O2，其中Hf:Zr＝7:3，在该组分下，掺杂HfO2具有良好的铁电性。
进一步地，所述铁电层厚度和栅氧层厚度之比小于4。
优选地，所述铁电层厚度和栅氧层厚度之比等于2。
其中，所述衬底101为Si；埋氧层102为SiO2；体硅层103为Si；栅氧层104为低K介质SiO2、抗辐照的SiO2/Al2O3或者高K栅介质HfO2，厚度为1～10nm。
进一步地，所述源区108a和漏区108b是通过对体硅层103进行多次离子注入形成的，所述源区108a和漏区108b的厚度与体硅层103的厚度相同，即与埋氧层102接触。
进一步地，所述具有抗辐射加固结构的低功耗晶体管器件采用SOI衬底，通过对体硅层103进行多次离子注入形成晶体管深结源区108a和漏区108b，使源区108a、漏区108b均与埋氧层102接触。其中，体硅层103的厚度为50～200nm，虽然不是超薄的硅层(5～10nm)，但是通过本发明中的源漏区多次离子注入，形成和SOI衬底的埋氧层102相接触的深结源区108a和漏区108b，使得其可等效全耗尽SOI，减小了浮体效应，抑制寄生二极管放大效应，进一步减小敏感存储节点收集辐射电荷的能力。
一种具有抗辐射加固结构的低功耗晶体管器件的制备方法，其特征在于，具体包括以下步骤：
步骤1、准备SOI衬底，SOI衬底包括衬底101、埋氧层102以及体硅层103；
步骤2、清洗衬底，在衬底上生长栅氧层104；
步骤3、采用光刻刻蚀工艺，将源区和漏区位置处的栅氧层刻蚀掉，露出体硅层；
步骤4、进行源漏区的第一次浅结离子注入，形成浅结源区105a和浅结漏区105b；
步骤5、退火修复离子损伤；
步骤6、形成侧墙106a和106b，以侧墙106a、106b和光刻胶PR1为掩模版进行第二次离子注入；
步骤7、退火修复离子损伤；
步骤8、在步骤7的侧墙基础上再次形成侧墙，多次重复以上“形成侧墙-离子注入”步骤，直到形成与埋氧层102接触的深结源区108a和深结漏区108b，去除光刻胶PR1；
步骤9、在栅氧化层104上依次淀积下极板金属层109/铁电层110/上极板金属层111，或者依次淀积铁电层110/上极板金属层111；
步骤10、利用光刻胶进行构图，进行刻蚀，刻蚀停止在SOI衬底表面，即可得到所述具有抗辐射加固结构的低功耗晶体管器件。
与现有技术相比，本发明的有益效果为：
1、本发明提供的一种具有抗辐射加固结构的低功耗晶体管器件，通过对SOI衬底的体硅层进行多次离子注入，形成和SOI衬底的埋氧层102相接触的深结源区108a和漏区108b，使得其可等效全耗尽SOI，减小了浮体效应，抑制寄生二极管放大效应，进一步减小敏感存储节点收集辐射电荷的能力。
2、本发明提供的一种具有抗辐射加固结构的低功耗晶体管器件，通过在栅氧化层上制作下极板金属层109/铁电层110/上极板金属层111，或者铁电层110/上极板金属层111的栅极叠层结构，实现沟道电势大于外部栅极电压，突破热力学限制下的60mV/dec的亚阈值摆幅，降低工作电压从而降低器件的功耗，同时也提高了器件的抗辐照能力。
3、本发明提供的一种具有抗辐射加固结构的低功耗晶体管器件，为了实现栅极叠层结构的电容和栅氧层电容的匹配，铁电层采用Hf0.7Zr0.3O2或者Hf0.5Si0.5O2，栅氧层采用HfO2时，铁电层厚度和栅氧层厚度之比需小于4。实施例中，采用10nm的Hf0.7Zr0.3O2作为铁电层，为了实现最佳匹配，栅氧层厚度设置为5nm，可实现器件抗辐照性能提升以及亚阈值摆幅从60.412mV/dec降低到40.285mV/dec的效果。
附图说明
图1(a)、(b)为本发明具有抗辐射加固结构的低功耗晶体管器件的两种实施方式；其中，(a)栅极叠层结构为下极板金属层109/铁电层110/上极板金属层111，(b)栅极叠层结构为铁电层110/上极板金属层111；
图2(a)～(h)为本发明实施例提供的一种基于MFMIS结构的具有抗辐射加固结构的低功耗晶体管器件的制备流程图；
图3为实施例提供的低功耗晶体管器件的仿真结果图；
图4为PDSOI的器件(部分耗尽型SOI器件)和实施例晶体管器件在单粒子辐射的情况下，敏感节点漏极的瞬态电流值对比图。
具体实施方式
以下，将参照附图和实施例来描述本发明。但是，这些描述只是示范性的，而非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免和本发明的概念混淆。
在附图中示出了根据本发明实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
图1(a)-(b)为本发明具有抗辐射加固结构的低功耗晶体管器件的结构示意图；具体为基于SOI衬底的MFMIS(金属/铁电/金属/介质/半导体)或者MFIS(金属/铁电/介质/半导体)结构，对SOI衬底的体硅层103进行多次离子注入，形成深结源区108a和深结漏区108b，源漏区与埋氧层102相接触，使得没有超薄体硅层的SOI结构可以等效成全耗尽SOI结构，从而减小了浮体效应，抑制寄生二极管放大效应，进一步减小敏感存储节点收集辐射电荷的能力。在体硅层103表面上生长栅氧化层104，在栅氧化层104表面上形成下极板金属层109/铁电层110/上极板金属层111、或者铁电层110/上极板金属层111的栅极叠层结构，两者的区别在于前者有下极板金属层109提供等势面，两者均可与高K栅介质CMOS工艺相兼容。
实施例
图2(a)～(h)为实施例提供的一种基于MFMIS结构的具有抗辐射加固结构的低功耗晶体管器件的制备流程图。
如图2(a)所示，准备SOI衬底，其中SOI衬底包括衬底101、埋氧层102以及体硅层103。其中，衬底101为掺杂浓度为1～5*1017cm-3的P型硅，优选地，掺杂浓度为1*1017cm-3；埋氧层102为SiO2；体硅层103为掺杂浓度为1～5*1015cm-3的P型硅，厚度为50～200nm，实施例中，掺杂浓度为1*1015cm-3，厚度为200nm。
如图2(b)所示，清洗SOI衬底后，在体硅层103表面生长栅氧化层104。具体地，栅氧层材料为低K介质SiO2、抗辐照的SiO2/Al2O3或者高K栅介质HfO2，厚度为1～5nm；可以通过热氧化生长的方式热生长SiO2，也可以在热生长质量好的1～2nm的SiO2后，通过ALD淀积一层Al2O3，位于SiO2表面的单层Al-O键会引入受主态捕获电子，从而在界面处产生负的固定电荷，降低SiO2的表面态Dit，形成抗辐照的栅氧化层，也可以通过ALD淀积高K栅介质HfO2，本实施例中，选择5nm高K栅介质HfO2。
如图2(c)所示，利用光刻胶PR1进行构图，确定栅极和源漏区的位置。
如图2(d)所示，以光刻胶PR1为掩模版，进行源漏区的第一次浅结注入，形成初始的浅结源漏区105a和105b，具体地，离子注入杂质源为PH3或AsH3，剂量为1.5～4.5*1015cm-2，能量为15～30KeV；本实施例中，选择剂量为3*1015cm-2，能量为20KeV的AsH3进行源漏区离子注入。
如图2(e)所示，形成侧墙106a和106b，具体地，通过大致共形的方式淀积一层氮化物层，然后以大致垂直于衬底表面的方向进行RIE刻蚀，以去除其横向延伸部分，留下其竖直延伸部分形成。
如图2(f)所示，以侧墙106a、106b和光刻胶PR1为掩模版，进行源漏区的第二次离子注入，形成源漏区107a和107b，具体地，离子注入杂质源为PH3或AsH3，剂量为1.5～5.5*1015cm-2，能量为15～45KeV。本实施例中，选择剂量为4*1015cm-2，能量为30KeV的AsH3进行源漏区离子注入。
如图2(g)所示，在侧墙106a和106b基础上再形成侧墙，以侧墙和光刻胶为掩模版进行源漏区的第三次注入，重复上述“形成侧墙-注入”的过程，直到形成与SOI衬底的埋氧层102接触的深结源漏区108a和108b，去除光刻胶。
进一步地，在每一次的源漏区离子注入后，都要进行退火处理来修复离子注入引起的晶格损伤。
然后，在栅氧化层之上淀积下极板金属层109，材料为TiN，优选地，通过溅射的方式形成厚度为3nm的TiN；接着在下极板金属层109上淀积铁电层110，材料为掺杂HfO2，优选地，通过ALD的方式淀积厚度为10nm的掺Zr的HfO2；具体的，掺Zr的HfO2材料组分为Hf0.7Zr0.3O2，其中Hf:Zr＝7:3；最后，在铁电层110上淀积上极板金属层111，材料为TiN，优选地，通过溅射的方式形成厚度为3nm的TiN。
如图2(h)所示，利用光刻胶进行构图，确定栅极叠层的位置，利用各向异性刻蚀对“下极板金属层109/铁电层110/上极板金属层111”进行刻蚀，刻蚀停止在SOI衬底表面。
为了使铁电层110材料Hf0.7Zr0.3O2具有铁电性，需要进行退火处理，通过合适温度的退火，使铁电材料形成铁电相，退火温度为400℃～700℃，退火时间为30s～60s。本实施例中，退火温度为500℃，退火时间为50s。
图3为实施例提供的低功耗晶体管器件的仿真结果图；该结构中源漏采用多次离子注入，实现深结结构，源漏结与底部二氧化硅层接触。图4为PDSOI的器件(传统的部分耗尽的SOI结构器件)和实施例晶体管器件在相同能量的单粒子辐射情况下，器件敏感节点漏极的瞬态电流值对比图；由图4可知，采用本发明的器件结构，单粒子在器件中产生的瞬态干扰脉冲幅度可以降低2～8倍，同时仿真结果也表明采用本发明晶体管器件所搭建的6管结构的SRAM存储单元，抗单粒子翻转的能力有明显的提高，甚至可以提高1～2个数量级，同时器件的亚阈值摆幅从60.412mV/dec降低到40.285mV/dec。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。
Claims (6)
1.一种具有抗辐射加固结构的低功耗晶体管器件，其特征在于，包括衬底(101)，位于衬底(101)之上的埋氧层(102)，位于所述埋氧层(102)之上的体硅层(103)，位于所述体硅层(103)之中、两侧的源区(108a)和漏区(108b)，位于体硅层(103)之上的栅氧化层(104)，位于所述栅氧化层(104)之上的栅极叠层结构，所述栅极叠层结构自下而上依次为下极板金属层/铁电层/上极板金属层，或者自下而上依次为铁电层/上极板金属层；其中，所述下极板金属层的材料为TiN，厚度为2～5nm；所述铁电层的材料为掺杂HfO2，厚度为10～30nm；所述上极板金属层的材料为TiN，厚度为2～5nm。
2.根据权利要求1所述的具有抗辐射加固结构的低功耗晶体管器件，其特征在于，所述掺杂HfO2为掺杂Si的HfO2、或者掺杂Zr的HfO2。
3.根据权利要求1所述的具有抗辐射加固结构的低功耗晶体管器件，其特征在于，所述掺杂HfO2为Hf0.5Si0.5O2、或者Hf0.7Zr0.3O2。
4.根据权利要求1所述的具有抗辐射加固结构的低功耗晶体管器件，其特征在于，所述铁电层厚度和栅氧层厚度之比小于4。
5.根据权利要求1所述的具有抗辐射加固结构的低功耗晶体管器件，其特征在于，所述源区和漏区是通过对体硅层进行多次离子注入形成的，所述源区和漏区的厚度与体硅层的厚度相同，使源漏结与埋氧层接触，提高器件的抗单粒子辐照能力。
6.一种具有抗辐射加固结构的低功耗晶体管器件的制备方法，其特征在于，包括以下步骤：
步骤1、准备SOI衬底，SOI衬底包括衬底、埋氧层以及体硅层；
步骤2、清洗衬底，在衬底上生长栅氧层；
步骤3、采用光刻刻蚀工艺，将源区和漏区位置处的栅氧层刻蚀掉，露出体硅层；
步骤4、进行源漏区的第一次浅结离子注入，形成浅结源区和浅结漏区；
步骤5、退火修复离子损伤；
步骤6、形成侧墙，进行第二次离子注入；
步骤7、退火修复离子损伤；
步骤8、在步骤7的侧墙基础上再次形成侧墙，多次重复以上“形成侧墙-离子注入”步骤，直到形成与埋氧层接触的深结源区和深结漏区；
步骤9、在栅氧化层上依次淀积下极板金属层/铁电层/上极板金属层，或者依次淀积铁电层/上极板金属层；
步骤10、采用光刻刻蚀工艺，刻蚀停止在SOI衬底表面，即可得到所述具有抗辐射加固结构的低功耗晶体管器件。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911294299.5A CN111081761B (zh) | 2019-12-16 | 2019-12-16 | 具有抗辐射加固结构的低功耗晶体管器件及其制备方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911294299.5A CN111081761B (zh) | 2019-12-16 | 2019-12-16 | 具有抗辐射加固结构的低功耗晶体管器件及其制备方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111081761A true CN111081761A (zh) | 2020-04-28 |
| CN111081761B CN111081761B (zh) | 2022-05-03 |
Family
ID=70314963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911294299.5A Active CN111081761B (zh) | 2019-12-16 | 2019-12-16 | 具有抗辐射加固结构的低功耗晶体管器件及其制备方法 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111081761B (zh) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863608A (zh) * | 2020-07-28 | 2020-10-30 | 哈尔滨工业大学 | 一种抗单粒子烧毁的大功率晶体管及其制作方法 |
| CN113193047A (zh) * | 2021-03-31 | 2021-07-30 | 南京邮电大学 | 一种不同厚度铁电层的负电容场效应晶体管及制备方法 |
| US20220209018A1 (en) * | 2020-12-31 | 2022-06-30 | International Business Machines Corporation | Field effect transistor (fet) devices |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW409366B (en) * | 1997-03-07 | 2000-10-21 | Sharp Kk | Ferroelectric memory cell and method of making the same |
| US20080242038A1 (en) * | 2007-03-28 | 2008-10-02 | Mark Liu | Methods of forming a multilayer capping film to minimize differential heating in anneal processes |
| CN102194828A (zh) * | 2010-03-16 | 2011-09-21 | 北京大学 | 一种新型源漏结构的抗辐照soi器件及制备方法 |
| US20120104474A1 (en) * | 2010-10-29 | 2012-05-03 | Institute of Microelectronics, Chinese Academy of Sciences a Chines Corporation | Transistor and method for forming the same |
| CN103000613A (zh) * | 2012-12-12 | 2013-03-27 | 中国科学院物理研究所 | 一种复合半导体层 |
| US20160064510A1 (en) * | 2014-08-26 | 2016-03-03 | Globalfoundries Inc. | Device including a floating gate electrode and a layer of ferroelectric material and method for the formation thereof |
| CN108122757A (zh) * | 2016-11-29 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其制造方法 |
| CN108538850A (zh) * | 2018-04-18 | 2018-09-14 | 湘潭大学 | 一种高抗疲劳性的铁电栅场效应晶体管存储器及制备工艺 |
-
2019
- 2019-12-16 CN CN201911294299.5A patent/CN111081761B/zh active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW409366B (en) * | 1997-03-07 | 2000-10-21 | Sharp Kk | Ferroelectric memory cell and method of making the same |
| US20080242038A1 (en) * | 2007-03-28 | 2008-10-02 | Mark Liu | Methods of forming a multilayer capping film to minimize differential heating in anneal processes |
| CN102194828A (zh) * | 2010-03-16 | 2011-09-21 | 北京大学 | 一种新型源漏结构的抗辐照soi器件及制备方法 |
| US20120104474A1 (en) * | 2010-10-29 | 2012-05-03 | Institute of Microelectronics, Chinese Academy of Sciences a Chines Corporation | Transistor and method for forming the same |
| CN103000613A (zh) * | 2012-12-12 | 2013-03-27 | 中国科学院物理研究所 | 一种复合半导体层 |
| US20160064510A1 (en) * | 2014-08-26 | 2016-03-03 | Globalfoundries Inc. | Device including a floating gate electrode and a layer of ferroelectric material and method for the formation thereof |
| CN108122757A (zh) * | 2016-11-29 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其制造方法 |
| CN108538850A (zh) * | 2018-04-18 | 2018-09-14 | 湘潭大学 | 一种高抗疲劳性的铁电栅场效应晶体管存储器及制备工艺 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863608A (zh) * | 2020-07-28 | 2020-10-30 | 哈尔滨工业大学 | 一种抗单粒子烧毁的大功率晶体管及其制作方法 |
| US20220209018A1 (en) * | 2020-12-31 | 2022-06-30 | International Business Machines Corporation | Field effect transistor (fet) devices |
| US11527647B2 (en) * | 2020-12-31 | 2022-12-13 | International Business Machines Corporation | Field effect transistor (FET) devices |
| CN113193047A (zh) * | 2021-03-31 | 2021-07-30 | 南京邮电大学 | 一种不同厚度铁电层的负电容场效应晶体管及制备方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111081761B (zh) | 2022-05-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111081761B (zh) | 具有抗辐射加固结构的低功耗晶体管器件及其制备方法 | |
| US11145510B2 (en) | FinFET device over convex insulating structure | |
| US9905467B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6537885B1 (en) | Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer | |
| US20120315736A1 (en) | Semiconductor device and method of manufacturing the semiconductor device | |
| CN113035716B (zh) | 基于22nm工艺的SONOS结构抗辐照FDSOI场效应管及其制备方法 | |
| CN101621009A (zh) | 一种制作部分耗尽soi器件体接触结构的方法 | |
| CN111986996B (zh) | 改善自热效应的soi器件及其制备方法 | |
| CN103730370B (zh) | 提升mosfet性能和nbti的方法和结构 | |
| CN115662902A (zh) | 沟槽型场效应晶体管的制作方法 | |
| CN105374878B (zh) | 包括带电荷穿通阻止层以降低穿通的半导体器件及其制造方法 | |
| CN103681332B (zh) | 晶体管的形成方法、半导体器件的形成方法 | |
| TWI429027B (zh) | 具有減輕閘極摻雜之半導體結構及其形成方法 | |
| CN103280409A (zh) | 一种结型场效应晶体管的制造方法 | |
| CN111223916A (zh) | 半导体器件及其制备方法和三维存储器 | |
| CN113644115B (zh) | 基于22nm工艺的抗辐照FDSOI场效应管及其制备方法 | |
| CN111564443B (zh) | 一种高集成密度半浮栅存储器及其制备方法 | |
| CN109285876A (zh) | 半导体结构及其形成方法 | |
| CN112382663B (zh) | 一种抗单粒子效应的FinFET器件及制备方法 | |
| CN111785777B (zh) | 高压cmos器件及其制造方法 | |
| CN110581172B (zh) | 半导体结构及其形成方法 | |
| CN110349957B (zh) | 半导体结构及形成方法、静态随机存取存储器及形成方法 | |
| US8956948B2 (en) | Shallow trench isolation extension | |
| CN110491934A (zh) | Fdsoi-mos晶体管、电路单元及其制造方法 | |
| CN106952954B (zh) | 一种soi mos器件及其制作方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |