TW409366B - Ferroelectric memory cell and method of making the same - Google Patents

Abstract

A method of forming a semi-conductor structure forming, on a prepared substrate, a ferroelecuic memory (FEM) gate unit. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on a FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer, and which is formed on a conductive channel precursor. The structure of the semiconductor includes a substrate, which may be either bulk silicon or SOI-type silicon, conductive channels of first and second type formed above the substrate, an FEM gate unit formed above a channel region, wherein the FEM gate unit includes a lower metal layer, an FE layer, and an upper metal layer, and wherein a conductive channel of a second type is formed under the FEM gate unit.

Description

Central Standard of the Ministry of Economic Affairs 印 Printed by Employee Consumer Cooperatives ~ _409366 V. Description of the Invention (1) Background of the Invention 1 · Field of the Invention This case relates to ferroelectric thin films used for non-volatile memory, especially to metal-ferroelectric-metal -Oxide_fragmented semiconducting, body. : 2 · Description of related technology This case is about ferroelectric thin film for non-volatile memory, and especially about metal-ferroelectric; metal-silicon semiconductor (or shallow junction metal-ferroelectric-metal · broken semiconductor) ). It is known that a ferroelectric random access memory (FRAM) is composed of a transistor (1T) and a capacitor (1C). An electric worshipper is usually made between two conductive electrodes by sandwiching a ferroelectric film. The electrode is usually made of platinum. The circuit configuration and read / write sequence of this type of memory are similar to the conventional dynamic random access memory (DRAM), but FRAM does not require data update. FRAM is known to have fatigue problems, and fatigue problems observed in ferroelectric capacitors are a major obstacle limiting the commercial use of such memory. Fatigue is due to the increase in the number of cycles, and the exchangeable polarization decreases (the stored non-volatile charge decreases). For this example, the "swap cycle" means the sum of the read and write pulses of the memory. Another known use of ferroelectric thin films for memory applications is to form ferroelectric gated field effect transistors (FETs) on the FET gate region by directly depositing the ferroelectric thin film. This type of ferroelectric gate control device is known as a cabinet and includes a device called a metal-ferroelectric-stone evening (MFS) FET. Merging the F R A M 'of the MFS FET structure has two major advantages over the transistor-capacitor configuration: (1) Mps fet occupies less surface area, and (2) provides non-destructive readout (NDR). The features described below enable MFS FET devices to read thousands of times without exchanging ferroelectric polarization. Because — ™ This paper is suitable for Guancai County (CNS) A4 size (.2) Qx297 Gongchu < --- X3 water — (Jing first read the notes on the back before filling ^ this tile) Order A7 B7 5 2. Description of the invention (2) When using the MFS FET device, fatigue is not a problem. Can form various types of MFS FET structures, such as metal ferroelectric insulator silicon (MFIS) FET, metal ferroelectric metal silicon (MFMS) FET and metal ferroelectric metal oxide silicon (MFMOS) FET 0; ι To make an effective MFS FET device must Overcoming multiple problems. The first problem is that it is difficult to form an acceptable crystalline ferroelectric thin film directly on silicon. This structure is suitable for U.S. Patent No. 3,832,700. In addition, it is extremely difficult to have a clean interface between ferroelectric materials and silicon. Another issue concerns the proper charge of ferroelectric materials. The FEM structure on the gate is shown in US Net Profit No. 5,303,182, which emphasizes that the transfer of metal ions to the gate is not expected ^. A similar structure is shown in U.S. Patent No. 5,416,735. The object of the present invention is to overcome the aforementioned problems. An object of the present invention is to provide an MFS FET device capable of providing non-destructive readout. Another object of the present invention is to provide an MFS FET device occupying a relatively small surface area. Another object of the present invention is to provide an MFS FET device requiring a relatively low programming voltage. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling out this page) Another object of the present invention is to provide a FEM memory unit with extremely low leakage current. Another object of the present invention is to provide an MFS FET device including a MOS transistor / FEM unit. Another object of the present invention is to provide a FEM gate unit which is laid on the 接 Γ layer of the shallow junction, and the p · layer extends beyond the edge of the FEM gate unit. _ 5 _ ,, V-1 This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 mm) 409366 A7 B7 V. Description of the invention (3) '" Another object of the invention is to provide an FEM unit of the formed diffusion barrier. Another object of the present invention is to provide a FEM unit including a drain electrode in contact with the n + and P conductive surfaces. (Another object of the present invention is to provide a FEM device occupying a relatively small surface area and requiring a relatively low program voltage. Another object of the present invention is to provide a FEM gate unit with asymmetric ferroelectric polarization. 〆 Summary of the invention -? 1 The method for forming a semiconductor structure of the FEM unit of the present invention includes forming a device region for a ferroelectric memory FEM gate unit on a silicon substrate. Appropriate impurities are implanted into the device region to form a conductive path for use as a source junction region, The electrode junction area and the drain junction area. The FEM unit includes a FEM gate unit formed on the substrate. The gate junction area is opposite the FEM gate unit on the FEM gate unit device area and is formed at the source junction area and the drain junction. Area, the FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. (Schott: y) barrier layer or very shallow contact layer is formed at the interface between the FEM gate unit and the gate. The interval serves as another conductive path. The FEM gate unit is separated from the source region and the gate region. It depends on other devices built on the substrate 'and on the efficiency of various structural sequences. Forming multiple conductive paths can be manufactured in multiple Mouth section. FE The M-unit semiconductor structure includes a substrate, which can be a body. The substrate or an SOI substrate is formed by the first and second conductive paths, and a FEM gate unit is formed on the gate region. The unit includes-a lower metal layer, a FE layer, and an upper metal layer, and among them, the second-6-: said that the scale is suitable for wealth and family (CNS) A view grid (21GX297), " ~ 1 " ^-~~~ --- (Please read the notes on the back before filling out this page) Clothing. Order -d. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. Printed by the Consumers Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Da 0) 366 V. Description of the invention (4>) The "type" conductive path is formed in the FEM gate unit and the gate interval / FEM unit can be connected in series with the conventional MOS transistor. The method of the present invention for forming two transistor semiconductor structures includes A MOS transistor and a ferroelectric memory (FEM) gate: a device region are formed on a silicon substrate. Appropriate impurities are implanted into the device region to form a conductive path for use as a source junction region, a gate junction region, and a drain junction. Area. The conventional Mos transistor is formed on the substrate. FEM single It includes a FEM gate unit formed on the substrate, which can be located above or along the MOS transistor. The gate junction area is formed at the source junction area and the drain junction area of the fem gate unit. The gEM The gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. FEM: The gate unit is separated from the source region and the drain region, as is the conductive path between the FEM gate unit and the gate interface. Depending on the other devices on the substrate and the efficiency of various construction sequences, the formation of multiple conductive paths can be performed at multiple manufacturing stages. The two-transistor semiconductor structure includes a silicon substrate, which can be a bulk silicon substrate or an SOI-type substrate " Three types of conductive paths are located above the substrate. The FEM gate unit is located above the gate region, and can be above or along the side of the conventional MOS transistor. The FEM gate unit includes a lower metal layer, a fe layer, and an upper metal layer. The structure method includes forming a ferroelectric memory FEM gate on a silicon substrate, and a device area of the unit. Appropriate impurity implantation device regions form conductive paths for use as source contact areas, gate contact areas, and non-contact contact areas. The FEM unit includes a FEM gate unit formed on a substrate. For the formation of the FEM gate unit on the FEM gate unit installation area, a paper gate scale is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 OX 297 mm) ^, 4 Bn, -------- οAgriculture --------- IT ------ 0 (Please read the notes on the back before filling in this 苋) Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 409366 A7 ------- 67__ 5. Description of the invention (s) The region is between the source junction region and the non-electrode junction region. The FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. The shallow junction area is formed in the interval between the fem gate unit and the gate electrode as another conductive path. Just like the conductive path between the fem free cell and the gate interface, the fem, closed cell is separated from the source and non-electrode regions. Depending on the other devices built on the substrate and the efficiency of various construction sequences, forming multiple conductive paths can be performed at various manufacturing stages. The FEM unit half < body structure includes a substrate which can be a bulk silicon substrate or a soi-type substrate. The first and second conductive paths are located above the fist. The gate unit is located above the passage area. The jtem gate unit includes a lower metal layer, an FE layer and an upper metal layer. The third type conductive path is located between the fEM gate unit and the passage. The FEM unit can be formed in series with a conventional MOS transistor. The method for forming a semiconductor structure of an FEM unit of the present invention includes forming a device region of a ferroelectric memory FEM gate unit on a silicon substrate. Appropriate impurities are implanted into the device to form a conductive path for use as a source junction area, a gate junction area, and a drain junction area. : The FEM unit includes a FEM gate unit formed on the substrate. A gate junction area is formed between the source junction area and the drain junction area of the FEM gate unit on the FEIM gate unit device area. The FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal. Floor. The shallow junction layer is formed in the interval between the fem gate unit and the gate electrode as a conductive pathway, which extends into the drain junction region. The FEM gate unit is separated from the source region and the drain region just like the conductive path in the gate contact area of the FEM gate unit. Depending on what other devices are built on the substrate and the efficiency of various constituent sequences, the formation of multiple conductive paths can be performed at multiple manufacturing stages. -8-This paper size applies to Chinese National Standard (CNS) A4 specification (21 × 297). (Please read the precautions on the back before filling this page.) Order i. 409B66 B7 V. Description of the invention (6) FEM unit semiconductor The structure includes a silicon substrate, which can be a bulk silicon substrate or an SOI type substrate. Two types of conductive paths are located above the substrate. The FEM gate unit is located above the gate region. The FEM gate unit includes a lower metal layer, an FE layer and an upper metal layer. Another third type of conductive via is located between the FEM attachment unit and the via region and extends into the drain region. The FEM unit can be formed in series with a conventional MOS transistor. A method for forming a semiconductor memory device on a silicon substrate includes implanting a first type doped impurity silicon substrate to form a first type conductive path for use as a gate region; forming a MOS capacitor If on the first type conductive path; and depositing a FEM capacitor On MOS capacitors, a lower metal layer FE layer and an upper metal layer are deposited to form a stacked gate unit; a second type of doped impurity is implanted on a silicon substrate on either side of the gate region to form a second type conductive path for use as The source junction region and the drain junction region; and the deposited insulation structure surrounds the FEM gate unit perimeter. Printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (谙 Please read the notes on the back before filling in " this page)

A ferroelectric memory (FEM) unit constructed according to the present invention includes a silicon substrate; a gate region is located on the substrate, and a first type conductive path is formed by doping: a source junction region and a drain junction region It is located on either side of the gate region of the substrate and is doped to form a pair of second-type conductive paths. A MOS capacitor includes an oxide layer and a third-type conductive layer on the gate junction area. The device has a predetermined surface area; a FEM capacitor includes a lower metal layer: an FE layer and an upper metal layer; wherein the FEM capacitor / container is stacked on and laid on at least part of the MOS capacitor, and thus forms a stacked gate unit with the MOS capacitor; An insulating layer has an upper surface laid on the interface area, the stack gate unit and the substrate; and a source electrode-9- This paper size is applicable to China National Standards (CNS) A4 specifications (210X297 mm)

Department of Economics, Central Standard, Malaysia, Consumer Cooperation, Du Printed 409366 A7 B7 V. Description of Invention (7) 'and a non-polar electrode are located on the surface of the insulation layer and extend through the insulation layer to make electrical contact with its individual interface area And a gate electrode is located on the upper surface of the insulating layer and extends through the insulating layer to make electrical contact with the metal layer above the stacked gate unit. These and other objects and advantages of the present invention will become more complete and clear by studying the following description in conjunction with the accompanying drawings. Brief Description of the Drawings Figures 1 and 2 illustrate examples of sequential steps for forming a substrate for a FEM unit of the present invention. Figure 3 illustrates a FEM gate unit constructed on a substrate. Fig. 4 illustrates a specific example of the FEM unit of the present invention, which includes a silicon layer formed under the FEM gate unit. Fig. 5 illustrates the preparation of a substrate for another specific example of the present invention. Fig. 6 illustrates the current flow of another FEM unit of the FEM. Gate unit of the present invention formed on a p-conductive layer. tThe basic operating principle of the MFSFET device of the present invention. Line diagram of the ID of the invented FEM gate unit,

Figures 10-13 illustrate the sequential stages P of the FEM unit preparation substrate and active area formation used in the present invention. Figure 14 illustrates the complete two-transistor memory cell as constructed on a bulk silicon acoustic board. FIG. 15 illustrates a complete two-transistor memory cell formed on an SOI substrate. Figure 16 illustrates a complete two-transistor memory cell constructed on an SOI substrate. -10 paper rule Lai Choi_ 家 榡 ^ TCNS (This page)

4093G6 A7 B7 V. Description of the invention (8) Another specific example.

Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs of the present invention, a 4 X 4 array of memory cells. Prove the basic operation principle of the MFSFET device of the present invention. The ID of the invented FEM gate unit is relative to the graph. FIG. 20 illustrates a substrate and a fertile region for a FEM unit of the present invention. FIG. 21 illustrates a substrate on which a FEM gate unit is formed. Fig. 22 illustrates a FEM gate unit formed on a substrate and surrounded by an insulating region. FIG. 23 illustrates that the FEM gate unit of the present invention has a source electrode, a gate electrode, and a non-electrode region attached to a substrate. Figure 24 illustrates the present invention; the pEM unit has a shallow junction layer formed below the FEM gate unit. _ Figure 25: The complete FEM unit of the present invention also clarifies the current flowing through it. The basic operating principle of the MFS FET device of the present invention-The ID of the FEM gate unit of the invention is compared to the VGT line diagram. : Figures 28-3: 0 illustrate the sequential stages of preparing substrates and forming active regions for the hand-mu cells used in the present invention & Figure 31 illustrates the FEM gate units formed on the substrate and surrounded by insulating regions. FIG. 32 illustrates that the FEM unit of the present invention has a source t-gate, a gate, and a drain region formed on a substrate. FIG. 33 illustrates that the FEM unit of the present invention has a shallow junction layer formed under the FEM gate unit. 11 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling out this page) hi V. Description of the invention (9 409366 A7 B7 Figure 34 illustrates the invention The complete FEM unit and the current flowing through it are also illustrated. Figure 35 illustrates an example of the replacement of the FEM unit formed on the main body substrate. 'Figure 3 ^^ 1 ^ The specific replacement of the FEM unit formed on the 301 substrate For example, the basic operating principle of the MFSFET device of the present invention is shown. Figure of the ID of the FEM gate unit of the invention vs. VG. _, Picture theory, the single transistor formed according to the present invention "offset stack gate single code-Figure 4 ^ 〇; Ming Yi explained the structure of the stacked transistor gate structure based on mining

1— ·· -1 Λ -II:-^^ 1 1 ^ 1 1 ^ 1 (Λ- ^ fe ^ —r. I {Please read the precautions on the back before filling this page} r ”ii, 1 Economy Figures 46-49 printed by the Ministry of Standards and Staff's Consumer Cooperatives illustrate the sequential steps of a variation example of a single transistor stacked gate unit composed according to the present invention. 'Figure 5〇_ ^] The P-E magnetic field of the FE of the present invention Hysteresis diagram. Figure sijg ^ jsib is the charge of the device in the "0 J state" and "i" state of the device according to the invention. Figure 5 shows the ID of the FEM gate unit versus the VG of the invention. Figure 5 FEMj constructed according to the invention $. The invented FEM, the unit ID is relative to the VG, and the PE hysteresis loops of various FEM gate units. Basic operating principle of the MFS FET device of the present invention Figure 57 illustrates a memory array constructed according to the present invention.

-12- The paper size of the table applies the Chinese National Standard (CNS) M specification (2) 0X297 mm) ό Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 409366 at 'B7 V. Description of the invention (10)' Explanation (Example 1) The ferroelectric memory (FEM) unit of this example can be formed on a SOI (SiMOx) substrate, or it can be formed on a bulk silicon substrate to form 7 counterbores. It is said that the fem gate unit is formed on the SIMOX substrate during the moon operation. It should be understood that in some specific examples of fem gate units, the MOS transistor system is manufactured at the same time as the ferroelectric memory unit by well-known hands in the industry. So for the sake of clarity, the drawing does not clarify the formation of MOS transistors. ^ Now referring to FIG. 1, the SIMOX substrate is illustrated at 3 ^ ^ In a specific example, the substrate 30 is formed of silicon dioxide and is a single crystal base β. As stated by _j, the substrate 30 can already be partially etched into the clarified configuration, and part of the substrate has been slightly doped to form an active region or device region 32, which provides the required background polarity, 'known in this example; for the n region The background polarity β is well known in the art. 'A plurality of such regions are formed on the surface of a silicon wafer. The FEM gate unit used in the present invention is arranged in a vertical grid to form a memory array. The rough formation and preparation method of the substrate will be explained initially. The j? EM gate unit will be laid on the substrate, and the final result will form a FEM memory unit. The edges of the active region 32 surround the inactive or insulating regions 30a, 30b, which are upward extensions of the substrate 30. A trench was formed in the first area of the substrate, which was explained at 34, 36. The trench area was finally filled with insulating material, usually silicon dioxide. Referring now to FIG. 2, it can be seen that the active region 32 has been modified into a source region 38, a gate region 40 and a drain region 4 2. These areas are shielded by applying photoresistance across the active area 32, and will eventually become the area of the gate area 40 and the appropriate ions will be applied to the Chinese National Elevation Standard (cns) Λ4 (2ΐ〇χ.297) T)

(Please read the notes on the back before filling out this page; I

Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ------- 409308 B7 V. Description of the Invention (11) The rest of the active area 32 is implanted to form two layers of η + layers, which is also called the first type conductive path here , Will be formed as the source region 38 and the drain region 42. In this example, the appropriate ion implantation can implant arsenic ions at a preferred energy of about 50 keV, but the range of implantation from 40 keV to 70 keV is acceptable, and the dose is from ~ cut, square centimeter to 5x1015 / cm2. range. In addition, phosphorus ions can be implanted in the same dose range with an energy range of 30 keV-60 keV. The wafers then excite and diffuse the implanted ions for processing. The temperature range of the heat treatment is 506c to lloo X :. At this point, the formation of the FEM gate unit can begin. Now referring to \ circle 3, the FEM gate unit is roughly indicated at 44 and includes a lower electrode 46, a ferroelectric (F; E) material 48 and an upper electrode 50. The structure of the FEM gate unit 44 begins by depositing a lower electrode on the gate region 40, which is also referred to herein as a second type conductive path. The lower electrode 46 may be made of Mg or iridium, platinum / iridium alloy or other suitable conductive material. The metal thickness is between 20 nm and 100 nm. Second, FE materials are deposited by chemical vapor deposition (CVD). The FE material can be any of the following: Pb (Zr, Ti) 03 (PZT), SrBi2Ta209 (SBT), PhGesOn, BaTi03, or LiNb03. The preferred order of the preferred compounds is PbsGesOu 'SBT and PZT. Most of the experimental work in the field of the FEM gate unit is to deposit PZT compounds to a thickness of 100 nm to 400 nm. · The upper electrode 50 is then formed on the gE material. The upper electrode may be formed from the same material as the lower electrode to a thickness of 20 nm to 200 nm. The precursor of the conductive path is indicated at 52. This precursor is finally diffused into the gate region 40 by the lower electrode 46 through the metal ions to become a metal silicide layer. __ -14- Two ____ · Touch home county (CNS) A in this paper scale system (2! GX297 reading): — ~ ~~ --- fjing read the precautions on the back before filling in this page j -Order_ -JU. A7 B7 409366 V. Description of the invention (12) Photoresist is applied to the FEM gate unit, and then the unit is etched into a proper configuration and size. It is necessary to understand that the three-layer FEM gate unit does not need to be accurately aligned as shown, The reason is that its shape can be formed by applying photoresist and etching with a mask having a different geometry. However, for clarity, the FEM gate unit is illustrated as having a structure adjacent to the facing sidewalls. Referring now to FIG. 4, the FEM gate unit 44 is illustrated as a component of the FEM memory unit 53, which includes the FEM gate unit 44 and the lower source region, the passage region and the non-electrode region. The specific example includes a layer formed in the FEM gate unit. Below the 4; a thin layer 54 of the compound, the conductive path precursor 52 is located here. As described in the second specific example of the method of the present invention, the sanding layer 54 may be formed before the components of the FEM gate unit 44 are deposited; or it is assumed that the lower electrode 46 is made of platinum (pt) or its alloy. Diffusion into the upper part of the gate region 40, forming a shallow silicide layer as a Xiaodi barrier layer, which is referred to herein as a third type conductive path. A layer of titanium oxide 56 or other appropriate barrier insulating material is formed by CVD to protect the FEM gate unit. Titanium oxide is etched to form the sidewall insulation layer of the gate electrode. The photoresist is formed by application and appropriate n + and P + regions by ion implantation. The oxide layer is formed by CVD or other suitable passivation insulation. Structure at 500 C to 1000X: heat treatment to passivate and diffuse the implanted ions. For a complete description of the FEM unit 53, a hole is formed in the oxide layer 58 and the source electrode 60, the gate electrode 62 and the drain electrode 64 and connected to a plurality of other components. The specific example illustrated in FIG. 4 shows the invention structure ‘simplest μ. The structure is a ferroelectric closed electrode depleting her S transistor. At the gate voltage of 0, the charge of the 10,000 n path under the closed cell is completely depleted. Therefore, the leakage current is extremely small. To maintain a small leakage, u The lower electrode 46 contacts any edge of the η sand, and this point is related to the η + source region. The standard of the household scale (CNS) applies (锖 Please read the notes on the back before filling in this 1)

1T d. Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs -15 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 409SS6 5. Description of the invention ^ # ~ At least 50 nm 俾 keep a small leakage current. But with the increase of];), remember, 矸, 厉, 兀, and 串联 series lightning resistance is also increased. Therefore, it is preferable that D is not greater than 300 nanometers. The contact between the ship-to-n-type dream barrier layer and the ferroelectric material is determined. = Current is the minimum to medium field strength of the gate current. The potential barrier between platinum and η-type silicon is 0.9 eV. A potential barrier of this size makes the "second channel unpolarized in the ferroelectric material, or the electrode under the ferroelectric material is completely depleted when it is polarized with a negative charge. When the ferroelectric material is polarized with a positive charge at the lower electrode, the threshold voltage of the memory transistor is small. The quality of these memory charges and the technique of changing the amount of voltage required by the programming unit will be described in detail later.

In another specific example of the MFSFET of the present invention, referring to FIG. 5, the p • layer 70 can be formed in the gate via region 40 as a conductive path precursor. The substrate 30 and the active region 32 are formed as a β p-layer as described in FIGS. 1 and 2 and can be formed by implantation; 6 or 3] [72 ions, or formed by diffusion of metal ions by a FEM gate unit. Boron ions can be implanted at an energy of 3 keV to 10 keV, while bF2 ions can be implanted at an energy of 15 keV to 50 keV. The ion concentration of the two cases is in the range of 1 × 10 η / cm 2 to 1 × 10 15 / cm 2. The bulk CMOS substrate is used as an example to explain the manufacturing process. The first step is to manufacture η · land and p-well structures, separate these structures, and implant the appropriate ions to provide the threshold voltage adjustment of the transistor. Photoresist is used to mask the CMOS section of the wafer. Secondly, the phosphorus ion is implanted into the p · well with an energy of 30 keV to 120 keV and a dose of 1.0 × 10 12 / cm 2 to 5.0 × 10 15 / cm 2, where a FEM gate unit will be formed. Multiple implantation steps and / or thermal diffusion are required to obtain the optimal donor distribution of the ιΓ layer. The photoresist is peeled off. Implanted η-type silicon -16 This paper is in accordance with the Chinese national standard (CMS〉 Α4 size (210 × 29 :?)) ((Please read the precautions on the back before filling in this tile)

409366 A7 B7 Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. The description of the invention (14) The layer can also be a selective epitaxial film with a thickness of lpnm to 1000nm and grown silicon instead. Boron (3 keV to 5 keV) or BF2 (30 keV to 50 keV) ion implantation has a dose of yOMOl2 / cm2 to 100x103 / cm2. Ions are thermally excited. Referring now to FIG. 6 ′, the FEM (R) unit is now formed by forming the lower electrode 46 by depositing inscriptions or other suitable materials as described above. This metal has a thickness of 20 nanometers to 100 ¾ micrometers. Can be implanted with puff or BF2 ions. The fe material 48 is deposited to a thickness of 100 nanometers to 4 "nanometers, and the upper electrode 50 is formed by depositing a thickness of 20 nanometers to 200 nanometers from platinum or other suitable electrode materials. Photoresist Upon application, and the upper and lower electrodes and FE are etched to provide the appropriate distance "D" from the source and drain regions as previously described. The photoresist is then removed by structural exfoliation. As illustrated in Figure 4, "Titanium oxide (56)" or another suitable barrier insulating layer is deposited by CVD to protect the ferroelectric material. Titanium oxide is etched to form a sidewall insulating layer on the gate electrode. Other oxides can be used in this step. Photoresist was applied again, and ions were implanted. Photoresist FEM exfoliation and oxide or another appropriate passivation insulating layer is applied by CVD. The structure is heated to densify the passivation insulating layer and activate the implanted ions. Photoresist was applied again, and the contact holes were engraved with silver. As for the method for forming the Xiaodi barrier layer 54 or the shallow junction layer, the barrier structure is used to provide the ingenuity of the present invention. In addition, if the ferroelectric material cannot be heated at high temperature, the source / drain ion implantation and annealing can be completed before the lower gate electrode is deposited. Assignment: The structure constructed according to the present invention is particularly effective because it is located in the closed pole area (please read the precautions on the back before filling in this tile) ^ ------

'1T

409366 A7 B7 V. FEM gate unit above the conductive path of the invention description (15). The polarity of the gate region can be moved, and the effective current can be obtained from the source flowing through the gate to the drain β structure in a "阙" shape ^ Provides almost complete charge depletion at all times and provides effective low heat transfer in the "on" state. Fig. 7 is an enlarged view of the FEM cell of the present invention and its explanation. A typical prior art current flow indicated by a dashed line 72, in which the current flowing through the gate region 40 is located just below the FEM gate unit. The reason is that the known fem cell configuration cannot fully allow current to flow through the gate region. This structure can be regarded as a semi-open "I". The solid line 74 illustrates the all-off switch of the present invention, where current can flow through the entire gate below the barrier structure 70; the acoustic zone. The memory early element formed according to the present invention can be placed in a memory cell array, so the gate line vertical drain line β is to be written into the FEM gate unit 4 4 ′ + Vpl is applied to all gate electrodes, and the source of the memory cell The electrode and the drain electrode are at a ground potential. The FE 48 is thus polarized so that the positive charge is located at the lower electrode 46 and the negative charge is located at the upper electrode 50 (see Fig. 8b). This makes the FEM gate unit 4 4 highly conductive. When the negative voltage -Vp0 is applied to the gate electrode (programming line) and the positive voltage + VpC is applied to the drain, and the source is grounded and here 丨 Vpl | > | Vp〇 丨, ^ is negative to the following electrode 46 The charge is polarized. This causes the feM gate unit 44 to be in a low conductivity state (see Fig. 8a). The nest process enables each memory transistor in the memory array to be written to other memory cells in the array without any interference from the threshold voltage of other memory cells in the array. The threshold voltage of the FEM gate unit 44 is determined as follows: For large arrays, the threshold voltage in the "1 J state must be positive, that is, 0,4 V to 0.8 V. The threshold voltage in the Γ 〇" state must be greater than the supply voltage. That is 3.3 V. η-pass layer is p-type base-18-This paper size applies Chinese National Standard (CNS) Λ4 specification (210 '< 297 cm) f J ^ — (Please read the precautions on the back before filling this page) -56 d Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 409360 A7 B7 V. Description of the invention (16) The board junction and the low-electrode Xiaodi barrier layer, or the very shallow p-surface layer and gate bias are consumed Exhausted. The memory window can be displayed as:

CPE Here Qfe is the residual charge and CFE is the ferroelectric capacitance of the gate unit. During the reading operation, a voltage Va that is not greater than the coercive voltage (that is, the voltage that can be changed in the memory content) is applied to the gate electrode and the drain electrode. As any electrode is biased with \ ^, the content of the memory cell is not disturbed, so the reading operation will not interfere with the memory content of any memory cell. Therefore, long-term charge retention can be obtained. -Single transistor memory cell: The general ID of MFMOS FET vs. VG is illustrated in Figure 9. Figure 9a illustrates the ID vs. VG characteristics of a FEM unit with a high-path doped ND. When the FEM gate unit is not charged, the center line is the ID vs. V0 curve. When the "1" state of the FEM unit program is planned, the threshold voltage of the FEM unit is negative. Such a large drain current flows through the path region, even if VG = 0 V. This device is not suitable for large and large array applications. Printed by the Central Laboratories of the Ministry of Economic Affairs and Consumer Cooperatives (please read the precautions on the back before filling in the clothing page) ⑴ ΔΥ, Figure 9b illustrates the ID vs. VG characteristics of the FEM unit with a low-pass doping. The threshold voltage of the FEM unit is positive when the program is planned to the Γ 1 ′ state. When the gate is at ground potential, no current flows through the device. The large memory array of such a device will have minimal standby leakage. Ferroelectric Pb5G & Ou film for MFMOS application: Displaying lower ferroelectric capacitance results in higher memory window and lower programming voltage. Thicker films and more mer materials can get lower ferroelectric capacitance; but if iron 19- this paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) 409366 A7 B7 Five 'invention description (17) The electric exchange field is clearly defined, the former option can increase the programming voltage. Common oxide ferroelectric materials have higher ~ and τ. Non-oxide ferroelectric materials have a lower erAT. 》 Oxide PbgGesOu film has extremely low sr and medium D. (178 ° C). Table 1 comparison! ^^ 03 device: Ji Yi body window and PbsGesOn, pZT and SrBi2Ta209 thin film ferroelectric gate. Even though the steady-state polarization of the film is much lower than that of the thin film, due to the low er $, the §memory window of the MFMOS device controlled by the PbsGhOu gate is larger than its relative window. Table 1: Memory window of MFM0S package with various ferroelectric materials (please read the precautions on the back before filling this page) 〇i ι

Pr * (^ C / cm2) when Vdep = 0.5V Note: hidden window2 Pr * / CFR (V) 0.8 0.25 order 1,08 1.29 3.23

Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs

The steady-state Vdep is assumed to be 0.5 V. Reveal FEM memory unit and its composition-Fang Qia. The FEM gate unit can be constructed as a single transistor device, and / or can be constructed with the associated Mos transistor. Although the preferred specific examples of the present invention have been disclosed, it should be understood that the structure and method of the present invention may be further changed without departing from the scope of the present invention, as defined in the appended patents. ___- 20-· ν 'The size of this paper is applicable to Chinese national standards (-: ~~ (Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 409366) 5. Description of the invention (18) (Example 2) Ferroelectric memory of this example (FEM) unit can be formed on a sol (SIMOX) substrate or can be formed on a bulk silicon substrate β The description here focuses on forming a FEM gate unit on the bulk silicon substrate ', but as used herein, "silicon substrate" means a S0I substrate or The body silicon substrate. It must be understood that the MOS transistor and the fem gate unit can be sequentially or simultaneously manufactured to form the double transistor structure of the present invention. The completed structure can provide a cost-effective extremely small memory unit with a simple circuit configuration. Provide non-volatile memory and have extremely low leakage current β. Referring now to FIG. 10, the silicon substrate is illustrated in ^ Feng; in the specific example, the substrate 210 is a single crystal substrate and is made of bulk silicon. The substrate 21 has been modified into a clarified configuration, and some substrates are slightly doped to form an active region or a device region 212, which provides the required background polarity. This example is the background polarity of the η-region, which is hereinafter referred to as the first Conductive path It is also referred to herein as the first type of doped impurity, and is formed by implanting a p-well to form a FEM gate unit with an energy of 30 keV to 120 keV at a dose of 1.0x1012 / cm2 to 5.0x1013 / cm2. Type I conductive pathways. Multiple implantation steps and / or thermal diffusion are required to obtain optimal donor distribution in the η · layer. The implanted n-type silicon layer can also be 100 nm to 1000 nm thick. The selective epitaxial film growth dream replaces the active region 212 with an insulating region 214. The insulating region is made of silicon dioxide by thermal oxidation or chemical vapor deposition (CV ^) to form a LOCOS between devices or / Inesa isolation. As is well known in the industry, multiple active regions are formed on the surface of the silicon wafer. As for the dual-electrode s memory cell 'active region of the present invention, they are arranged in a vertical grid to form a memory array (detailed later) ). -21-This paper size applies to Chinese National Standard (CNS) A4 (2IOX297 mm) r (Please read ΫNotes on the back before filling this page)

Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Civil Engineering A7 409366 B7 V. Description of the Invention (19) Now referring to FIG. 11, it can be seen that the structure of the semiconductor device of the present invention has progressed to the point that the MOS transistor 215 has been formed on the substrate. The active region 212 has been modified to include a p-well 216 by masking the active region 212 and ion implantation. The hafnium layer can be formed on the active layer 212 by implanting B or BFi ions (herein referred to as: a second type of dopant impurity). Boron ions can be implanted at an energy of 3 keV to 10 keV ’JBF2 ions are implanted at an energy of 15 keV to 50 keV. The ion concentration in the two cases ranged from 5x10η / cm2 to ιχ100.5 / cm2. Ion loan; thermal excitation. The implanted ion is diffused to form the Δη-active region to form a ρη layer ', which is referred to herein as a second type of conductive path. It is carried out at a temperature of 0 to 1100 c. The via region 718 of the first type conductive via remains on either side of the p-well 216. The outer side of the active region 212 is formed by masking a silicon dioxide layer 22 through the cvd on the plf 216 and a part of the via region 218. A layer of η + polycrystalline silicon was deposited thereon again by CVD. A silicide layer 224 may be formed on the η-poly second by cVD and as a component of a MOS transistor. Although illustrated in the drawings, it is an optional part of the method and structure of the present invention. Another silicon dioxide layer 226 is also referred to herein as a transistor insulation layer and is laid by cvd. In addition, a fine dioxide layer can be deposited in the non-shielded region and the via region 218 'of the p-well 216. The silicon dioxide layer is etched to form a sidewall, and η + polycrystalline. Wheat layer 222 and layer 224 are deposited therein. A top silicon dioxide layer is deposited on the sidewall and layer 224.

The MOS transistor is covered with a photoresist 22 ^, which covers the MOS transistor 215 and the via region 218 of the FEM gate unit. Then, the remaining device region 212 is formed by the ion implantation process! + Silicon source g23 and n + silicon drain region 232, which is referred to herein as a second type conductive path. Appropriate ion implantation in this example is about 50 keV 22- (Please read the precautions on the back before filling this page)

Bi S-, V

SN standard tr 410366 A7 ------B7 printed by the Central Bureau of Standards of the Ministry of Economic Affairs of the Bayer Consumer Cooperative V. Description of the invention (20) ^ The better energy for arsenic ion implantation, but the planting of 40 keV to 70 keV It is also acceptable and the dosage ranges from 1 × 10 5 / cm 2 to 5 × 10 15 / cm 2. In addition, phosphorus ions can be implanted at the same dose range from 30 keV to 60 keV. In either case, the material implanted in this constituent step is referred to herein as a type III dopant impurity. The photoresist is peeled off. Referring now to FIG. 12, a FEM gate unit 234 is manufactured. The closed cell includes the lower electrode 236, the fE layer 238, and the power core 240 FEM gate early element 234. The structure starts from sinking. The lower electrode is deposited on the silicon dioxide layer 226, and the dioxide layer partially extends on the via area jig. The power-down contacts 236 ~ T are made of box or silver, monoxide-sensitive or ship / stranded alloy or other suitable conductive materials. Electrodes of other preferred embodiments of the appropriate conductive barrier layer β can also be used. The thickness is 20 nm to ΐα0 nm. The FE material 238 is then deposited by CVD. The FE material can be any of the following: Pb (Zr5 Ti) 03 (PNZT), SrBi2Ta209 (SBT), Pb5Ge3〇u,

BaTi03 'or LiNbO are arranged in a preferred order, and the preferred compounds are PhGesOn, SBT and PZT. Most of the experimental work in the field of FEM idle units is performed on PZT compounds. The p E material 23 8 is deposited to a thickness of 50 μm to 400 nm. Then, an upper electrode 240 is formed on the FE material. The upper electrode is made of the same material as the lower electrode to a thickness of 2.0 nm. The photoresist is applied to the FEM gate unit, and then the unit is etched to an appropriate configuration and size. It must be understood that the three layers of the FEM gate unit do not need to be exactly aligned as shown, because the shape is based on the application of photoresist and has different geometries. The mask is formed momentarily. But for the sake of clarity, the FEM gate unit is clarified as having adjacent facing sidewalls-23- · :: This paper size applies the Chinese National Standard (CNS) Λ4 specification (2Ϊ〇 × 297 mm) {PLEASE read the precautions on the back first Ear fill in this page j

1T d 4093G6 A7 B7 V. The structure of invention description (21). (Please read the notes on the back before filling in the large page.) Now referring to Figure 13, the photoresist is peeled off by the FEM gate unit, and a layer of TiOx 242, Si3Ny ^ other suitable dielectric materials are isolated by CVD to isolate the ferroelectric materials. With silicon dioxide. 'As shown in Figure 14, this structure is completed by depositing a silicon dioxide layer 244, covering the insulating layer on the extension of the structure, and grinding and inserting the electrode 246, the gate electrode 248, and the source electrode 250. . Referring now to FIG. 5, the structure of the present invention is shown to be formed on an SOI substrate, which includes substantially all of the same parameters _ numbered with the specific example of FIG. 14-4: 4 identical components, but the substrate is made of dioxide Silicon 252 is made of bulk silicon instead of the bulk silicon used in the specific example of FIG. 14. Referring now to FIG. 16, an alternative specific example of the recording unit is schematically illustrated at 260. In this specific example, bulk silicon is used as the substrate 262 to form an active region 264 and subsequently modified into f-wells 266, ιΓ regions 268, 270, which serve as gate regions of the MOS transistor 272 and the FEM unit 274, respectively. Like the n + source region 278, an n + drain region 276 is formed. The oxide region 279 is formed next to the active region 264 and is formed by thermal oxidation or CVD. The materials of both the MOS transistor 272 and the FEM gate unit 274 are laid in order. As for each layer of the MOS transistor 272, a silicon dioxide layer 280, an n + polycrystalline silicon layer 282, and a selective silicon layer 284 are formed. The FEM gate unit 274, printed by the staff of the Central Standards Bureau of the Ministry of Economic Affairs, is formed through the bottom electrode 286, the FE material 288, and the top electrode 290. Next, TiOx, Si3N4, or other appropriate insulating / insulating layer 292 is deposited by CVD, and a silicon dioxide layer 294 is also deposited by CVD. The manufacturing process is completed by mounting the drain electrode 296, the gate electrode 298, and the source electrode 2100. The MOS transistor and FEM were ionized with TiOpt Si3N4 layer. This tool-24 · This paper size applies Chinese National Standard (CNS) A4 specification (210X297 cm) '4093 (56 .A 7 B7 V. Description of the invention (22) In the system, layer 292 is used as the transistor insulation layer, and layer 294 is used as the Cover the insulating layer. (Please read the precautions on the back before filling out this page} This has shown some specific examples of MFS transistor combinations formed next to MOS transistors. If "adjacent" is used here to indicate the formation of a double transistor along two sides: Or one transistor is stacked on top of the other.

Specific examples illustrated in Figs. 14, 15 and 16 show a conventional MOS transistor of a ferroelectric gate depletion type MIS transistor combination. When FE is at the bottom electrode interface 238a

The positive charge is polarized ^, and the threshold, voltage, and voltage of the MFS transistor can be negative. When FE is polarized with the negative charge of the bottom electrode interface 23 8a, the threshold voltage of the FS transistor is extremely large. At zero gate voltage, the MOS transistor "is not conductive. Therefore, even if the threshold voltage of the MFS transistor is negative, no current flows through the device. When the gate voltage is equal to the working voltage: the MOS transistor is extremely conductive. The device current is controlled by the current flow of the MFS transistor. When the MFS transistor is in the "0" state, that is, when the threshold voltage is greater than the operating voltage, no current flows through the device. To maintain a small leakage current in the "0_!" State, the distance between any edge of the lower electrodes 236 and 268 and any edge of the n + source region and the n + drain region is represented by "D", which must be at least 50 nm. However, as D increases, the series resistance of the memory cell also increases. Therefore, D is preferably not more than 300 nm. When the MFS. Transistor is in the "1" state, that is, when the threshold voltage is extremely low or has a negative voltage, the printed body of the MOS transistor's Central Standards Bureau employee consumer cooperative and the MFS transistor are conductive. Therefore, the large electric jfL peak passes through the device. This allows the device to be used in large / memory arrays even if the "1" state threshold voltage of the MFS transistor is negative. Operation: The memory unit constructed according to the present invention can be placed in the memory unit array, and the gate-25- ;: This paper size is applicable to China National Standard (CMS) A4 specifications (2 丨 0: ', 297 cm)' 409366 A7 B7 5. Description of the invention (23) The epipolar line is perpendicular to the non-polar line, as shown in FIG. Now, referring to FIG. 14, 17, 7 and 18, if the FEM gate unit 234 is to be nested, + Vpl is applied to all the inter electrode 248 (Y1, Y2, Y3, and Y4), and the source electrode of the memory cell is 25. The drain electrode 246 (XI, X2, X3, and X4) is located at ground. The potential a is so polarized as FE 238, so the positive charge is located at the lower electrode interface 238a and the negative charge is located at the upper electrode interface 238b (see FIG. 18b). This causes the FEM gate unit 234 to become highly conductive. When negative voltage-Vp0 is applied to the gate electrode 248 .. '(programming line), for example, Y 2' Positive voltage + VPQ is applied to ί and electrode 23 2, for example, if it is X 3, and source 230 ground and here 丨 Vpi 丨 > .j Vp〇 丨 'F E such as 210 stand, X 3, Υ 2 with the negative charge polarization of the lower electrode interface 23 8a. This puts the 'FEM closed cell 234 in a low conductivity state (see Fig. I8a). The nesting process allows each memory transistor of the memory array to be nested incoherently with other memory cells in the array without interfering with other memory cells in the array. The threshold voltages of the FEM gate units 215 and 274 shown in Figures 14 and 16 are as follows: For large arrays, the threshold voltage in the Γ 1 ″ state can be negative 値 or small positive dust. The threshold voltage of the "0" state must be greater than the supply voltage, which is 33 V. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs If the impurity density of the if area is about ΐ, Οχίο! 6 / cm3, the interval width of the ιΓ area of the pt_n barrier layer is about 0.3 microns. The threshold voltage can be adjusted by changing the doping density and thickness of the n-channel region to make the ferroelectric capacitance-gas $ permittivity and residual charge. f During the reading operation, a voltage Va that is not greater than the coercive voltage (that is, the voltage that changes the memory content) is applied to the gate electrode and the drain electrode. As any electrode is biased with va, the content of the memory cell is not disturbed, so the reading operation is -26- This paper size applies to China National Standard (CNS) A4 specification (210X297 public inspection) 409366 A7 B7 Central Standards Bureau of the Ministry of Economic Affairs Printed by Pui Gong Consumer Cooperative Co., Ltd. 5. Description of the invention (24 will not interfere with any memory content of _ 记 开 ^ u 早 疋. Therefore, long-term charge retention is obtained. Compared with v & Objective: The brain unit of ND mixed with high pathway. Relative to readability

. When the FEM gate unit is not dreaming, the center line 2104 is ^ relative to V. curve. When the FEM unit's% formula is set to the “1” state (line 21G6), the threshold voltage of the fem unit is negative ▲ FEM unit, and when the program is set to the “0” state (line 2⑽), the fem unit voltage is positive. This is in the "1" state .. Even if VG = 0V, it is possible to flow the Ik channel area. Such a device alone does not fill a large array application. Figure 19b illustrates the relative characteristics of the device according to the invention. The Id vs. ν curve of line J 2 Nameitian FEM gate unit when it is not charged. When the cell programming is in the "1" state (line 2110), the threshold voltage of the FEM cell is negative. When the FEM cell program is planned to be “0” (line 2114), the threshold voltage of the positive% cell is positive. When the threshold voltage of the MOS transistor (dotted line 2116) is “1J state, the device threshold voltage is limited to the small positive voltage. When the gate is at ground potential, no current flows through the device. The large memory of this device The array will have a very small standby leakage current. In this way, a dual-transistor memory cell including a MOS transistor and a FEM gate unit and a method for constructing the same have been disclosed. The structure and method have been further changed without departing from the scope of the present invention as defined in the accompanying patent application. (Example 3) The ferroelectric memory (FEM) unit of this example can be mounted on a SOI (SIMOX) substrate. 27--· This paper size is applicable to China National Standards (CNS) M specification (210X29 * 7mm) r (Please read the notes on the back of this page before filling out this page)

409366 Printed by the Consumers' Cooperative of the Central Bureau of Standards and Assistance of the Ministry of Economic Affairs of the People's Republic of China 5. Invention Description (25) — can be formed on the silicon substrate. The description here focuses on forming a FEM gate unit on a bulk silicon substrate. It must be understood that in some specific examples of FEM gate units, the MOS transistor system is manufactured at the same time by a well-known means known to those in the industry = ferroelectric memory cells. As such, for the sake of clarity, the formation of MOS transistors is not illustrated in the drawings. Referring now to FIG. 20, the silicon substrate is illustrated at 310. In a preferred embodiment, the substrate 310 is a single crystal substrate; it is made of bulk silicon. Other specific examples can be formed on the soi substrate. For example, the term "silicon substrate" is used herein to refer to the bulk silicon substrate or soi substrate or any other appropriate silicon-based substrate. As shown in Figure 2, substrate 310 has been partially etched to the The configuration and the sub-substrate have been slightly doped to form an active region or device region 312, which provides the background polarity. In this example, the n-region polarity is referred to herein as the first type of conductive path. The active region 312 consists of One gasification second insulation zone package garden. As is well known in the industry, multiple such areas are formed on the surface of a silicon wafer. The FEM gate sheet 7L used in the present invention has a vertical grid structure to form a memory. Arrays. The bulk CMOS substrate is used as an example to explain the process. The initial steps are to manufacture n-well and p-well structures, isolate these structures, and implant the appropriate ion to provide the threshold voltage adjustment of the transistor. Photoresist is used to shield the wafer area Secondly, phosphorus ions (herein referred to as the first type doped impurities) are implanted at an energy of 30 keV to '12 keV at a dose of 1.0x1012 / cm2 to 5,0χ1013 / m2, which will constitute a FEM gate. Single redundant p_well. 雩Multiple implantation steps and / or thermal diffusion are required to obtain the optimal donor distribution in the η layer. The photoresist is stripped and removed. The implantable silicon layer can also be silicon with a thickness of 100 nm to 〇00 nm Growth epitaxial film growth alternative. '• II-' (Please read the notes on the back before filling this page)-»d-28-28” Winter ... Min Zhang standards are applicable to China National Standards (CNS) specifications. (2IGx 297) 409366 A7 __. B7 V. Description of the invention (26) At this time, the FEM gate unit is formed. Now refer to Figure 21 1. The FE gate unit is generally labeled at 316, including the lower metal layer or electrode 318, iron Electrical (FE) material 320 and an upper metal layer or electrode 322. The composition of the FEM gate unit 316 starts by depositing a lower electrode on the active region 312, and a lower electrode 318; it can be made of Pt, Ir, or Pt / Ir alloy or other suitable conductive materials. In a preferred embodiment, the metal has a thickness of 20 nm to 100 亳 m. Finally, a p-layer can be formed at the interface between the FEM gate unit 316 and the gate. The p-layer may be formed by implanting B or BF2 ions into the first type conductive surface or the lower electrode 318. Shelf ions can be implanted at 3 keV to 10 keV energy, and 3? 2 ions are implanted at 15 keV to 50. keV energy. The ion concentration of the two kinds of emotions is in the range of lxlO11 / cm2 to lxlO15 / cm2. In the annealing step (to be detailed later), the implanted ions diffuse into the η-gate junction area to form a p_ layer, which is referred to herein as a third type conductive path. Secondly, after proper shielding, the FE material is deposited by chemical vapor deposition (CVD). ? The ugly material can be any of the following: Pb (Zr, Ti) 03 (PZT), SrBi2Ta209 (SBT) 'Pb5Ge3On, BaTi03, or LiNb03. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Better Economy (please read the notes on the back before filling out this page) ηΊ The compounds are arranged in a better order as PbsGegOn, SBT and PZT. Most of the experimental work in the field of FEM gate units The PZT compound is performed. The FE material 320 is deposited to a thickness of 50 nm to 400 nm.-Then is formed on the FE material. The upper electrode 322 is made from the same material of the lower electrode to 20 nm f to 200. Nanometer thickness. The photoresist is applied to the FEM gate unit, and the unit is etched to the appropriate configuration and size. It must be understood that the three-layer FEM gate unit as shown does not need to be accurately aligned, because its shape may be applied by photoresist and Masks with different geometries are etched. But for the purpose of «29- r, this paper size applies the Chinese National Standard (CNS) A4 gauge (210X297 feet) ~ Γ ~ ^ --- 409366 A7 __B7---- -—Η ... ________ ____ V. Description of the invention (27) a 'It is clear that the FEM gate unit is clarified as having a structure adjacent to the opposite side wall.

TiOx, si # 4 or other appropriate barrier insulating material layer 324, as shown in Figure 22, is formed by CVD to protect the FEM gate unit. The barrier insulating material is etched to form the sidewall insulating layer of the gate electrode. .. Now referring to FIG. 23, it can be seen that the active region 312 has been modified into a source region 326, a gate region 328 and a drain region 330. Each region forms a two-layer layer (also referred to herein as a second-type conductive pathway) by implanting appropriate ions (also referred to herein as < type II doped impurities) into the rest of the active region 312, which will be referred to as a source here A polar region 326 and a polar region 330 are formed. The appropriate depleted implantation in this example can be performed at a preferred energy of about 50 keV implantation of osmium ions, but can be implanted in the range of 40kev to 70keV Fanyuan and used lxl0 [V cm2 to 5xl015 / m2 Dose in centimeters. In addition, phosphorus ions can be implanted in the energy range of 30 keV to 60 keV at the same dose range. Printed by the Shell Standard Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the note on the back and fill in this page) Now referring to Figure 24, the wafer is heated and excited to diffuse and implant the implanted ions including the source region and the Han Ions in the polar region and ions in the lower electrode. The diffusion of the implanted ions of the lower electrode 318 results in the formation of a shallow interface 332 'under the FEM gate unit 316. This is a third type conductive path. The temperature range of the heat treatment is 500 ° C to 110 ° C to purify and diffuse the implanted ions. Then cVD is used to form a silicon dioxide layer 334 over the structure, or other appropriate 'passivation insulation can be applied. Now refer to FIG. 2 5, FEM. Gate unit 31 $ Explanation: JEM is a part of FEM memory unit 336, FEM memory; the unit includes FEM gate unit 316 and the source, path, and drain regions below. This specific example includes a thin shallow junction area 332 It is a p-layer formed below the FEM gate unit 316. To complete the description of the FEM unit 336, a boring hole is formed in the oxide layer 334 and -30- This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) 4093G6 A7 B7 V. Description of the invention (28) The employee cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed the Gona source electrode 338, the gate electrode 340 and the drain electrode 342 which are connected to their individual components. The specific example illustrated in Figure 25 represents Ferroelectric gate depletion type 1 § Transistor. The charge in the η-channel under the zero-gate voltage 'FEM gate unit: the charge is completely depleted. This leakage current is very small. To maintain a small leakage current, the lower electrode 3 α 8 Any edge and η · source region The edge spacing of the n_drain region is indicated by "^". It must be at least 50 nm. It must maintain a small leakage current. However, as d increases, the resistance of the memory cell also increases. Therefore, the preferred D is not .. More than 300 nanometers. Gate leakage current is determined by ρ · type silicon shallow junction 332 and platinum to ferroelectric materials. The potential barrier between platinum and H-type silicon is 〇9 eV. Type III · The potential barrier between the ρ-conductive layer 332 and the first type ΓΓ conductive layer 328 is also about 0-9 ev. When a potential barrier of this size causes the ferroelectric material to not be polarized, the η-type silicon path is completely Depletion. The threshold voltage is small when the ferroelectric material is polarized with a positive charge on the lower electrode interface 348. When the ferroelectric material is polarized with a negative charge on the lower electrode interface 348, the threshold voltage of the transistor This kind of memory charge property and the technique of changing the programming and unit voltage requirements will be described in detail later. The implanted B or BF2 ions diffuse into the gate junction area by maintaining any edge of the shallow junction layer 332 and The distance between the source region and the drain region "c" controls 6. In a preferred embodiment, "C" is about 0 nm to 300 nm. Shallow The surface structure is used to increase the potential barrier layer with reliable leakage current between the gate region 328 and the conductive path and to provide an effective exchange mechanism of the FE] unit of the present invention. In addition, if the ferroelectric material cannot maintain high temperature heating treatment, it can be Complete source / drain ion implantation and annealing before lower electrode deposition. Assignment: Γ (Please read the precautions on the back before filling out this page)-.. Order d -31-Central Bureau of Standards, Ministry of Economic Affairs Printed by Pui Gong Consumer Cooperative 409366 A7 __ B7 V. Description of the Invention (29) The structure constructed according to the present invention is particularly effective because the FEM gate unit located above the conductive path in the gate region can transfer the polarity of the gate region, so the license is valid Current flows from the source through the path to the drain. The structure provides redundant full charge depletion when in the "off" state. Figure 25 also illustrates a typical prior art current flow, indicated by the dashed line 344, where the current flowing through the gate region 328 flows only directly below the FEM gate unit. The reason is that the known FEM unit configuration is a surface- 表面 inverted structure, and the device disclosed here is of the depletion type. The operating theory of the depletion device is similar to that of the junction FET. A solid line 346 illustrates the current flowing through the device of the present invention, and the current can flow through the junction 332 to the entire gate region. The memory early element formed according to the present invention can be arranged in a memory: cell array so that the gate line is perpendicular to the drain line. At a negative voltage,-乂 is applied to the gate electrode 340 (programming line) 'and at a positive voltage + Vp. When applied to the drain electrode 33o and the source 3: Z6 to ground and here | Vpll> | Vp0 丨, the FE is polarized with the negative charge of the lower electrode interface 348. This places the FEM gate unit 316 in a low conductivity state (see Fig. 26a). The writing process allows each memory transistor in the memory array to be nested independently of other memory cells in the array without disturbing other memory cells in the array. To write the FEM, the early element 316 '+ Vpi is applied to all the closed electrode 340, and the source electrode 338 and the drain electrode 342' of the memory cell are both at the ground potential. FE 320 is thus polarized in such a way that positive charges are located at the lower electrode interface 34′8 and negative charges are located at the upper electrode interface, surface 35 (see FIG. 20b). This makes the FEM gate unit 316 highly conductive. The threshold voltage of the FEM gate unit 316 is determined as follows: For a large array, the threshold voltage in the "1" state must be a small positive voltage, that is, 0.4 V to 0.8 V. -32- The standard of this paper is applicable to China National Standard (CNS) Α4 specification ((Please read the precautions on the back before filling in this page)

A7 409366 B7 V. Description of the invention (30) The threshold voltage of the "0" state must be greater than the supply voltage, that is, 3.3 V. The η ′ path layer is depleted by the P-type substrate and depleted by the extremely shallow ρ · surface layer and the gate bias. (Please read the precautions on the back before filling in this page) Can be displayed as a memory window equal to: 20 △ VT =-^ (2)

^ FE Here QfE is the residual charge and the ferroelectric capacitance of the free cell. During the reading operation, an electric calendar < Va which is not greater than the voltage of the head (that is, a voltage that can be changed in the memory content) is applied to the gate electrode and the drain electrode. As any electrode is biased with VaM, the contents of the memory unit are not disturbed, so the reading operation will not interfere with the memory contents of the memory unit. Because of this-there can be a charge between the long sides. Single transistor memory cell: The general ID of MFMS FET vs. Vg is illustrated in Figure 27. Figure 27a illustrates the ID vs. VG characteristics of a FEM unit with high-path doped ND. When the FEM gate unit is not charged, the center line is the ID vs. V0 curve. When the FEM unit is programmed to the "1" state, the threshold voltage of the FEM unit is negative. This is so even if V0 = 〇 V, a large 31-pole current can flow through the path area. This type of device is not suitable for large array applications. Printed by the Employees' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs Figure 27b illustrates the ID vs. VG characteristics of the FEM unit with low-channel doped ND. When the FEM unit is programmed to the "1" state, the threshold voltage is positive. When the gate is at ground potential, no current flows through the device. The large memory array of such a device has minimal standby leakage current. —A ferroelectric Pb5Ge30n film for MFMS application: Obviously lower ferroelectric capacitance results in higher memory window and lower programming voltage. Thicker films and lower core materials can result in lower ferroelectric capacitance; but the former -33- This paper size applies to the Chinese national standard ((:! '«:) six 4 specifications (210 > < 297 male 1) 409366 a? _____B7 V. Description of the invention (31) " Selection can increase the programming voltage. The oxide Pb5Ge3〇li film has extremely low er and medium Tc (178 ° C). Even the steady-state polarization of Pb5Ge3〇u film is far away. The polarization of PZT and SrBi2Ta209 films is lower than that of the PZT and SrBi2Ta2O9 films. However, the memory of the MFMS device controlled by PbsGesOu is closed. The body window is larger than the memory window of the latter two. Thus, the FEM memory unit and Its construction method. The fem gate unit can be constituted as a single transistor device or it can be constituted as a combination of Mos transistors. Although the present invention has not been disclosed as a specific example, it must be understood that it may not deviate from it as attached According to the patent application park of the invention, the structure and method of the invention are further modified. (Example 4) The ferroelectric memory (ΙΜΜ) unit of this example can be formed on a SOI (SIMOX) substrate, or Formed in the body silicon substrate. The description here will focus on the body Even though the FEM gate unit is formed on the substrate, but if used here, "shirt substrate" means an SOI substrate or a bulk silicon substrate. Some specific examples of Fem gate units must be understood. · Electric memory units are manufactured at the same time. So for the sake of clarity, the drawings do not explain the M0S transistor. "The Central Government Standards Bureau of the Ministry of Economic Affairs of the Industrial and Commercial Cooperatives Co., Ltd. Now refer to FIG. The example substrate 410 is a single crystal base and is made of bulk silicon. As illustrated in Figure 28, the substrate 41 has been partially etched as illustrated; ^ type, and some substrates are slightly doped to form an active region or device region 412. Provide the required background polarity. This example is the background polarity of the n-region, which is called the first type of conductive path. The active region 412 contains a silicon dioxide insulating region 414. As the industry knows well,- 34-k This paper size is in accordance with Chinese National Standard (CNS) Λ4 specification (210 × 297 public trips) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 409366 A7 _______B7 V. Description of the invention (32) As for the gate unit of the present invention, the cell is arranged in a vertical grid to form a memory array. The bulk CMOS substrate is used as an example to explain the manufacturing method. The initial steps are to manufacture η-well and P-dross structures. Separate these structures, and implant: provide threshold voltage adjustment to the transistor through ions. The substrate 41 of this specific example has been P-sand or P-dip. Photoresist is used to shield the wafer section, Secondly, the phosphorus ion is also referred to here as the first impurity doped at 30 keV to keV and implanted into the p_well at a dose of l.Pxio12 / sq. . Multiple implantation steps and / or thermal diffusion are required to obtain the optimal donor distribution for the n_layer. Photoresist was removed by stripping ginger. The implanted silicon layer can also be replaced by a selective epitaxial film that grows silicon to a thickness of 100 nm to 10,000 nm. _ Now refer to FIG. 29, followed by the formation of a p- · layer 1 6 D p-on the active region 412. The layer can be formed by implanting B or BF2 ions (herein referred to as a second type impurity replacement impurity) to the active region 412. . Shelf ions can be implanted at 3 keV to 10 keV, while BF2 ions can be implanted at 15 keV to 50 keV. In two cases, the ionic titers ranged from 5x10u / cm2 to ΐχΐ15 / cm2. Ions are thermally excited by annealing. The implanted ions will diffuse into the n-active region to form a p-n layer, which is referred to herein as a second type conductive path. The annealing is at 500. 〇 皇 丨〗 00. 〇 的 温度 进行 ·。 Temperature. _ At this point, the formation of FEM〒 units can begin. Referring now to FIG. 30, the FEM gate unit is generally indicated at 418 and includes a lower metal layer or electrode 42, a ferroelectric (FE) material 422, and an upper metal layer or electrode 424. The construction of the FEM gate unit 418 begins by depositing a lower electrode on the p-layer 416. The lower electrode 420 can be made of Pt or Ir, Ir02 or -35. The paper size is applicable to the Chinese national standard (CNS) Λ4 specification (210X297). Γ

U (Please read the notes on the back before filling this page) Order

• 1J Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 --- 87 --- --__ V. Description of Invention (33) ~

Made of Pt / Ir alloy or other suitable conductive material. Other suitable conductive barrier materials may also be used. In a preferred embodiment, the thickness of the electrode 420 is 20 nm to 100 nm. Next, the 'FE material is deposited by chemical vapor deposition (CVD). ] p E materials can be prepared for one of the following: Pb (Zr Ti) 〇3 (pzT), SrBi2Ta209 (SBT),

Pb5Ge3〇ii 'BaTi03' or LiNb03. The preferred compounds are listed in a preferred order as PbsGeWn, SBT, and PKT. Most of the experimental work in the field of FEM gate units is performed on ζ compounds. The FE material 422 is deposited to a thickness of 100 nm to 400 nm. _ / r ^ — * Then an upper electrode 424 is formed over the FE material »The upper electrode can be made of the same material as the lower electrode to a thickness of 20 nm to 200 nm. A photoresist is applied to the FEM gate unit, and the unit is etched to the appropriate configuration and size. It must be understood that the three layers of the FEM gate unit as shown need not be precisely aligned, as its shape may be formed by applying photoresist and engraving with masks with different geometries. However, for the sake of clarity, the FEM gate unit is illustrated as having a structure that adjoins the facing sidewalls. As shown in FIG. 31, the 1 ^ (^ layer 426 or other appropriate barrier insulation material is formed by CVD to protect the FEM gate unit. TiOx is etched to form a sidewall insulation layer of the gate electrode plant. Now referring to FIG. 32, it can be seen The active region 412 has been modified into a source region 428, a gate region 430, and a drain electrode 432. Each region is shielded by applying a photoresist across the active region 412, the p · layer 416, and the FEM gate unit 418. The region of the polar region 430 and the appropriate ion, also referred to as the third type doped impurity, are implanted in the rest of the active region 412 to form two n + layers. Here _ -36- a paper size applies Chinese national standards (CNS > Λ4 is now grid (2iOX * ^ 7 公 漦): 1 ~~ f Please read the notes on the back before filling in this page} Order

I A7 B7 409366 V. Description of the invention (34) (Please read the notes on the back before filling this page) It is called the third type conductive path, which will be used as the source region 428 and the drain region 432. Note the p-layer 416 Extending on the gate junction region 430 and partially on the drain junction region 432. In this case, suitable ion implantation can be performed at a better energy of about 50 keV, but 40 keV to 70 keV is acceptable, and arsenic ions are implanted at a dose of ΐχΐ015 / cm2 to 5xl015 / cm2. In addition, phosphorus ions can be implanted in the same dose range within the energy range of 30 keV-60 keV. Now refer to Figure 3 3 'Wafer by heat treatment ... and stimulate and diffuse the implanted ions, including the source region and the drain region And the lower electrode—. Plant ^ | 416iB * BF2 ion diffusion leads to the formation of a shallow p-n junction under the FEM gate unit 41S, which is a second type conductive path. The heat treatment temperature range is from 500 ° C to 110 ° C (range can passivate and diffuse the implanted ions. Then CVD forms a silicon dioxide layer 434 over the structure, or applies other passivation insulation. Now refer to In Figure 34, the FEM gate unit 418 is illustrated as a part of the FEM memory unit 436. The FEM memory unit includes the FEM gate unit 418 and the lower source, pathway, and non-electrode regions. The specific example includes a shallow layer formed under the Fem gate unit 418. The interface area 416 is a pn layer. The Central Standards Bureau of the Ministry of Economic Affairs has printed a FEM unit 436 for redundancy description, forming boring holes in the oxide layer 434 to receive the source electrode 43 8 and the gate electrode 440 and The anode electrode 44Ϊ2 is connected to an individual component. The drain electrode 442 may be connected to the drain area—432 and the ρ · η junction 416. Figure 3 3 illustrates a specific example of a special ferroelectric gate depletion type MIS transistor. When β is at zero gate voltage, the charge of the η-channel under the FEM gate unit is completely consumed. So the leakage current is very small. To maintain a small leakage current, any edge of the lower electrode 42 and the η + source or η + The distance between the edges of the drain region is indicated by "D". The paper is again applicable to the Chinese National Standard (CNS) A4 specification (210XW7 mm) printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 409366 a? -------- 'B7 V. Description of Invention (35) " Must be at least 50 nanometers to maintain a small leakage current. But with the increase, the series resistance of the memory cell also increases. Therefore, it is preferred that D is not less than 300 nanometers. Gate leakage current is made of platinum and p 'type. The contact of the silicon shallow junction 432 and the contact of platinum and ferroelectric materials determine the leakage current to be the gate electricity application at a very small to medium field strength. The potential barrier between the 〆 layer and the η-type dream is 0 8 eV to i 〇 …. This kind of large]% barrier barrier can make the ferroelectric material unpolarized, or the positive electrode of the ferroelectric material below the polarized charge, the n-type silicon path is completely depleted. When the ferroelectric material Because the negative charge of the + electrode is polarized, the threshold voltage of the memory transistor is small. This kind of memory charge property and the voltage change technology required by the programming unit will be described in detail later. The material cannot sustain high-temperature heat treatment, so source / drain ion implantation and annealing can deposit the gate under The electrode is completed. Now referring to FIGS. 3 and 5, an alternative specific example of the FEM unit is illustrated. The specific example includes two silicide layers 444 and 446 formed at the source and drain junction regions. The second compound layer is deposited on the insulating layer 434. Formed by CVE >. This structure and advantages are lower resistance to the source and drain regions. This increases the early memory and electrode currents. ≫ Specific examples of FEM cells formed on SOI substrate 448 Illustrated in Figure 3 6 ° Operation: The structure constructed according to the present invention is particularly important because the FEM gate unit located above the conductive path in the gate region can change the polarity of the gate region, allowing the effective current to flow from the source through the path to The drain, when in the "off" state, this structure provides a complete depletion of charge. When in the "on" state, the current flows through the entire path -38 " "1" This paper size applies to China National Standard (CMS) A4 specifications (2 丨 0 · 〆2? 7mm) f Please read the back Note refill this page)-Order

A 409366 A7 B7 V. Description of invention (36) area. The memory cell constructed according to the present invention can be placed in a memory cell array such that the gate line is perpendicular to the drain line. FEM gate unit 418, Shi Ya ^ is applied to all gate electrodes, while the source and drain electrodes of the memory unit are at ground potential. The FE 422 is thus polarized, so that the negative charge is located on the lower electrode 420 and the positive charge is located on the upper electrode 424 (see FIG. 10b). This causes the FEM gate unit 418 to become highly conductive. ® Negative voltage-VP4 is applied to the gate electrode (program .. planning line), and positive voltage + vpQ is applied to the drain, and the source is grounded and here, FE & — ＋ Positive charge bias on the lower electrode 420 Into. This causes the feM gate unit 418 to become low-conducting (see FIG. 37a). The writing process allows each memory transistor of the memory array to be nested independently of the other memory cells in the array without disturbing the programming of other memory cells in the array. The threshold voltage of the FEM gate early element 418 is determined as follows: For large arrays, the threshold voltage in the "1" state must be positive, that is, 0 4 V to 0.8 V. The voltage of Γ 〇 ″ must be greater than the supply voltage, which is 3.3 V. The if-via layer is depleted by the p-type substrate junction and by the very shallow p-surface and gate bias. The memory window shows that it is equal to: 2? Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ΔΥ- (3)

CPS Here Qpe is the residual charge and CFE is the K capacitor of the gate unit. The spatial avoidance of the ιΓ region of the P + M junction is about 0.3 microns when the impurity density of the n-region is i 0xi〇1S / cm3. Obviously, if the thickness of the n_channel layer is small and the interference is small, the threshold voltage of the “1” state can be positive. Threshold voltage can be obtained through the passage layer 39 This paper size is applicable to the Chinese national standard {CNS) Λ4 specification (210 X 297 public epidemic) r 409366 A7 V. Description of the invention (37) and the impurity density and thickness of p 'surface layer, permittivity and Adjustment of the residual charge of the ferroelectric capacitor. During the reading operation, a voltage not greater than the coercive voltage (that is, the voltage that changes the memory content) is applied to the gate electrode 'and the drain electrode: electrode. When the electrode is biased by VJu, the memory list has no content and is not disturbed, so the reading operation will not disturb the memory content of the memory unit. Therefore, long-term charge can be maintained. Single transistor memory cell: MFMOS FETi-general ID vs. VG mapping. Figure 38a illustrates the VG characteristics of the 10-phase mouth of a FEM unit with a high-channel doped ND. When the FEM gate unit is not charged, the center line is ID relative to the V o line. When the program of the FEM unit is “1”, the threshold voltage of the FEM unit is negative. Therefore, even if V G = 0, a large set current flows through the path areaa. This device is not suitable for large array applications. Figure 38b illustrates the ID vs. VG characteristics of a FEM unit with low-channel doped ND. When the FEM unit is programmed to the Γ 1 ″ state, the threshold voltage is positive. When the gate electrode is at ground potential, no current flows through the device. The large scale of such devices: Memories arrays have minimal standby leakage currents and do not need to be updated frequently. Ferroelectric Pb5Ge3Ou film for MFMOS: Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). Obviously lower ferroelectric capacitance results in higher memory window and lower program voltage. Thicker films and lower er materials can lead to ferroelectric capacitance; but if the ferroelectric exchange domain is clearly defined, the former option can increase the programming voltage. T Common oxide ferroelectric materials have higher er and T ... oxides 135 (^ 3011 film has extremely low er and medium T. (178 ° C). Table 2 compares the memory window of MFMOS device with Pb5Ge30 „, ferroelectric gate of PZT and SrBi2Ta209 film-40-^ 'This paper size is applicable Chinese National Standard (CNS) Λ4 specification (210X297 mm) 409366 A7 B7 V. Description of invention (38) pole. Even though the steady-state polarization of Pb5Ge3On film is much lower than the steady-state polarization of PZT and SrBi2Ta209 film, Pb5Ge3On The memory window of the gate-controlled MFMOS device is still larger than the others, because it is low. 'Table 2: Memory window of MFMOS devices with various ferroelectric materials Ferroelectric Pb (Zr, Ti) 03 SrBi2Ta209 Pbs Ge3 011 Γ (μϋ / οηι2) X 15 7 3.5 1000 280 35 dFerir. (Angstrom) 2000 2Θ00 2000 vdeo (V) 3.14 4.39 6.87 Pr * (μΟ / οιη2) When Vd0p = O.5V 2.4 0.8 0.25 Memory window 2? RVC ^ (V) 1.08 '1.29 3.23

The competition state Vde "is set to 0.5V printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before writing this page). This reveals the FEM memory unit and its composition method. The FEM gate unit can be composed as A single transistor device may be formed with the related MOS transistor. Although the preferred specific examples of the present invention have been disclosed, it must be understood that the scope of the present invention and the method can be made without departing from the scope of the invention as defined by the accompanying patent application. (Example 5) As mentioned above, the present invention is a method for manufacturing an MFMOS memory unit. The MFMOS memory unit includes a ferroelectric (FE) capacitor or a FEM gate unit on top of the MOS capacitor. The two devices are here Collectively referred to as a stacking gate unit. In the specific example of the present invention, the area of the MOS capacitor is larger than the surface of the ferroelectric capacitor * 41 · This paper size applies to the Chinese National Standard (CNS) A4 specification (2IO × 297 Gongchu) '' Central Bureau of Standards, Ministry of Economic Affairs Printed by the employee consumer cooperative 409366 A7 --------. B7 V. Description of the invention (39) ^ ~ 'product, so as to improve the coupling efficiency and reduce the programming voltage of the device. Narration f a In the system, a second electric body is formed along the side of the stacked Mos & FE capacitor, and it includes a ferroelectric capacitor on top of the Mos capacitor. Among them, the electric capacitor and the MOS capacitor have the same cross section .: This configuration You can obtain # -type single-units and compare higher programming voltages of different size structures (also known as off-position gate ferroelectric cells). Another specific example includes 1 ^ 〇3 electric moxibustion stacked on FE capacitors, The two types of capacitors have the same size footprint. 堆叠 The stacked ferroelectric memory gate unit of the present invention can be formed on the spj base, or the bulk silicon base g can be formed in the p-well. As used herein, "silicon The substrate J represents an SOI substrate, a bulk silicon substrate, or any other type of substrate that contains debris as a component and is suitable for use in the present invention. When a bulk substrate is used, the substrate is an n 'type. The initial steps are to manufacture n-wells and p-wells ... Isolate the two structures and implant the appropriate ions to adjust the threshold voltage of the transistor. "When using a SOI substrate, there is no need to form an n-well or a p-well.-Referring now to Figure 39, the silicon substrate is illustrated at 51 °. In a preferred embodiment, the substrate 5 10 is a single crystal substrate, which is made of bulk silicon. As shown in Figure 39, the substrate 510 is made of η · silicon. The p-well 512 can be implanted with B or BF2 ions on the surface of the substrate, and then at 95 (TC The thermal diffusion step is performed to 120 ° C for 1 to 4 hours to form. Boron ions can be implanted in amounts of 3 keV to 10 keV, and BF2 ions can be implanted in amounts of 1 keV to 50 keV. —The ion concentration of the two cases is in the range of ixio12 / cm2 to lxio14 / cm2. To isolate the device, the insulating region 514 formed by silicon dioxide is grown on the substrate before the well 512 is formed. As everyone in the industry knows, many of this area are formed " 42--(Please read the precautions on the back before filling this page) 1ϋ t-shirt --- The size of the paper is applicable to the Chinese National Standard (CNS) Λ4 specifications (210X 297 at public expense)

I Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Consumer Cooperatives ^ 09366 A7 B7 V. Description of the invention (40) on the surface of the silicon wafer. For the structure of the present invention, the unit is a memory array formed by a gate 2 pair of drain and a ρ · well vertical grid. Now, a single-transistor memory cell of the present invention will be described with reference to FIG. 40 '. As shown in FIG. 40, the active region 512 is modified to include two regions 518 and 518, which are particularly used as the source and drain of the memory cell. The Yu-wei via region 52o, referred to herein as the first type conductive via, remains on the substrate 51o. The source region 516 and the drain region 518 are formed by implanting appropriate ions (herein referred to as a second-type doped impurity) into the active region 512 to form two regions, and are also referred to herein as second-type conductive path formation. In this case, a proper ion implantation may be a preferred energy of about 50 keV, but implantation of 40 keV to 80 keV can accept arsenic ions in a dose range of 5 cm / cm to 5 x 1015 / cm2. In addition, phosphorus ions can be implanted in the same dose range from 20 keV to 50 keV. The MOS capacitor 522 is formed by growing a thin layer of thermal oxide 524 on the p_channel 520 after being appropriately shielded. In a preferred embodiment, the thickness of the layer 524 is 3 nm to 10 nm. The selective n + polycrystalline silicon layer 524 is formed by CVD to a thickness of 100 nm to 300 nm to complete the MOS capacitor 522. n + polycrystalline silicon acts as a buffer layer to relieve the stress between the lower electrode of the FEM capacitor and the underlying oxide. At this time, the formation of the FEM capacitor gate unit is started. The FEM gate element 528 includes a lower metal layer or electrode 53, a ferroelectric (FE) material I32, and an upper metal layer or electrode 534. The FEM gate unit 528 is formed by depositing a lower electrode on the MOS capacitor 522. The lower electrode 530 may be made of Pt, Ir, Ir02 or Pt / Ir alloy or other suitable conductive materials. In the preferred embodiment, the thickness of the metal is 20 nm to 100 nm-43. The paper size is applicable to China National Standards (CNS) M specifications (210X297 mm) f '--- 1 1 ^ —J ^ I ^^ ^ 1 F: ·-. ^ -N (Please read the notes on the back before filling this page)

1T A7 409366 B7 V. Description of the invention (41) Micron. The lower electrode 530 and the n + polycrystalline silicon layer constitute an upper electrode of the MOS capacitor 522 when used. (Please read the notes on the back before filling out this page.) Second, FE materials are deposited by chemical vapor deposition (CVD). The FE material can be any of the following: Pb (Zr, Ti) 03 (PZT), SrBi2Ta209 (SBT), PbsGegOu, BaTi03, LiNb03, or other suitable ferroelectric materials. The preferred compounds are arranged in a preferred order as Pb5Ge3On, SBT and PZT. Most of the experimental work in the field of FEM brake units is performed on PZT compounds. FE material 532 is deposited to a thickness of 50 nm to 400 nm. .. An upper electrode 534 is then formed on the FE material. The upper electrode can be made of the same material as the lower electrode to a thickness of 20 nm to 200 nm. A stacked gate unit includes a FEM gate unit 528 and a MOS capacitor 522. This specific example shows the characteristics of an over-position FEM gate unit, where the FEM gate 'unit covers a smaller area than the full surface area of the MOS capacitor. The 40 structure is completed by depositing a suitable insulating material such as TiOx, Si3N4 or other appropriate barrier insulating materials on the memory cell. A thick layer of interlayer dielectric material is formed to obtain proper contact between the source region, the gate region, and the drain region. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economics 覌 Referring to Figures 41a and 41b, the structure and structure of two types of transistor memory units with stacked gate units will be described. In this example, the structure is formed on the second substrate 540 on which the oxide layer 542 has been formed. The cathode, drain, and gate regions can be formed at this step of the method or formed at the ^^ service. All in all, it is preferable to deposit the n + polycrystalline silicon layer 544 by CVD, which together with the oxide layer 542 forms the MOS capacitor 546. A lower metal layer or electrode 548 is then formed on the n + polycrystalline silicon layer, 544, as previously described. The top plan view of the lower metal layer 548 is illustrated in Figure 41b. 0 -44- This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210 乂 297 public 犮) '' Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economy 409366 A7 _________ · B7 V. Description of the invention (42) In the next step, as described in the specific example of a single transistor, a ferroelectric material 550 is deposited on the lower electrode 5 48, and then an upper metal layer 5 52 is formed. The lower metal layer 548 and the upper metal The top plan view of layer 552 is shown in Figure 42b. The upper and lower metal layers and the FE material constitute the FEM gate 554. The photoresist is applied and the lower electrode 548 and the η + polycrystalline silicon layer 544 are etched to obtain the structure shown in Figure 43 The structure shown in FIG. 43 includes a second transistor 556 which includes a portion of the oxide layer 542; an η + polycrystalline silicon layer 544, and a lower metal layer 548. These components are marked with an "apostrophe". Previously applied .. The photoresist is stripped and removed, and a new photoresist is applied. As described above, the second type of impurities are implanted and the shape of the η + region 558 '560' 562 shown in Figure 44 is referred to herein as the second type of conductive `` path. Now refer to Figure 4 5. The original photoresist is peeled off, and the wafer is properly insulated. Layer passivation, applying new photoresistance to open contact holes and defining the first interconnecting metal 'results in the upper metal layer 552 being electrically bonded to the metal layer 548. This configuration has the advantage of low leakage current. The device leakage current is controlled by M0S Transistor current limitation. 'The next specific example of the present invention starts again from the aforementioned silicon substrate. Referring to Figure 46, an oxide layer 572 is formed above the p-well 570. Additional layers are sequentially deposited thereon, including the n + polycrystalline silicon layer 574, below Metal layer 576, FE layer 5 78 and upper metal layer 580. The photoresist is applied and the structure is etched. The structure shown in Figure 47 is obtained. It includes a MOS capacitor 582 and an FPM gate unit or a capacitor 584 formed as a stacked gate unit. 585. At this time, a layer of insulating material such as Ding O 3 £ or other appropriate insulating material can be applied with a protective iron. Then, n + ions are implanted to form n + source region 5 86 and n + drain region 5 88. The remaining ρΓ material It is stated that the gate access is provided at 590. ___- 45 -_, _ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public epidemic): 'r (Please read the precautions on the back before filling in two I'), -= θ

-JJ 409366 A7 B7 V. Description of the Invention (43) Now referring to FIG. 49, the final structure will be described with an insulating layer 592 for positioning. It includes a source electrode 594, a gate electrode 596, and a drain electrode 598. This specific example provides a very small unit "This device is particularly suitable for VLSI memory applications. Programming to a high threshold voltage state: Figure 50 illustrates the P-E hysteresis loop of the ferroelectric material used for the memory cell here. P r is the polarization value of the ferroelectric material. Pr0 is a negative polarity saturation polarization. Pr00 is the polarization of the ferroelectric material after the device has been programmed to a high threshold-electricity. After the pressure is released, the device is released. Pr! Is positive-polarity and partial-polarity; and Pr10 is the device — · The polarization of the ferroelectric material that has been loosened and broken in the device after it has been programmed to a low threshold voltage state. The electrical distribution of the device constructed according to the present invention is illustrated in Fig. 51, where Fig. 51a illustrates the charge distribution of the device program planned to the "0" state. And Fig. 51b illustrates the charge distribution when the device program is planned to be "1". When you want to program a large positive threshold voltage to program the memory transistor to the Γ ″ state, the device is not conductive at normal operating voltage, and a negative voltage is applied to the control gate. As a result, the charge distribution shown in Figure 5ja is shown. Poson (poison ) The formula is: (Please read the notes on the back before filling this page) * JL. --- ά'Ϋ Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ctc: ε〇χ — [c (x) c ( x = Τοχ)] + c (x = Tax) ε〇χ εη (4) points obtained twice

Pr〇qp si Cfe (5) -46 The paper size is applicable to Chinese National Standard (CNS) A4 (2 丨 OX 297 mm) 409366 A7 B7 V. Description of the invention (44 PrQ is shown here in Figure 5 0 Dust across ferroelectric capacitors is:

F

Pr〇qp Cf £ (6) So the programming voltage is: 阈 The threshold * pressure after programming is:

Vw = Vfs + Hf〆 ^ < r > FP £ Stcl ^ ^. + Pr〇〇 C〇.x

Cfe (8) Here Pr00 is the polarization of the ferroelectric material after the program planning device is relaxed to a high threshold voltage. Program to Low Threshold Voltage State: • To program the memory to a low threshold voltage, which is the "1" state, a positive voltage v is applied to the gate and a negative voltage VD1 is applied to the non-pole and p-well. When fabricated on a SOI substrate, a p-well is not required. The source is at ground potential. The charge distribution is plotted in Figure 51be. The Posen equation is:-j --------—— (Please read the precautions on the back before filling this page) -5 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs --- qN ^ [U (x) U (^ v)] ^ ~ A ^ qn [c (x = W) c (x = W ^ T〇x)] ^ [S ^^ qn] of PrL = · ^)) Dx: es / integral formula (9) obtained twice:

~ + 2 4 + ί ^, ^^ Zη y〇i C〇x CfE (10) 47- The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) r 409366 5. Description of the invention (45) Formula (10) Rewritten as: A7 B7 yn = vFB + 2 < pf ί-f ^ Sr,: v7fyr ^ ^ (v -fq gy Νλ φΡ „+ qrt] Pr,

Cf £ Ύ (H) The voltage drop from the surface 顚 to the top electrode of the ferroelectric capacitor is: ε <;,, s: si Ν ^ φ ^ Λ-qn] Pr,

Cox

C η (12) The voltage drop of the ferroelectric capacitor is y fe so the supply voltage is:

Cfb (13) f, please read the notes on the back first. Please write this page} V ^ V0, -VF8 ^ -V ^ 1 ^ (14). The threshold voltage is:, [4〇7 ^ ~ J7f. And . H Pr, 〇νΤί ^ ν ^ 2φ ^ — ^ F £ (15) Printed by the I-Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. The program is planned to a low threshold voltage. • After easing him. PrlQ is a lighter charge. In this way, β increases the density of the passage through (1)! N >. '(2) reducing ferroelectric capacitance by selecting lower dielectric constant materials and / or increasing ferroelectric film thickness, and (3) increasing gate oxide capacitance by using thinner thermal oxide layer Cox, the threshold voltage of the device in the "0" state can be greater than 0.0V. This is a necessary condition for a single transistor RAM VLSI array. The results clearly indicate that when the oxide 48-this paper rule is applied to the Chinese National Standard (CNS) Λ4 specification (2IOX297 mm) 4093G6 Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (46) " — Capacitor When it is high, the programming voltage becomes smaller. Under a variety of polarization conditions, the programmed voltage and threshold voltage of the device can be calculated by the above formula. It is shown in Table 3. Here, the programmed voltage and the channel impurity density are adjusted to obtain the “1” state threshold voltage as Vt / = 〇 6, v. During the programming period, the polarization charge is assumed to be 36% higher than the steady-state polarization. It is further assumed that the thickness of the ferroelectric material is 300 nm and the capacitance is 2.9 × 10-7 F / cm2. The voltage drop across the ferroelectric material during programming was 3 V. The thicknesses of the two gate oxides, 5 nm and 6 nm, have been evaluated. The memory window △ ▽ ^ is shown in the bottom column of Table 3 and an example is shown in Figure 5 2 / _ Table 3 ^ ox = T〇x = 6nm prc〇 = Prt doped Vp [• vP〇 doped I VP | Vp〇AVth 0.50 5,70 -4.70 1.23 I 5.23 -3.53 ^ 05 0,75 6.00 5.95 -4.4-5 5.22 '5.71 -3.09; 78 1.00 13.59 6.20 -4-.20 11.97 6.15 -2.65 '50 1.25 24.50 6.45 -3.95 21.48 6.59 -2.21 c 73 1.50 38.44 6,70 '3.70 33.76 7.03 -1.78 V 95 1,75 55,50 6.95 -3.45 48.79 7Λ6 -1.34 *, 68 2.00 75,69 7.20 -3.20 66.59 7.90 -0.90 I 2.25 99.00 7.45 1 -2.95 'B7.U 8.34 -0.46 1. 13— 2.50 125.44 7.70 1 -2.70 no. 8.78 -0.03 I -'S5 Referring now to Figure 52a, Illustrate ID # VG mapping of prior art devices. Line 5100 indicates that Vtl is less than zero and Vt0 is positive, which is Shen. A structure with this characteristic requires at least two devices (a memory transistor and a common transistor) for the RAM array, and acting on a single transistor RAM array will require a relatively high programming voltage. Figure 52b illustrates the Γ 1 ″ threshold voltage of the device formed according to the method of the present invention is _-49-]. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 cm) (Please read the precautions on the back first) (Fill in this page again)

Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 409366 A7 _______ B7_ V. Description of the Invention (47) Line 5104 indicates ’and“ 〇 ”threshold voltage is indicated by line 5106. In this way, the FEM memory unit and its constitution method are revealed. Although the preferred specific examples of the present invention have been disclosed, it must be understood that the structure and method of the present invention can be further changed without departing from the scope of the present invention as defined in the appended patent application scope. (Example 6) _ The ferroelectric memory (FEM) unit of this example is formed on a SOI (SIMOX) substrate, or it may be formed on a bulk silicon substrate. The description here will focus on the / em gate unit formed by the bulk silicon substrate. Referring now to Fig. 5 3 'silicon substrate is illustrated at 61 °. In a more specific example, the substrate 610 is a single crystal substrate and is made of bulk silicon. Other real examples can be formed on the soi substrate. As used herein, "silicon substrate" means the bulk silicon substrate or SOI substrate or any other suitable-silicon-based substrate. As shown in FIG. 5A, the p-substrate 610 contains a first-type doped impurity, which is boron or a boron compound, and has a concentration of about 1.0 × 10 15 / cm 3 to 50 M015 / cm 3. The shallow Γ-type layer 612 (well structure) is also referred to herein as a second-type conductive path, which contains a second-type doped impurity and is then formed in a square shape under the gate region by implanting phosphorus or arsenic. The ion energy is 10 keV to 50 keV and the dose is ΐ.οχίο! 2 / cm 2 to l.OxlO13 / cm 2. The p-type hard extremely shallow layer i 4 (sub-well structure) is formed in the shallow n_-type layer 12 and contains the third type dopant ▼ The n-type soil guide is implanted with BF2! Layer on top. It can range from 10 keV to 40 keV and the dose is in the range of 50 × 1010 / cm2 to 5.0 × 10 / cm2. This layer is referred to herein as a third type conductive path. At this point, the formation of the FEM gate unit can begin. The FEM brake unit is roughly labeled as "50-Silver Standard Applicable Standard (CNS) ΛEG (2 similar to 297 public hair)-------t--^^ 1 ·---(please first hear Jing (Notes on the back then fill out this page)

I Ding,-'° 409366 A7 B7 V. Description of the invention (48) 616 and includes a lower metal layer or electrode 618, a ferroelectric (FE) material 620 and an upper metal layer or electrode 622. The composition of the FEM gate unit 616 begins by depositing the lower electrode 618 and the p · layer 614. The lower electrode 618 may be made of Ir or Ir / Ir02 alloy or Pt / Ir alloy or other suitable conductive material. In a preferred embodiment, the thickness of the metal is 20 nanometers to 100 nanometers. Secondly, after proper masking, the FE material is deposited by chemical vapor deposition (CVD). The FE material can be any of the following: Pb (Zr, Ti) 03 (PZT), SrBi2Ta209 (SBT), Pb5Ge3On, BaTi03, or LiNb03. In a preferred order, the preferred compounds are Pb5Ge30, SgT, and PZT. Most of the experimental work in the field of FEM gate units is performed on PZT compounds. FE material 620 is deposited to a thickness of 50 nm to 400 nm. Then, in The FE material is shaped to form an upper electrode 622. The upper electrode may be made of Pt, Pt / Ir alloy, Pt / Ir02 alloy or other suitable material to a thickness of 20 nm to 200 nm. A photoresist is applied to the FEM gate unit, and then The unit is etched into a proper configuration and size. It must be understood that the three layers of the FEM gate unit as shown do not need to be precisely aligned, because the shape can be formed by applying photoresist and etching with masks with different geometries. But for clarity See, the FEM gate unit is illustrated as having a structure adjacent to the opposite side wall. Now the 〆 substrate 610 is implanted. The appropriate ion # is also called a fourth type doped impurity to form two n + layers, which is also called the fourth. Type conductive paths, which are / are source regions 624 and ί and pole regions 626. In this case, appropriate ion implantation may be better than about 50 keV, but 40 keV to 70 keV is also acceptable and lxlO15 / Cm2 to 5x1015 / cm2 Implantation of arsenic ions. * 51-This paper size is applicable to China National Standard (CNS) A4 specification (2〗 0X297):> '(11 ^->-I / 1 / -1 ^^ 1 ^ ϋ > n (Please read the notes on the back before filling this page) -1 ° Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 409366 ^ -------^ _____ V. Description of the Invention (49) · In addition Phosphorus ions can be implanted at the same dosage range in the energy range of 30 keV- 60 keV. The wafer is heated to excite and diffuse the implanted ions in the source and drain regions. The temperature range of the heat treatment is 500Ό to 1100β. 〇 Excitation and diffusion of implanted ions.

TiOx'Si3N4 or other appropriate barrier insulating material layer 630 is formed by CVD to protect the FEM gate unit, resulting in the formation of an FE memory unit 632. To complete the description of the FEM unit 632, a hole is formed in the green layer 630 to accommodate the word line (WL) (gate) electrode 634 and bit line (BL), and the electrode 636 is connected to its individual component. The source 624 is grounded 640. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Figure 5 3 illustrates a specific example of a ferroelectric gate depleted MFMS transistor. At zero gate voltage, the charge in the n_ path below the FEM gate unit is completely depleted. Thus, the leakage current is extremely small. To maintain a small leakage current, the distance between any edge of the power down 618 and the n + source and n + drain regions 626 has a marginal margin of "626. The DJ indicates that it must be at least 50 nm. However, the small leakage current is maintained. With the increase of D, the series resistance of the memory cell also increases. Therefore, it is preferably 0 or less than 300 nm. The potential barrier layer between the third type p-conductive layer 14 and the second type ^ conductive layer 612 is about 0.9 eV. A potential barrier of this size can completely deplete the n-type hair path when the ferroelectric material is not polarized. When the ferroelectric material 62 ° is polarized with a positive charge adjacent to the lower electrode 618 ^, The threshold voltage is small. When the ferroelectric material 620 is polarized with the negative charge of the lower electrode 6 丨 8, the threshold voltage of the memory transistor is extremely large. The nature of the charge of this memory and the amount of voltage required to change the programming unit In addition, if the ferroelectric material cannot tolerate high temperature heat treatment, the source / drain -52-this paper size applies to China National Standard (CNS) A4 specification (2! 0X297 public waste) 409366 A7 Ministry of Economy Printed by the Consumer Standards Cooperative of the Central Bureau of Standards. B7 V. Invention Description (50) Ion Implantation The annealing and annealing can be completed before the gate electrode is deposited. Operation: The structure constructed according to the present invention is particularly effective, because the MG gate unit located above the conductive path in the gate region can change the polarity of the gate region. The source flows through the path to the drain. The structure provides full charge depletion in the "off" condition. Depletion devices operate similarly to interface FETs. The outline of the IMFMS VT 10 vs. VG is illustrated in Figure 54. Figure 54a illustrates the symmetric FEM cell ilD, VG characteristics. When the FEM unit is not charged, the center line is the curve of Id versus V0, where Pr = 0. When the FEM unit program is planned to be "1", the threshold voltage of the FEM unit is negative. Thus, even if VG = 0V, a large drain current can flow through the path region. This device is not suitable for large array applications. -Figure 54b illustrates one of the asymmetric FEM units of the present invention. For VG characteristics. When the program plan is "1", the threshold voltage of the FEM unit is positive. When the gate is at ground potential, no current flows through the device. The large memory array of such a device can have minimal standby leakage current. The asymmetrically polarized ferroelectric memory transistor unit of the present invention can be applied to MFMS units and MFMOS units to provide low leakage current, high speed, and very large memory arrays. Low leakage current can be achieved for the "1" state and the "0" 'state' for a positive threshold voltage. High-speed read and write can be achieved by increasing the driving current and reducing the path capacitance. Because the electron mobility is much higher than the pore mobility, ιΓ channel memory devices are better for high-speed operations. Referring now to Fig. 5, Jiang et al. "High-density non-volatile ferroelectric SrBi2Ta20" innovative technology of i-memory body ", 1996 VLSI Technology Seminar« 53 ** This paper size applies the Chinese National Standard (CNS) A4 specification ( 210X297 mm) — · 々r! 0 ^---I--JAI (Read the precautions before reading and then fill out the tile)

'1T Seoul

J 409366 B7__ V. Introduction to the Invention (S1), Honolulu, June 11-1, 1996, page 26, describes the use of indium instead of platinum as the lower electrode of ferroelectric memory capacitors to achieve improved performance. As illustrated in Figure 5-5, the hysteresis loop measured for a 100 kHz single-click pulse layer on a SrBi2Ta209 (SBT) capacitor with different lower electrodes is described. The lower electrode in Fig. 55a is Pt / Ti〇2; the lower electrode in Fig. 551> is irO2; and the lower electrode in Fig. 55c is pure Ir. The residual polarization ρNν was measured 10 seconds after the capacitor was written. As shown in Figure 55c, the Pt / SBT / Ir capacitor shows a great depolarization charge in the positive polarization, and the depolarization of the negative polarization capacitor is extremely small. In order to obtain the positive 11 state (highly conductive state) threshold voltage device, it must have a small positively polarized charge at the lower ferroelectric / electrode interface, as shown in Figure 56a. To maintain a large memory window, a large polarized negative charge is also required at the lower ferroelectric / electrode interface, as shown in Figure 56b. This can be achieved with a Pt / SBT / Ir semiconductor structure. The "steady state" 1 J state has a polarized charge of about 10 μ (: / £; ιη2, while the steady state "0 J, the politely polarized charge is about -2 pC / cin2 〇 to 0.3 with a dielectric constant of 280 For micron SBT films, the corresponding threshold voltage migration is 12 ″ v and 2/42 V. By adjusting the channel doping density, the threshold voltage is reached at about 3 V at 0 ferroelectric polarization, and VT1 and VT can be obtained respectively. Approximately 0.6 volts and 15 volts, as shown in Figure 54b. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) This ferroelectric memory device can be used for Low voltage, high luxury and high-speed applications. The memory cell is placed in the p-well 610 as shown in Figure 5-7. Figure 57 illustrates the nine-cell memory array. The word scales are labeled WL1, WL2, and WL3. The element line or drain line is marked as BLI, BL2 and BL3. The source area and substrate of all transistors are grounded. The source, word line, and bit line are independently connected to peripheral circuits, as shown in Figure 5-7. Memory The array is applied with a positive voltage of Vpp to the word line -54 ** · * This paper size is applicable to the Chinese national standard (<:?) Such as said (210 \ 297 mm Printed by 409366 A7 'B7 of the Ministry of Economic Affairs, Zhunxun Cooperative Consumer Cooperative V. Invention Description (52) (Gate) and the bit line is grounded and planned by the block program as "" (highly conductive). Individual memory cells in the program plan are in the "0" (low conductivity) state. The negative program plan voltage -Vpp is applied to the word line and the positive program plan voltage Vpp is applied to the bit line. This results in that only one cell has a bias voltage at the gate terminal ^ ^ And Yu Jiji + Vpp. This memory cell is the only cell in the entire array that will be nested in the "0" state. Many electrode groups can be observed to relax asymmetric polarization polarization. In addition, it can be used in any kind of ferroelectric film and Observation of any kind of ferroelectric gate structure. Observed. The asymmetry polarization relaxation mechanism is both complex and sensitive to the processing conditions. Therefore, it is required in the preferred embodiment of the present invention that the 'asymmetry polarization relaxation technique is used. Manufacture of a single transistor memory cell controlled by a ferroelectric gate. The threshold electric dust of the MM gate unit 616 is determined as follows: For a large array, the threshold voltage in the "1 J state must be small positive, that is, 04 V to 08 V The threshold of "〇" state The pressure must be greater than the supply voltage, that is, the 3.3 va n-channel layer is depleted by the p-type substrate junction and depleted by the extremely shallow p-surface layer and gate. The memory window is displayed as: ΔΥί Here Qfe is the residual charge and Cfe It is the ferroelectric capacitance of the gate unit. During the reading operation, a voltage Va that is not greater than the voltage of the head (that is, the voltage that changes the content of the memory) is applied to the gate electrode of the gate electrode. When the pole is biased by VaM, Memory for a single day; the content is not disturbed, so the reading operation will not interfere with the memory content of any memory unit. Therefore, it is possible to obtain a long-term retention of Xinghe. Rent -55 This paper is compatible with Chinese National Standard (CNS) A4 specifications (21〇 > < 297 Gongchu (Please read the precautions on the back first and discard this page)

(16)

Cfe

Claims (1)

409366 VI. Application scope 1 · = A method for forming a semiconductor structure with a ferroelectric memory (FEM) gate unit on a single crystal silicon substrate, which is characterized by: forming a silicon device region for the FEM gate unit; Impurities are implanted in the silicon device area to form the first; type conductive paths are used as the source junction area and the drain junction area; the insulating boundary surrounding the device area is etched; and the FEM gate unit on the silicon gas filling area is formed — A gate junction area is located between the source junction area and the drain junction area; a conductive path precursor slide is formed in the gate junction area; and a FBM gate unit sharp junction area is deposited, which includes & amp Build-up metal layer 'a layer of FE layer and a layer of upper metal layer, wherein the size of the FEM gate unit on the gate junction area is any edge of the FEM gate unit with a source junction area and a drain junction area; The distance between the edges is "D", where the factory diameter J is about 50 nm to 300 μm. 2. The method according to item [patent for patent application], wherein the formation of the conductive path 'precursor includes 3 keV to 10] ^ or 15 keVi50keV2 energy range' and ΙχΙΟ11 / cm2 to 1χ1〇13 / square A dose of centimeters is implanted into a precursor selected from the group consisting of 3 or 3! 72 dopants to form a conductive pathway ". 3. The method according to item 1. of the patent application park", which is included in about 500 to The junction is annealed at a temperature of 1100 C, and the scandium ions diffuse from the lower metal layer into the gate junction area to form a conductive path precursor. 4. If the scope of patent application is the first! Method, wherein the deposited FEM gate sheet does not include a deposition thickness of about 20 亳 micrometers to 100 nanometers. _ _ 56-^ Zhang Zhang scales apply ^ National Standards (CNS) A4 specifications (2丨 0X297 mm) -Γ— It- hi n--It J \ ~-1 (Please read the precautions of the memorandum before writing the copy y} -Order. Printed by the Consumers' Cooperatives of the Bureau of Loss and Standards of the Ministry of Economic Affairs I Γ A8 BS C8 D8 5. Printed 409366 by the Central Bureau of Guidance Bureau of the Ministry of Economic Affairs, applying for a metal layer under the scope of the patent; depositing a thickness of about 100 nm to 400 nm selected from the group including Pb (Zr, Ti). 3 (PZT), SrBi2Ta209 (SBT), PhGegOu, BaTi03, and LiNb03; FE layer; and deposited with a thickness of 20 nm to 100 nm, selected from Pt, Ir and Pt / Ir alloys The material is made of an upper metal layer. For example, the method of patent application Fanyuan No. 1, wherein the implanted impurity comprises a region selected from an ion doped device including god and phosphorus, and the energy is about 40 keV to 70 keV. Implants and scales implanted at about 30 keV to 60 keV with an ion implantation dose of about 2x1 p: 15 / cm2 5xl013 / cm2. — The method of patent application No. 1 which includes depositing a layer of TiOx on the FEM cell: a kind of ferroelectric memory (FEM) gate formed on a single crystal silicon substrate. The method of semiconductor structure is characterized by comprising: forming a silicon device region to the FEM gate unit; implanting dopant impurities into the device region to form a first type conductive path for use as a source junction region and a drain junction region; etching The insulation boundary around the device area; forming a gate-free interface area between the source interface area and the drain interface area for the FEM gate unit on the device area; formed in the gate interface area, and a conductive path precursor; And depositing a FEM gate unit on the gate junction area, including depositing a lower metal layer made of a material selected from materials including pt, Ir & pt / Ir alloy with a thickness of about 20 nm to 100 nm, and depositing a thickness About 100 nanometers 57- This paper size is applicable to the Chinese National Standard (CMS) A4 specification (2〗 0X297) ((Please read the precautions on the back before filling in the poverty) 8. 10 · 11 · Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 12- 409366 A8 B8 C8 DS Patent application scope; selected from 40nm to Pb (Zr, Ti) 03 (PZΤ), SrBi2Ta209 (SBT), PbsGesO " 'BaTi〇3, and LiNb03 materials made of FE layer, and deposition thickness of 20nm to loonm. Choice. From materials including Pt, Ir and Pt / Ir alloy, made The upper metal layer is formed; wherein the FEM gate unit is formed on the gate junction area so that any edge of the FEM EMearly element has a source junction area and a non-electrode junction area. The distance between the edges is "D", here "D" is about 50 nm to 300 nm. If you apply for the method of item 7 of the scope, one of the precursors for forming a conductive path includes an energy range garden at 3 keV to 10 keV or 1 $, keV to 50 keV, and lxlO11 / cm2 to lxl013 / + A square centimeter dose is implanted with a dopant selected from the group consisting of dopants including B or BFs to form a conductive pathway precursor. The method of claim 7 in the patent scope includes annealing the structure at a temperature of about 500 ° C to 1100C to diffuse ions from the lower metal layer into the interfacial junction area to form a conductive path precursor. For example, the method of claim 7 includes forming a second conductive type via having a thickness of about 50 nm to 100 nm. For example, the method of claim 7 of the scope of the patent application, wherein the implanted dopant impurities include pruritus with an ion implantation device selected from the group consisting of kun and phosphorus, and implanted with an energy of about 40 keV to 70 keV and phosphorus at about 30. kv ——- v King 60 keV energy implantation, the dose of ions is about 2 × 10 5 / cm 2 to 5 × 10 15 / cm 2. For example, the method of claim 7 of the scope of patent application includes a deposition-layer TiOx layer on the FEM gate unit. -58- Good paper size applies Chinese National Standard (CNS) A4 specification (2! 0X297 公 #) r (Please read the notes on the back before filling this tile), 1T 13. 14. 409366 A8 B8 C8 D8 Ministry of Economic Affairs Printed by Zhongli Standard Bureau Shellfisher Consumer Cooperative 15. 16. Scope of patent application = Method 7 of the scope of patent application 'wherein the conductive path precursor layer is located below the edge of the FEM gate unit. A ferroelectric memory (FEM) unit is characterized in that it includes: a single crystal base tertiary, which includes an active region; a source junction region and a drain junction region are located on the active region and are formed by doping; A pair of first-type conductive paths; a gate; a junction area, which is located at the boundary between the source junction area and the drain junction area, and is doped to form a second-type conduction passage; a conductive path precursor Object area, which is located on the gate; ^ junction area; a FEM 閛 unit, which includes a layer of metal: layer,-layer? ] And one upper metal layer; the size of the FEM gate unit on the gate junction area is the distance between any edge of the FEM gate unit and the edge of the source junction area and the non-electrode junction area is Γ β ", this The "D" at the place is about 50 nm to 300 nm; an insulating layer has an upper surface on the junction area, the FEM gate unit and the substrate;-a source electrode and a drain electrode, each on the insulating layer On the surface and extending through the insulation layer to make electrical contact with its individual interface area. Contact and a gate electrode are located on the upper surface of the insulation layer and extend through it to make electrical contact with the metal J on the FEM gate: ¾. For example, in the scope of patent application No. 1, 4; FEM unit, wherein the conductive path precursor includes pt ions, which are diffused from the metal layer under the FEM gate unit during the annealing of the structure at about 500 force to 1100 ° C. For example, for the FEM unit in the 14th scope of the patent application, the conductive path -59 sheet 1 is applicable to the Chinese National Standard (CNS) M threat (training magic 奵 mm f (Please read the precautions on the back before filling in Benwa Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China 4093G6 6. The scope of the patent application precursor includes ion implantation and the plasma ion is selected from the energy including B and BF2 between 3 keV to 10 keV and 15 keV to 50 keV Implants and doses range from lxlO11 / cm2 to lxlO13 / cm2. 17. For example, the FEM unit of item 14 of the patent application park, wherein the FEM gate unit includes a lower metal layer made of Pt with a thickness of about 20 nm to 100 nm, and a thickness of about 100 nm to 400 nm. The micron is selected from the group consisting of FE layers made of materials including Pb (Zr, Ti) 03 (PZT), SrBi2Ta209 (SBT), Pb5Ge3Ou, BaTi03, iLiNb03, and a layer having a thickness of about 20 nm to 100 nm. Pt, Ir and Pt / Ir combined; ΐ, a metal layer made of gold. 18. The FEM unit of item 14 in the patent application range, wherein the active region includes ions selected from the group consisting of arsenic and phosphorus, arsenic is implanted at an energy of about 40 keV to 70 keV, and the scale is at about 30 keV to With 60 keV energy implantation, the plasma dose is about 2xl015 / cm2 to 5xl015 / cm2. 19: A method for forming a semiconductor structure having a MOS transistor and a ferroelectric memory (FEM) unit formed on a silicon substrate, which is characterized by comprising: forming an active region on the substrate, thereby forming a first-type conductive path Forming p_ 咣 on the substrate, thereby forming a second type conductive path; forming a JV10S transistor on the f-well; and forming a FEM gate unit, which includes depositing a lower metal layer, a _FE layer and an upper metal Layer, wherein the lower metal layer is located on at least a portion of the first type conductive path. -60-vi This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ^ I_1 Irr A8 B8 C8 D8 409366 VI. Application scope of patents' 20- The method of applying for patent scope item 19, wherein the formation of the second type conductive path includes 3 keV to 10 keV or IS keV to 5 The energy in the range of 〇keV and a dose of ΙχΙΟ11 / cm2 to lxl013 / cm2 are implanted in the device area with a kind selected from the group consisting of B or BF2, miscellaneous agent β 21. If the method of item 19 of the patent application, including At about 500. The structure is annealed at a temperature of 0 to 1100 ° C, so that the B or BF2 ions diffuse from the second-type conductive path into the gate junction area to form a second-type conductive path. 22. The method according to item 19 of the patent application park, wherein the deposition gate unit includes a deposition thickness of about 20 nanometers to 400 millimeters selected from the group consisting of Pt, Ir, Ir02 and Pt / Ir alloys. The material is made of a lower metal layer with a thickness of about 50 nm to 400 nm selected from the group consisting of Pb (Zr, Ti) 03 (PZT), -SrBi2Ta209 (SBT), PbsGesO ", BaTi〇3, and LiNb. The FE layer made of the lining material of 3, and the upper metal layer made of a material selected from the group consisting of Pt, Ir, ΐΓ〇2 & 'Pt / Ir alloy with a thickness of about 20 nm to 100 nm. 23. The method according to item 19 of the patent application range, wherein the implanting of the third type of gadolinium + impurity includes doping the device region with an ion selected from the group consisting of kun and phosphorus, and arsenic is about 40keV to 70keV The energy implantation and the sacral implantation are performed at an energy implantation of about 30 keV to 60 keV, and the dose of ions is about ixiQi 'cm2 to 5xl015 / cm2. 24. The method according to item 1 of the scope of patent application, wherein an insulating structure is deposited around the FEM gate unit, including depositing a layer of an insulating material selected from the group consisting of TiOx & SbN4 on the MOS transistor and the FEM gate unit. Floor. ______- 61-This paper is a common national standard (CNS) inspection (210x297) '~ [ri (please read the notes on the back before filling out this page), 1T Central Bureau of Standards, Ministry of Economic Affairs-Industrial Consumption Cooperative printed ABCD 409366 6. Application for patent scope 25. The method for applying patent scope item 19, wherein the forming of the FEM gate unit includes depositing a transistor insulation layer on the MOS transistor, and then on the transistor insulation layer Forms a FEM brake unit. 26. The method of claim 19, wherein the forming the FEM gate unit includes depositing a transistor insulating layer on the MOS transistor and then forming the FEM gate unit along the side of the MOS transistor. 27. A method for forming a semiconductor structure, the semiconductor structure having a MOS transistor and an 'electrical (FEM) unit formed on a dream substrate, comprising: · ,,,, forming an active region on the substrate, thereby forming a first Forming a p-well on the substrate, thereby forming a second type conducting path; forming a MOS transistor on the well; and forming a FEM gate unit including a deposition thickness of about 20 nm to 100 nm The lower metal layer is made of materials including Pt, Ir, Ir02 and Pt / Ir alloy, and a thickness of about 50 nm to 400 nm is selected from the group including Pb (Zr, Ti) 03 (PZΊ), SrBi2Ta209 (SBT) ， FE layer made of materials of Pb5Ge3On, BaTi03, and LiNb03, and made of materials selected from the group consisting of Pt, Ir, IrO2, and Pt / Ir alloys with a deposition thickness of about 20 nm to 100 nm An upper metal layer, wherein the lower metal layer covers at least a part of the first type conductive path. 28. The method according to item 27 of the patent application, wherein the formation of the second type conduction / electrical path includes the energy at 3 keV to 10 keV or 15 keV to 50 keV, respectively, and lxlO11 / cm2 to lx 1013 / A dose of cm2 is implanted in the device area with an impurity selected from the group consisting of B or BF2. -62--This paper is a Chinese standard (CNS) A4 specification (210 × 297 mm) .. ~~ 1. Γ —---- t ^ \ J ^ I — (Please read the notes on the back first (Fill in this page again), 1T Magic '; Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, printed by ABCD Printed by the Consumers Cooperatives of the Central Standards Bureau of Ministry of Economic Affairs, printed by the Consumer Cooperatives 409366 VI. Application for Patent Scope 29. Such as the method of applying for patent No. 27 , Which includes annealing the structure at a temperature of κ500〇β (: to 1100 C, so that b or BFs is diffused from the second conductive path into the closed junction area to form a second type conductive path. 3．As applied The method of item 27 of the patent model, wherein the implanting of the third type dopant includes doping the device region with an ion selected from the group consisting of arsenic and phosphorus. Arsenic is implanted at an energy of about 40 keV to 70 keV and Phosphorus is implanted at an energy of about 30 keV to 60 \ eV, and the dose of ions is about ΐχΐ015 / cm2 to & 1015 / cm2.-31. The method of item 27 of the patent application park- , Where: f to form a FEM gate single fan consists of depositing a transistor_insulating layer on the MOS transistor and subsequently. The FEM gate unit is formed on the insulating layer. The method of 3Z such as the scope of the patent claim 27, wherein the formation of the FEM gate unit includes depositing a layer of a transistor insulating layer on the MOS transistor and then forming a ρ along the side of the MOS transistor. · EM gate unit. 3 丄. A dual transistor memory unit is characterized by comprising: a silicon substrate including an active region, wherein the active region is formed by a first doped, though doped, substance to form a first type conductive path. A via region, which is located in the active region and is doped with a second type doped impurity to form a second type conductive path; a source junction region is a non-electrode junction region, which is located in the active region and located at the gate The junction area is formed on either side of the junction area by doping-a third type conductive path; and-a MOS transistor located adjacent to the second type conductive path; a FEM gate unit including a lower metal layer, Layer by layer! _ '-63- .. ,, This paper size applies to China National Agricultural Standard (CNS) A4 (210X297 mm) f (Please read the precautions on the back before filling in this tile) 409366 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 6. The scope of patent application and a layer of upper metal layer; where the FEM gate unit is at least partially covered above the first type conductive path and at the gate junction area The size is FE] The distance from any edge of the VR to the source interface area and the drain interface area is "D", where "D" is about 50 μm to 300 nm; -A layer of transistor insulation layer is located between the MOS transistor and the FEM gate unit;-a layer covering the insulation layer which extends on the conductive path, the MOS transistor and the FEMfri unit; and-a source electrode and a drain An electrode, which is located on the upper surface of the covering insulating layer and extends through the insulating layer to apply electrical contact to its individual interface area, wherein the drain electrode is in contact with the drain interface area and the second type conductive path; and Two gate electrodes are located on the upper surface of the covering insulating layer and extend through the insulating layer to make electrical contact with the metal layer above the FEM gate unit. 34. The memory unit according to item 33 of the patent application scope, wherein the second-type electrical path includes an ion implantation therein, and the plasma system is selected from the group including B and BF2, which are 3 keV to 10 keV and 15 respectively. Energy in the range of keV to 50 keV and a dose of lxlO11 / cm2 to lx1013 / cm2 are implanted, and ions are diffused in the structure from 50 (TC to 1100X: diffused from the device area during the annealing at a low temperature. 35. If requested The memory unit of the 3rd item of the patent, wherein the j? Em gate unit includes a metal layer with a thickness of about 20 nm to 100 nm ipt, and a layer of thickness from about 100 nm to 400 nm is selected from the group consisting of Pb (Zr, Ti) 03 (PZT), SrBi2Ta2009 (SBT), Pb5Ge30 „, 64-.. This paper size applies Chinese National Standard (CNS) A4 (210 X297 mm) I .——.- -------- Q —— (Please read the note _ item on the back, and then fill out this page) Order the print of the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperative Co., Ltd. 409366! D8 6. The scope of patent application BaTi03, and LiNb03 FE layer of the material, and a layer having a thickness of 20 nm to 100 nm selected from the group including Pt, Ir, Ir0 2 and Pt / Ir alloy material. The upper metal layer. 36. For example, the memory unit of the patent application No. 33, wherein the active region includes ions selected from arsenic and phosphorus, arsenic is about 40 The energy implantation and defense of keV to 70 keV is based on the energy implantation of about 30 keV to 60 keV, and the dose of ions is about lxl 015 / cm2 to 5x1ο15 / cm2. Memory unit-element, in which the FEM gate unit is covered on the MOS transistor. 38. If the memory unit in the 33rd item of the patent application, the MOS transistor and the FEM gate unit are arranged side by side. 39. A method for forming a semiconductor structure. The semiconductor structure has a ferroelectric memory (FEM) gate unit on a baseboard. The board is characterized by comprising: forming a dream device region of the FEM gate unit; and implanting a first in a silicon device region. Doping impurities to form a first type conductive path for use as a gate junction area; depositing a FEM gate unit on the gate junction area includes depositing a lower metal layer, a FE layer and an upper metal layer, wherein the FEM gate unit gas on gate junction area The rule is that the distance between any edge of the ρΕΜ gate unit and the edge of the source junction region and the drain junction region is "DJ", where "D" is about 50 nm to 3 nm; deposit an insulating structure on the FEM Around the gate unit; implant the first type of doped impurities in the gate junction area of the silicon device area _____ · 65 · '' this paper New Cailaijia County (CNS)-~: --- (Please Read the notes on the back before filling out this page) Order ABCD Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printed by 409366 VI. Patent application park = side to form a second-type conductive path for the source contact area and sink A third type conductive path is formed on the gate contact area, wherein the size of the third type conductive path on the gate contact area is any edge from the third type conductive path to the source contact area The distance from the edge of the drain junction area is' "C", where "C" is about 0 nm to 300 nm. 40. The method of claim 39 in the scope of patent application, wherein the formation of the third type conductive path includes energy in the range of 3 keV to 10 keV- and 15 keV to 50 keV, and 1x1011 / cm2 to 1x1 〇13 /, 4. Implanting a dopant selected from the group consisting of B or BF2 at a dose of square centimeters "41. The method of item 39 of the patent application, which includes annealing the structure at a temperature of about 500eC to 1100C The B or BF2 ions diffuse from the lower metal layer into the gate junction area to form a third type conductive path. 42. The method according to item 39 of the patent application park, wherein the deposition of the feM gate sheet. The element includes depositing a layer of a thickness of about 20 nm to 100 nm selected from the group consisting of Pt, Ir, Ir02 and Pt / Ir alloy material under the metal layer, deposited with a thickness of about 50 nm to 400 nm selected from materials including Pb (Zr, Ti > 03 (PZT), SrBi2Ta209 (SBT), Pb5Ge3On, BaTi03, and LiNb03 FE layer, with a thickness of 20 nm to 100 nm. It is selected from the group consisting of fPt, Ir, Ir02 & Pt / Ir alloy material. Method, wherein the implanting of the second type dopant impurity includes doping the device region with an ion selected from the group consisting of thorium and phosphorus, arsenic is implanted at an energy of about 40 keV to 70 keV and is squatted at about 30 -66-eight Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) Printed by AS 4093G6 cl D8, Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs VI. Application for patents == keV to 60 keV for implantation of energy, the dose of ions is about lx1015 / cm2 to 5xl015 / cm2 44. For example, the method of claim 39 in the patent application park, wherein the depositing the insulating structure on the FEM gate unit includes depositing a layer of an insulating material selected from the group consisting of TiOxKShNi on the FEM gate unit. 45. A method for forming a semiconductor structure, the semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate, which is characterized by comprising:-a ... forming a sand device area of the FEM gate unit l > in silicon A first type of doped impurities is implanted in the device area to form a first type conductive path for use as a gate junction area; depositing a FEM gate element on the gate junction area, including depositing a layer having a thickness of about 20 nm to 1 〇〇nm is selected from the group consisting of pt, ιΓ, Ir〇2 and Pt / Ir alloy under the metal layer, the deposition thickness of about 50 nm to 400 nm is selected from the group consisting of: Pb (Zr, Ti) 03 (PZT), SrBi2Ta2O9 (SBT), PbsGeWn, BaTi03, and LiNb03 materials, and FE layer with a thickness of 20 nm to 100 nm selected from materials including Pt 'Ir, Ir02, and Pt / Ir alloys The upper metal layer, wherein the size of the FEM gate unit on the gate junction area is the distance between any edge of the fem gate unit and the edge of the source selection junction area and the drain junction area is "D", here "D "" Is about 50 nm to 30 nm; deposit an insulating structure on the FEM gate unit The second type of doped impurities are implanted on either side of the gate contact area of the silicon device area to form a second type conductive path for use as the source contact area and the drain-67- ..:., Zhang Zhang Standards are applicable to China National Standard (CNS) A4 specifications · 7Ίϊ〇χ297mm) ':-(Please read the precautions on the back before filling in this page} _ 1 '409366 ABCD VI. The scope of patent application is economical. 郅 The central plug-in bureau staff consumer cooperatives in the middle electrode contact area; a third type conductive path is formed on the gate contact area, where the third type conductive path is in the gate. The size of the electrode junction area is that any edge of the third type conductive path is away from the source junction area and the drain junction: the distance between the edge of the area is "C", where "Cj is about 0 nm to 300 mm 46. The method according to item 45 of the patent application park, wherein the formation of the third type conductive path package 1 has an energy in the range of 3 keV to 10 keV and 15 keV to 50 keV, i lxlO11 / cm 2 to χ 1〇η The implantation dose per square centimeter is selected from the dopants including B or BF2 in the lower gold layer. 47. For example, the method in the scope of patent application No. 45, wherein the third type of conductive path is formed by 3, 10 to 10 keV And an energy in the range of 15 keV to 50 keV and a dose of lxlO11 / cm2 to lxl0i3 / cm2. Implanted from a dopant including B or BF2 on the surface of the first type conductive layer. A method according to item 45, which comprises depressurizing at a temperature of about 501 to 1100 C. Fire the structure to diffuse b or bf2 ions from the lower metal layer into the gate junction area to form a third type conductive path. 49. For example, the method of claim 45 in the scope of patent application, wherein the second type dopant is implanted Impurities include doping the device area with ions selected from the group consisting of arsenic and phosphorus. Arsenic is implanted at an energy of about 40 keV to 70 keV. Phosphorus is implanted at an energy of about 30 keV to 60 keV. Implantation, the ion dose is about ιχ1〇ΐ5 / flat—one—square centimeter to 5χ1015 / flat gas centimeter. 50. The method according to item 45 of the patent application scope, wherein the deposition of the insulating structure around the FEM 閛 unit includes depositing a layer selected from the group including Ti0; The insulation material of the team is on the FEM brake unit. -68- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2I0X297 official celebration) ({Please read the precautions on the back before filling out this page), " ·- ί-I 印 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 409366 as C8 ______________— DS VI. Scope of patent application ^ ^ -----— A child-type ferroelectric memory (FEM) unit, which is characterized by the inclusion of; One silicon substrate including one active area; Each gate junction area, tp… is located in the active area and is doped to form a first-type conductive path; each source junction area and a non-polar junction area are located at the gate junction in the active area. On either side of the area, they are doped to form a pair of first-type conductive paths; a first-type conductive path is located on the gate junction area; and a FEM gate unit includes a lower layer of gold, A layer of FE layer and a metal layer on the layer; wherein the FE1VT gate unit is covered on the third type conductive path and has a surface area smaller than that of the third type conductive path area, and its size on the gate junction area is The distance from any edge of the FEM gate unit to the source junction region and the drain junction region is "D", where "D" is about 50 nm to 300 nm; an insulating layer having an upper surface covered on the The interface areas, the gate unit and the substrate; and a source electrode and a drain electrode, each of which is located on the upper surface of the insulation layer and extends through the insulation layer to make electrical contact with its individual interface area, and a The gate electrode is located on the surface of the insulation layer and extends through the insulation Layers make electrical contact with the metal layer over the FEM gate unit. *-^ _w_ · 52. If the FEM unit of item 5 丨 of the patent application scope, wherein the third type conductive path includes ion implantation, and wherein the ions are selected from the group consisting of B and BF2, which are respectively at 3 keV To 10 keV and 15 keV to 50 keV Fanyuan's energy and ΙχΙΟ11 / cm² to ιχι〇ι " cm²-69-— „__ ^ ______, --- (Please read the notes on the back before filling this page ) ^ Order} ----— -—----— * __ This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) f 8 00 8 8 ABCD 409366 6. Scope of patent application (please first Please read the notes on the back of the page and fill in this page). The dose implantation is diffused by the metal layer under the FEM gate unit during the annealing of the structure at a temperature of about 500 ° C to 1100 ° C. 53. The FEM unit of 51, wherein the FEM gate unit includes a layer having a thickness of about 20 nanometers to 100 millimeters: a metal layer under a pt of a meter, and a layer having a thickness of about 100 nanometers to 400 nanometers It is selected from the group consisting of Pb (Zr, Ti) 03 (PZT), SrBi2Ta209 (SBT), PbsGejOn, BaTi03, and LiNb03. FE layer of the material, and a layer of a thickness of / 0 nm to 100 nm selected from the group consisting of pt, Ir, IrO2 and Pt / Ir alloy on the metal, layer.,-S 5 4 The FEM unit of item 51, wherein the active region includes ions selected from kun and phosphorus, arsenic implanted at an energy of about 40 keV to 70 keV, and scales implanted at an energy of about 30 keV to 60 keV. The dosage of the plasma is about lxio15 / cm2 to 5x1015 / cm2. 55. The FEM unit of Item 51 of the patent application park, wherein the third type conductive path is constructed and arranged to make any edge distance The distance between the edge of the source junction region and the edge of the set junction region is "C", where "C" is about 0 nm to 300 nm. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 56. A method of forming a semiconductor structure with a ferroelectric memory (FEM) gate unit on Huan Jidong, which is characterized by: f formation The silicon device area of the FEM gate unit; the first type doped impurity is implanted in the device area to form the first type conductive path for the gate interface area; __________ ™™ 70 _. This paper is located at the CNS Α4 · (21ι) χ297 male thin]: ~~ —— r ABCD 409366 _____ _____ 'VI. Application scope of patent,' Implant a second type doped impurity into the device area to form a second type conductive layer; deposit a FEM gate unit On the second type conductive path; including depositing one lower metal layer, two 1 ^ layers: and one upper metal layer, wherein the size of the FEM gate unit on the gate junction area is Fem, and any edge of the gate unit is away from the source The distance between the junction area and the edge of the Zen junction area is "D", where "; 0" is about 50 nm to 300 nm; < depositing an insulating structure on the Fem gate unit; and implantation Type III doped impurities in silicon _ The placement area is on any side of the 竑 -electrode junction area, and a third type conductive path is formed for use as the source-contact area and; and the pole-contact area, wherein the second-type conductive path extends into the drain contact. 57_ The method according to item 5 of the patent application range, wherein the forming of the second type conductive path includes the energy of Fan Yuan at 3 keV to 10 keV and 15 keV to 50 keV, and lxlO11 / cm2 to lxl0i3 Dosage per square centimeter is implanted in the device area selected from the dopants including B or Bh. 58_ The method according to item 56 of the patent application, which includes annealing the structure at a temperature of about 500 ° C. to 1100 ° C. The b or bf2 ions are diffused from the lower metal layer into the gate junction area to form the fifth contention path. 59, for example, the method of item 5f of the scope of patent application, wherein the depositing gate unit includes depositing a layer with a thickness of about 20 nanometers to 100 nanometers is selected from the group consisting of Pt, Ir, Ir02 and Pt / Ir alloys under the metal layer, the deposition thickness of about 50 nanometers to 400 nanometers is selected from the group consisting of _ 71 _ Dimensions are applicable to National Standards (CNS) A4 (210X297 mm) of country f ^ LI LI --------- · \ Ν! (Please read the notes on the back before filling in this 1) stT Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 409306 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. (Zr, Ti) 03 (PZΤ), SrBi2Ta209 (SBT), Pb5Ge30, BaTi〇3, and LiNb03; Fe layer, and a thickness of 20 nm to 100 nm selected from the group including Pt, Ir , Ir02 and Pt / Ir alloy on top of the metal layer. 60. The method according to item 56 of the patent application range, wherein the implanting of a third type of doped impurity includes doping the device region with an ion selected from the group consisting of arsenic and phosphorus, and arsenic is implanted at an energy of about 40 keV to 70 keV Phosphorus is implanted at an energy of about 30 keV to 60 keV, and the dose of ions is about ιχιΟ15 / cm2 to 5xl015 / cm2. For example, the method of claim 56 in the patent application park, wherein depositing the insulating structure around the FEM gate unit includes depositing a layer of an insulating material selected from the group consisting of TiOx & Si3N4 on the FEM unit. For example, the method in the 56th patent application scope further includes depositing a silicide layer on the source junction region and the drain junction region. 63. A method for forming a semiconductor structure, the semiconductor structure having a ferroelectric memory (FEM) gate unit on a wonderful substrate, which is characterized by comprising: a silicon device region forming the FEM gate unit; and implanting in a sand device region The first type is doped with impurities to form the first type conductive path for use as the gate junction area; the first type is implanted into the device area to form the second type conductive layer; a FEM gate unit is deposited on the second Type conductive path above the gate junction area, including depositing a layer with a thickness of about 20 nanometers to 100 nanometers 61. 62. -72- The paper size applies to Chinese national standards (CNS > A4 specifications (2 〖0χ297 (Gongchu) r " — ^-j ------ Λ__ (Please read the precautions on the back before filling out this page) 'IT C8 D8 Printed by the Consumer Consumption Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. Application Patent Fan Yuan.. M & selected from the group consisting of pt, lr, 〇Γ〇2 and pt / Ir alloy under the metal layer 'deposited thickness of about 50 nm to 400 nm selected from the group including Pb ( Zr? Ti) 〇3 (PZT), SrBi2Ta209 (SBT), Pb5Ge3Ou, BaTi〇3, and LiNbCh FE layer, and a thickness of 20 nm to 100 nm selected from the group consisting of pt, Γγ, Ir02 & P " Ir alloy I material over the metal layer, wherein the FEM gate unit is connected to the gate electrode The ruler on the area is the distance between any edge of the FEM gate unit and the edge of the source contact area and the end of the non-contact interface. The distance is “D” .., where “D” is about 50 millimeters. Micron to 300 nm; \ ^ a *? 'Deposit an insulating structure on the FEM gate unit; > and implant a type II doped impurity on the silicon device region on either side of the gate junction region' to form The third type conductive path is used as the source contact area and the drain contact area, wherein the second type conductive path extends into the drain contact area β-64 '. Wherein, the formation of the second type conductive path includes energy implanted at a range of 3 keV to 10 keV and 15 keV to 50 keV, and a dose of 1U011 / cm2 to 1x10n / cm2. One is selected from the group consisting of: B or BF2. The dopant in the device area is β-preventing the method according to item 63 of the patent application scope, which includes about 500 °. However, ions or ions diffuse from the lower metal layer into the gate junction area to form a second type conductive path. 66. For example, the method of claim 63 in the patent application scope, wherein the implanted third type doped impurities include Selected from the device area containing ions of arsenic and phosphorus, arsenic is implanted at about 40 keV to 70 keV and phosphorus is at about chuan 丨 -73- This paper size applies to Chinese National Standard (CNS) A4 specification (2iOX297 (Information): ί, ο! (Please read the notes on the back before filling out this page) Printed by the Central Labor Bureau of the Ministry of Economic Affairs, Printed by the Consumer Cooperative of A8 B8 __409366 品 _ ττ, patent application scope keV to With 60 keV energy implantation, the dose of ions is about 1 x 1015 / cm2 to 5 x 1015 / cm2. 67. The method of claim 63 in the scope of Shenjing patent, wherein depositing the insulating structure on the FEM gate unit includes depositing a layer of an insulating material selected from the group consisting of TiOx & Si3N4 on the FEM gate unit. 68. The method according to item 63 of the patent application park, which further includes depositing a dream material layer on the source junction region and the drain junction region. 69. A type of ferroelectric g memory body (FEM) unit, comprising: a silicon substrate including an active region; ^ a gate junction region, which is doped in the active region to form a first type of conduction Via; a source junction region and a drain junction region, which are located on either side of the gate junction region in the active region, and which are doped to form a third type conductive path; ^ a first The second type conductive path is located on the gate junction area and partly extends into the non-electrode junction area. A PMM gate unit includes a lower metal layer, a layer of ugly layer and an upper metal layer; wherein the FEM gate unit It is covered on the third type conductive path and has a surface area smaller than the surface area of the third type conductive path area, and its 'inch' on the gate electrode rain area is any edge of the FEM gate unit from the source junction area. The distance between the contact areas is "D", where "DJ is about 50 nm to 30 nm; an insulating layer having an upper surface covering the contact areas, the gate unit and the substrate; and -74 -LI. CV—, f% first notices Jing Jing's back and then writes Page) • Order. This paper size applies Chinese National Standards (CNS) M specifications (21〇 × 297 male thin A8 B8 C8 VI. Patent applications I thank you: ----- one source electrode and one non-polar electrode , Which are respectively located on the upper surface of the insulation layer and extend through the insulation layer to make electrical contact with its individual interface area, and a gate electrode is located on the upper surface of the insulation layer and extends through the insulation layer and above the FEM gate unit. Metal The layer is in contact with 嚅., 70 'If the FEM unit of item 6 or 9 of the patent application scope, wherein the second type conductive path includes ion implantation therein, and wherein the ion system is selected from the group consisting of B and BF2 / which are respectively at 3 Energy implanted in the range of keV to 10 keV and 15 keV to 50 keV and doses from cm2 to ΐχΐ〇Π / cm2, which are implanted in the structure at about 5i) 0 ° c. The metal layer under the FEM gate unit is diffused. 71. For example, the FEM unit under item 69 of the patent application park, wherein the FEM gate unit includes a metal layer with a thickness of about 20 nm to 100 nm. A layer having a thickness of about 100 nm to 400 nm FE layer consisting of Pb (Zr, Ti) 03 (PZT), SrBi2Ta209 (SBT), Pb5Ge3〇ii, BaTi〇3, and LiNb〇3, and a layer with a thickness of 20 ′ to 100nm selected from Including the metal layer on the material of pt, Ir, Ir02 and Pt / Ir alloy. 72. For example, the FEM unit of item 69 of the patent application park, wherein the active region includes ions selected from arsenic and scales. The energy implantation of 40 keV and 70 keV, and the energy implantation of phosphorus based on 30 keV to 60 ^ eV, the dose of the plasma is about} × 10 5 / cm 2 to 5 × 10 15 / cm 2. 73. For example, the FEM unit of item 69 of the patent application park includes a layer of debris on the source junction area and the non-electrode junction area. -75 ~-— __ ____ · · — — This paper size applies to the Chinese National Standard (CNS) M specification (210X297 mm) '* nn Γ— n II— I l · · il I Factory J f Please read the first Note: Please fill in this education again) ir r Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy—-409366 g | 6. Scope of patent application. 4 'A method for forming a semiconductor memory device on a silicon substrate, comprising: implanting a first-type doped impurity in the silicon substrate to form a first-type conductive path for use as a gate region; forming a MOS capacitor in the first Type I conductive path; > Several FEM capacitors on MOS capacitors, including deposition of a lower metal layer, a FE layer and an upper metal layer, thus forming a stacked gate unit; an implanted second type dopant The impurities form a second-type conductive path on the silicon substrate on either side of the gate-to-plane interface area for use as the source-to-plane interface area and the drain-to-electrode interface area; and a body is deposited around the FEM gate without a dielectric junction. 75. The method of claim 74, wherein forming the first type conductive path includes energy in the range of 3 keV to 10 keV and 15 keV to 50 keV and ΙχΙΟ! 2 / cm2 to 1χ1〇14 / A dose of cm2 is implanted in a dopant selected from the group consisting of B or BF2. 76. The method according to item 74 of the patent application scope, wherein the depositing the FEM gate sheet comprises depositing a layer of a material selected from the group consisting of Pt, lr, ir0 2 & pt / Ir alloy with a thickness of about 20 nm to 100 nm A metal layer with a thickness of about 50 nm to 400 nm is selected from materials including Pb (Zr, Ti) 03 (PZT), SrBi2Ta20 "SBT", PbsGesOn, Ba: Ti03, and LiNb03. FE layer, and a metal layer selected from materials including Pt, Ir, Ir02, and Pt / Ir alloy with a thickness of 20 nm to 100 nm. -76-_ This paper is applicable to the national standard (CNS) A4 specification (210X297mm) 丨 ·-丨 ^ ----- t &l; (Please read the items on the back of the report before filling in this purchase) Sun order · Order ABCD 409366 x, apply for patents (please first (Please read the notes on the reverse side and fill in this page) 77. If the method of applying for the scope of the patent No. 74, wherein the implanted second-type doped impurities include doping the device area with ions selected from the group consisting of kun and phosphorus, arsenic is Energy implantation of about 40 keV to 80 keV and phosphorus implantation of energy of about 20 keV to 50 keV, the dose of ions is about lxl O15 / cm2 to 5xl015 / cm2. 78. The method according to item 74 of the patent application, wherein the deposition of the insulating structure on the FEM capacitor and the MOS capacitor includes a layer of insulation selected from the group consisting of 40; £ and Si3N4. Material layer ..- 79. The method of claim 74, wherein forming a MOS capacitor includes forming a MO & capacitor with a predetermined surface area, and wherein the depositing FEM capacitor includes depositing a surface area less than the MOS FEM capacitor with surface area of capacitor. 80. The method of claim 74, wherein the forming a MOS capacitor includes forming a MOS capacitor having a predetermined surface area, and wherein depositing the FEM capacitor includes depositing a surface area substantially equal to a 'MOS capacitor The surface area of the FEM capacitor. 81. The method as described in item 74 of the patent application scope, which includes forming a second MOS capacitor along the side of the stack gate unit. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 82.-Kind of silicon substrate There are no methods for forming semiconductor memory devices, which are characterized by: The first type conductive path is formed on the silicon substrate to be used as the gate region for the gate interface region. Forming a MOS capacitor on the substrate includes forming an oxide layer on the first type conductive path. And a layer of n + poly-77- is formed on it. This paper size is applicable to Chinese National Standard (CNS) M specification (2Λ0 × 297 mm) Printed by the Consumers' Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs A8 409366 1 6. Scope of patent application A layer of silicon; depositing a FEM capacitor on a MOS capacitor includes depositing a layer of metal selected from the group consisting of ir, IrO2, and alloys with a thickness of about 20 nm to 100 nm; 〇 • nm to 400nm selected from the group consisting of: ρ | 3 (Zγ, ΊΌ〇3, .SrBi2Ta2009 (SBT), Pb5Ge3On, BaTi03, and LilSfb03 material FE layer, and the deposition thickness is 20 millimeters Micrometers to loo nanometers are selected from the group consisting of Pt 'Ir' Ir〇2 and Pt / Ir alloys-the metal layer on the material, thus forming a stacked gate unit; _, _-V implanted a second type of doped impurities in Silicon substrate Any-a second type of conductive path is formed on the side for use as the source junction area and the gate junction area! And _ deposit an insulation structure around the gate unit. 83. The method according to item 82 of the patent application range, wherein the forming of the first type conductive path includes energy in a range of 3 keV to 10 keV and 15 keV to 50 keV, respectively, and lxlO12 / cm2 to 1X1 〇14 / square A dose of centimeters is implanted on the substrate with a dopant selected from B or BF2. 84. The method of claim 82, wherein the implanted second-type dopant impurity comprises doping the device region with an ion selected from the group consisting of arsenic and phosphorus, and arsenic is at an energy of about 40 keV to .80 keV. Implantation and phosphorus are introduced at an energy of about 20 keV to 50 keV, and the dose of ions is about 1 x 1015 / cm2 to 5 x 1015 / cm2. 85. The method according to item S 2 of the scope of patent application, wherein the deposited insulating structure is deposited around a FEM capacitor and a MOS capacitor, and a layer selected from -78- This paper ruler is applicable to Chinese National Standard (CNS) A4 specifications ( 210X297 male sauce) (please read the notes on the back of the book before filling out this page), 1T printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, A8 409SG6 | VI. Patent Application Scope =-Including Si3N4t insulation material layer. 86. A type of ferroelectric memory (FEM) unit, comprising: a silicon substrate; 13 an inter-electrode region, which is located on the substrate and is tapered to form a first pad conductive path: a source terminal The surface area and a drain junction area are located on any of the substrates on the gate surface of the substrate—are formed by doping on the side—widely for the second type conductive path _________ · · = = MOS capacitors' It includes two layers of intermediate oxide layer and a third type of conductive layer located on the gate junction area. The MOS kettle container has a predetermined surface area; a FEM capacitor includes a lower metal layer, a FE layer and an upper metal layer. ; Wherein the FEM capacitor is kept stacked and covered on at least a part of the MOS capacitor ', thus forming a stacked gate unit together with the μ〇§ capacitor; 1 layer of an insulating layer having an upper surface covering the junction areas, Stacked gate units and substrates; and-a source electrode and a drain electrode, each on the upper surface of the insulating layer and extending through the insulating layer to make electrical contact with its individual interface area, and a gate electrode, And the insulating layer on the surface of the insulating layer and extending through the intersection of the gate stack, on top of the metal element 'do the electrical contact layer. 87. If the FEM unit of item 86 of the patent application scope, wherein the first type conductive path includes ion implantation therein, and wherein the ions are selected from the group consisting of B and BF2, which are respectively at 3 keVi 10keV & 15 1 ^ 1 ^ / to 5〇 ____ _79_ i Two standards (? NS) in paper making Α4 · (Xin Xin Mi Li)-(Please read the precautions on the back before filling this page) Order 409366! D8 Six 2. Patent application, energy in keV range, and implantation at a dose of lxlO12 / cm2 to lxlO14 / cm2. 88. The FEM unit according to item 86 of the patent application scope, wherein the FEM capacitor includes a metal layer under the material of P t, I r, Ir02 and PlVIr alloy with a thickness of about 20 to 100: nanometers, A layer of a thickness of about 100 nanometers to 400 nanometers selected from the group consisting of four materials including Pb (Zr, Ti) 03 (PZT), SrBi2Ta209 (SBT), Pb5Ge3On, BaTi03, and LiNb03, and a layer of 20 nm in thickness The micrometer to 100 nanometers are selected from a metal layer over a material including Pt, Ir, Ir02 and Pt / fr alloy. 89. If the FEM unit of item 86 of the patent application scope, wherein the second type conductive path includes ions selected from arsenic and phosphorus, arsenic is implanted at an energy of about 40 keV to 70 keV, and phosphorus is at about 30 For implantation of energy from keV to 60 keV, the dose of the plasma is about lxlO15 / cm2 to 5xl015 / cm2. 90: For example, the FEM unit of item 86 of the patent application scope, wherein the third type conductive path is n + polycrystalline silicon. 91. If the FEM [unit of item 86 of the patent scope is applied, which is printed by the Consumer Cooperative of the Central Standards Bureau of the FEM capacitor economy department (please read the precautions on the back before filling this page) The device is covered on the full surface area of the MOS capacitor on. ‘92. For example, the FEy sheet of item 8.6 of the scope of patent application; ^, wherein the coverage area of the FEM capacitor is smaller than the full surface area of the MOS capacitor. / 93. For example, the FEM unit of item 86 of the patent application scope includes a second MOS capacitor formed along the side of the stacked gate unit. 94. A method for forming a semiconductor structure with a -80-This paper size is applicable to China National Standard (CNS) A4 specifications (210X297 mm) A8 B8 C8 D8 95. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Manufacturing 96.409366 patent application scope Ferroelectric memory (FEM) gate unit on a silicon substrate, which is characterized by: incorporating a first type doped impurity into the substrate to form a first type conductive substrate;.; Implanted a second type doped The impurities are formed on the first type conductive substrate to form a second type conductive path; the third type conductive impurities are implanted on the second type conductive substrate to form a third type conductive path for use as a gate junction area; Type IV dopant impurities are formed on the gate junction area on the side to form a plurality of fourth-type conductive paths for use as the source junction area and the drain junction area; and > a few product FEM gate units at the gate junction The surface area includes the deposition of a lower metal layer, a FE layer and an upper metal layer, wherein the size of the feM gate unit on the gate junction area is any edge of the FEM gate unit from the source junction area and; and Pole connection The edge distance of the region is "D", where "DJ is about 50 nm to 300 nm. For example, the method of claim 94 in which the implanted second-type doped impurities are included in the range of about 10 keV to 50 The energy in the range of keV and a dose of about five square centimeters to about five centimeters square centimeters of Fanyuan are implanted with a method selected from the group consisting of phosphorus and arsenic, such as the 9th item of the patent application, wherein the first Type 3 conductive pathways include energy from 1 keV to 10 keV and 10 keV to 50 keV, and a dose of 5xl0u / cm2 to lxl0i3 / cm2. Implants selected from the group consisting of B or BF; 2 Agent. . -81-Wood paper size applies Chinese National Standard (CNS) A4 specification (21〇χ297 公 楚) (Please read the notes on the back before filling in the wood page) ABCD Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative I 409366 VI. Patent application scope: ~~ 97. If the method of applying for patent scope item 94 'is included, which includes annealing the structure at a temperature of about 500 ° C to 1100 ° C, B or Bh ions are diffused by the gate junction area to form a barrier layer between gate * FEM gate units. 98. A method as claimed in the patent claim No. 94, wherein the depositing FEM gate sheet comprises depositing a layer selected from the group consisting of Ir and Ir / IrO2 alloys with a thickness of about 20 nm to 100 nm. The underlying metal layer is deposited with a thickness of about 50 nanometers < meters to 400 nanometers selected from the group consisting of pb (Zr, Ti) 〇3 (PZT) 'SrBi2Ta209 (SBT), Pb5Ge3Ou, BaTi03, and LiNb. 3, and a thickness of 20 nm to 100 mm. The thickness of the nanometer is selected from the group consisting of materials including Pt, Ir '^ and Xunqi alloy. For example, the method of claim 94, wherein the implantation of the fourth type of doped impurities includes doping the device region with ions selected from the group consisting of arsenic and phosphorus, and the energy implantation and phosphorus system are about 40 keV to 70 keV. Implanted at an energy of about 30 keV to 60 keV, the dose of ions is about ixiV5 / sq.cm to 5xl015 / cm2. 100. The method of claim 94, wherein the depositing the insulating structure on the FEM gate unit periphery comprises depositing a layer of an insulating material selected from the group consisting of Τχ and Si3N4. '101, a method for forming a semiconductor structure, the semiconductor structure has a 1 · ^ · ferroelectric memory (FEM) ^ unit on a silicon substrate, and is characterized by comprising: implanting a first type of impurity into the substrate to form Type I conductive substrate; -82- This paper size applies to China National Standard (CNS) A4 specification (2I0X297mm) (Please read the precautions on the back before filling in each page) 6 6 3 9 ο 4 8888 ABCD Printed by the Consumer Cooperative of the Central Standards Bureau, Ministry of Economic Affairs, implanted the first type doped impurities on the first type conductive substrate to form the second type conductive path: implanted the third type doped impurities on the second type Conducting a substrate to form a third type conductive path for use as a gate interface area;; ', implanting a fourth type doped impurity on either side of the gate contact area to form a plurality of fourth type conductive paths for use as Source junction area and drain junction area; and depositing a% EM gate unit on the gate junction area, including deposition, with a layer thickness of about 20 nm to 10 (3 nm gas is selected from the group consisting of Ir and The metal layer under the Ir / IrO2 alloy material is deposited with a thickness of about 50 nm to 400 nm selected from the group consisting of pb (2r, Ti) 〇3 (ρζτ), SrBi2Ta209 (SBT), BbsGesC ^], FE layer of materials of BaTi03 and LiNb03, and a metal layer selected from materials including Pt, Ir, Ir02 & Pt / Ir alloy with a thickness of 20 nm to 100 nm, wherein the FEM gate unit The dimensions on the gate and junction area are any edge of the FEM gate unit from the source junction area and drain The edge distance of the pole contact area is "D", where "D" is about 50 nm to 300 nm. 102. The method of claim 101 in the scope of patent application, which includes about 500 Annealed the structure from ° C to 1100eC to diffuse a b or BF2 ion from the junction and surface area to form a barrier layer between the gate and the FEM gate unit. 103. The method according to item 101 of the scope of patent application Where the implanted second-type doping impurities include doping the device region with ions selected from ions including arsenic and phosphorus, arsenic is implanted at an energy of about 40 keV to 70 keV. And the scale is at about -83 pieces of paper Standards apply to Chinese National Standard (CNS) A4 specifications (210X297 mm) (Please read the notes on the back before filling out this page) iy, 1T 4093G6 A8 B8 C8 D8 Patent application scope Printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives 30 Energy implantation from keV to 60 keV, 'square centimeter to 5x1015 / square centimeter β 疋 W amount is about Idol " 104. According to the method of patent application No. 101, the structure is in the follower unit Surrounded by the layer of insulation material in the middle of the child's accumulated margin 4 and 105.- A ferroelectric memory (FEM) unit is characterized in that it includes: a first conductive type silicon substrate; a Ί conductive type conductive path formed on the substrate; a third conductive type surface conductive layer is difficult to form. The conductive path provides a gate contact area; a source contact area and a non-contact contact area are located on either side of the gate contact area within the shallow conductive path, and are doped to form a fourth type. Conductive path: and a FEM gate unit includes a lower metal layer, a FE layer and an upper metal layer, wherein the FEM gate unit covers the third type conductive path and has a surface area smaller than that of the third type conductive path area, And its size on the gate junction area makes any side of the FEM gate unit green from the source junction area and the drain junction area edge distance "D", where "DJ is about 50 nm to 300 Nanometers; an insulating layer having an upper surface covering the interface regions, the FEM gate unit and the substrate; and a drain electrode, which is located on the upper surface of the insulating layer and extends through the insulating layer to interface with it Make electrical contact, a gate electrode The pole is located on the upper surface of the insulation layer and extends through the insulation layer and -84 of the FEM gate unit. This paper size is applicable to the national standard (CNS) A4 specification (210X297). (Please read the precautions on the back before filling in this. Page j -Order 1 ........--· mi ABCD Printed by the Consumer Cooperatives of the Central Standardization Bureau of the Ministry of Economic Affairs 4093G6 6. Application of patents on the metal layer for electrical contact and a source electrode on the insulation layer And grounding a 106. For example, the FEM unit of the 105th patent application range, wherein the third type of conductive path includes ions implanted therein, and the ions are selected from the group consisting of B and BF2, respectively, from 1 keV to 10 keV and energies ranging from 10 keV to 50 keV and doses ranging from 1 × 10 μΐ / cm² to ιχ 10 × 3 / cm² ^, were ionized during the annealing of the structure at a temperature of about 500 * c to 100 ° C. A barrier layer is formed by the gate junction area spreading between the FEM gate unit and the gate junction area. , _ ,: '107. For example, the Fem unit of the 105th patent application range, wherein the Qiu μ 閛 unit includes a layer with a thickness of about 20 nm to 100 nm; ^ a lower metal layer, a thickness of about 100 A nanometer to 400 nanometer FE layer selected from materials including Pb (Zr, Ti) 〇3 (PTZ), SrBi2Ta209 (SBT), PbsGesOn, BaTi〇3 ', and LiNb〇3, and a thickness of 20 redundant microns Up to 100 nm is selected from a metal layer over a material including IΓ and IΓ / ΙΓ〇2 alloy. 108. For example, the FEM unit of the 105th patent application range, wherein the active region includes ions selected from arsenic and arsenic, arsenic is implanted at an energy of about 40 keV to 70 keV and phosphorus is at about 30 keV to 60 keV for bismuth implantation, the plasma dose is about 1x1015 / Pingzhu centimeter to 5x1ο1 s / square centimeter-85- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) (please first (Read the notes on the back and fill out this tile)