CN111009573A - 半导体器件、半导体部件和制造半导体器件的方法 - Google Patents

半导体器件、半导体部件和制造半导体器件的方法 Download PDF

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CN111009573A
CN111009573A CN201910922865.6A CN201910922865A CN111009573A CN 111009573 A CN111009573 A CN 111009573A CN 201910922865 A CN201910922865 A CN 201910922865A CN 111009573 A CN111009573 A CN 111009573A
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major surface
semiconductor device
pad
semiconductor
layer
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C.冯科布林斯基
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

半导体器件、半导体部件和制造半导体器件的方法。在实施例中，半导体器件包括半导体本体，该半导体本体包括第一主表面、与第一主表面相对的第二主表面和至少一个晶体管器件结构，布置在第一主表面上的源极焊盘和栅极焊盘，耦合到另外的器件结构的漏极焊盘和至少一个另外的接触焊盘。漏极焊盘和至少一个另外的接触焊盘布置在第二主表面上。

Description

半导体器件、半导体部件和制造半导体器件的方法
背景技术
晶体管在功率电子应用中用于切换。用于功率应用的常见晶体管器件包括SiCoolMOS®、Si功率MOSFET和Si绝缘栅双极晶体管（IGBT）。垂直MOSFET具有垂直漂移路径并且包括半导体管芯的上表面上的源极焊盘和栅极焊盘以及下表面上的漏极焊盘，所述半导体管芯包括晶体管结构。
US 2014/0319602 A1公开了一种具有两个电隔离区的半导体管芯。功率晶体管布置在第一区中并且栅极驱动晶体管布置在第二区中。
包括除了用于功率切换的功率晶体管的主要功能之外的附加功能的器件是期望的。
发明内容
在实施例中，半导体器件包括半导体本体，该半导体本体包括第一主表面、与第一主表面相对的第二主表面和至少一个晶体管器件结构，布置在第一主表面上的源极焊盘和栅极焊盘，耦合到另外的器件结构的漏极焊盘和至少一个另外的接触焊盘。漏极焊盘和至少一个另外的接触焊盘布置在第二主表面上。
在实施例中，制造半导体器件的方法包括提供半导体本体，该半导体本体包括第一主表面，与第一主表面相对的第二主表面，至少一个晶体管器件结构，另外的器件结构，布置在第一主表面上的源极焊盘和栅极焊盘，以及布置在第二主表面上的、包括一个或多个不连续部分（discrete portion）的绝缘层。该方法还包括将光致抗蚀剂层沉积到半导体本体的第二主表面上，增加光致抗蚀剂层的预定区域的表面粗糙度并产生表面轮廓，等离子蚀刻半导体本体，由此光致抗蚀剂层的表面轮廓被转移到半导体本体的第二主表面上，使得第二主表面在与绝缘层的不连续部分横向相邻的区中被粗糙化，在粗糙化的区上和绝缘层的不连续部分上沉积种子层，将导电层沉积在种子层上，构造（structure）种子层和导电层并且在第二主表面上形成漏极焊盘和至少一个另外的接触焊盘，该另外的接触焊盘被电耦合到另外的器件结构。
在阅读以下详细描述时并且在查看附图时，本领域技术人员将认识到附加的特征和优势。
附图说明
附图的元素不一定相对于彼此按比例。相同的附图标记表示相应的类似部分。可以组合各种示出的实施例的特征，除非它们彼此排斥。示例性实施例在附图中被描绘并且在下面的描述中被详细说明。
图1示出了根据一个实施例的半导体器件的截面视图。
图2示出了根据一个实施例的半导体器件的部分截面视图。
图3示出了半导体器件的后表面的透视图。
图4示出了安装在封装中的半导体器件的透视图。
图5a示出了根据一个实施例的半导体器件的后表面上的接触焊盘的截面视图。
图5b示出了根据一个实施例的半导体器件的后表面上的接触焊盘的截面视图。
图6a至6f示出了用于制造半导体器件的方法。
图7a至7e示出了增加半导体器件的表面的表面粗糙度的方法。
图8示出了用于制造半导体器件的方法的流程图。
具体实施方式
在以下详细描述中，参考了附图，附图形成了详细描述的一部分，并且其中通过图示的方式示出了可以实践本发明的具体实施例。在这方面，参考所描述的图的取向使用方向术语，诸如“顶部”、“底部”、“前部”、“后部”、“头部（leading）”、“尾部（trailing）”等。由于实施例的部件可以定位在许多不同的取向上，所以方向术语用于说明的目的并且绝不是不是限制性的。应当理解，在不脱离本发明的范围的情况下，可以利用其他实施例并且可以进行结构或逻辑改变。以下详细描述不被视为具有限制意义，并且本发明的范围由所附权利要求书来限定。
下面将解释多个示例性实施例。在该情况下，相同的结构特征由图中相同或相似的附图标记标识。在本说明书的上下文中，“横向”或“横的方向”应被理解为意味着大致平行于半导体材料或半导体载体的横向范围延伸的方向或程度。因此，横向方向大致平行于这些表面或侧面延伸。与此相对，术语“垂直”或“垂直方向”被理解为意味着大致垂直于这些表面或侧面并因此垂直于横的方向延伸的方向。因此，垂直方向在半导体材料或半导体载体的厚度方向上延伸。
如在本说明书中所采用的，当诸如层、区或衬底之类的元素被称为在另一元素“上”或延伸到另一元素“上”时，它可以直接在另一元素上或直接延伸到另一元素上，或也可能存在中间元素。相对地，当元素被称为“直接在”另一元素“上”或“直接”延伸到另一元素“上”时，不存在中间元件。
如在本说明书中所采用的，当元素被称为“连接”或“耦合”到另一元素时，它可以直接连接或耦合到另一元件，或者可能存在中间元素。相对地，当元素被称为“直接连接”或“直接耦合”到另一元素时，不存在中间元件。
图1示出了根据一个实施例的半导体器件10的截面视图。半导体器件10包括半导体本体11，半导体本体11包括第一主表面12和与第一主表面12相对的第二主表面13。半导体本体11包括至少一个晶体管器件结构14。半导体本体11可以被称为半导体管芯或半导体芯片。半导体器件10包括布置在第一主表面上的源极焊盘15和栅极焊盘16以及布置在第二主表面13上的漏极焊盘17。半导体器件10还包括布置在第二主表面13上的另外的接触焊盘18。如线19所示意性指示的，另外的接触焊盘18耦合到另外的器件结构20。
晶体管器件14可以是电源开关，并且可以是垂直FET（场效应晶体管）器件，例如具有垂直漂移路径的MOSFET，具有布置在半导体本体11的相对主表面上的源极焊盘15和漏极焊盘16。
另外的器件结构20位于半导体本体11之中或之上。另外的器件结构20包括这样的结构：利用该结构可以改变例如电压或电流之类的器件的参数。另外的器件结构20可以包括子结构，利用该子结构可以改变器件的参数，例如通过施加电压、电流。在一些实施例中，另外的器件结构包括用于改变驱动信号的子结构。驱动信号可以是施加到半导体器件10的晶体管器件14的栅极驱动信号。晶体管器件14可以提供功率切换。在一些实施例中，另外的器件结构或子结构20可用于增加半导体本体11中的晶体管器件14的切换频率。
另外的器件结构20可以与晶体管器件结构14并且与半导体本体11的其余部分物理地分离并电隔离。
半导体器件10包括第二主表面13，其通常被称为半导体本体11的后表面，其包括除了由漏极焊盘17提供的开关晶体管器件结构功能之外的附加功能。半导体器件10可被描述为具有功能化的后表面。该布置在半导体器件10用在所谓的源极向下布置（source downarrangement）中的实施例中可能是有用的，在所谓的源极向下布置中，源极焊盘15和栅极焊盘16面向诸如引线框架之类的再分布衬底并且安装在诸如引线框架之类的再分布衬底上，并且漏极焊盘17背向再分布衬底面向上。通过在第二主表面13上包括一个或多个另外的接触焊盘18，其在半导体管芯11的源极向下位置面向上，不得不由再分布衬底提供的导电再分布迹线或引线的数量可以被减少到例如仅源极焊盘15和栅极焊盘16，并且增加通过其他手段电接触的第二主表面13上的接触焊盘的数量。通过使用诸如例如接合线、接触夹（contact clip）连接之类的附加的电连接器可以更简单地实现提供到向上面对的表面的电连接，所述表面现在是第二主表面13。
半导体器件10不限于如例如针对MOSFET器件的情况具有被表示为源极、漏极和栅极的接触焊盘的晶体管器件21。半导体管芯还可以包括例如绝缘栅双极晶体管（IGBT）或双极结晶体管（BJT），对于此，这些元件的术语通常不同于用于MOSFET器件的术语。在该情况下，对于IGBT器件，源极是发射极并且漏极是集电极。对于BJT器件，源极是发射极，漏极是集电极接触焊盘并且栅极是基极。因此，如本文所用，“源极”还包括发射极，“漏极”还包括集电极并且“栅极”还包括基极，其对于该类型的晶体管器件是适当的。
图2示出了根据一个实施例的半导体器件30的部分截面视图。半导体器件30具有半导体本体31，该半导体本体31包括第一主表面和第二主表面32，第一主表面在图2的部分截面视图中不可见，第二主表面32与第一主表面相对。如在图1中示出的实施例中，半导体本体31包括至少一个晶体管器件结构33和至少一个另外的器件结构34。漏极焊盘35和与漏极焊盘35横向地隔开的另外的接触焊盘36布置在第二主表面32上。晶体管器件结构33可以是用于功率切换的垂直功率晶体管器件。
另外的接触焊盘36通过绝缘层37与半导体本体31间隔开并且与半导体本体31电绝缘，绝缘层37布置在另外的接触焊盘36和第二主表面32之间。绝缘层37可以具有限定的区域并且被认为是为绝缘层37的不连续部分。漏极接触焊盘35可以直接被定位在第二主表面32上，以便制造到位于半导体本体31的第二主表面32处的晶体管器件33的漏极区的低欧姆连接。
在一些实施例中，半导体器件30可以包括导电通孔38，导电通孔38电耦合到另外的接触焊盘36并且与半导体本体31电绝缘。导电通孔38可被用于将另外的接触焊盘36耦合到另外的器件结构34。
导电通孔38可由通孔或过孔39提供，通孔或过孔39定位在半导体本体31中并且由半导体本体31的材料限定。过孔39衬有（line）绝缘材料40，并且导电材料41定位在过孔39中并且通过绝缘层40与半导体本体31电绝缘，以形成导电通孔38。绝缘层40可以与布置在半导体管芯31的第二主表面32上的绝缘层37接触，并且导电材料41可以与另外的接触焊盘36接触。
绝缘层37包括包含孔42的不连续部分。在一些实施例中，另外的接触焊盘36可以延伸到开口42中并与位于导电通孔38中的导电材料41接触。另外的接触焊盘36由于布置在半导体本体31的第二主表面32和另外的接触焊盘36之间的绝缘层37并且由于导电通孔38的绝缘衬里（lining）40而不与半导体本体31直接接触。
在其他实施例中，另外的接触焊盘36延伸到孔42中并且与半导体本体31的第二主表面32接触。例如，另外的器件结构34可以定位在后表面32处，使得延伸到开口42中的另外的接触焊盘36的该部分与另外的器件结构34接触。另外的器件结构34可以与晶体管结构33电隔离。例如，另外的器件结构34可以布置在衬有绝缘层的半导体本体31中的井（well）中。另外的接触焊盘36可以通过环形不连续绝缘层37与半导体本体31的第二主表面32的周围部分间隔开。
绝缘层37的不连续部分可以被认为具有围绕孔42的环形。外轮廓可以具有不同的形式，例如正方形、矩形、圆形或六边形。在一些实施例中，例如，不连续部分可以具有U形，使得接触焊盘36定位在U形绝缘层上并延伸到由U形的臂提供的开口中以与第二主表面32或导电通孔接触。在一些实施例中，绝缘层37的不连续部分包括从环形的至少一侧延伸的延长。不连续部分可以具有L形或伸长的形状，具有定位在远端处的孔或开口。在该实施例中，可以认为环形的孔不对称地位于绝缘层的不连续部分中。环形可具有与延长不同的或相同的厚度。另外的接触焊盘36可以延伸到延长上以增加其横向区域，同时保持与位于下方的半导体本体31的电绝缘。
在一些实施例中，半导体器件30的半导体本体31的第二主表面32包括粗糙化的表面。在一些实施例中，整个第二主表面包括粗糙化的表面。在一些实施例中，外围区比第二主表面的中心区更光滑，即具有更低的表面粗糙度。
在一些实施例中，诸如图2中所示的实施例中，第二主表面32的预定义区被粗糙化以形成粗糙化的区43，并且第二主表面32的其他部分保持未被粗糙化（unroughened）并形成未被粗糙化的区44。未被粗糙化的部分44具有比粗糙化的区43低的表面粗糙度。一个或多个未被粗糙化的区44可以位于第二主表面32的外围，例如在切口（kerf）区45中或在被绝缘层37并且特别是绝缘层37的不连续部分覆盖的第二主表面32的区中。
在一些实施例中，粗糙化的表面43被提供在第二主表面32的未被绝缘层37覆盖的区中。粗糙化的表面43可以位于漏极焊盘35之下。
在一些实施例中，种子层46位于粗糙化的表面43上并且漏极接触焊盘35位于种子层46上。在一些实施例中，种子层46位于绝缘层37上并形成另外的接触焊盘36的部分。种子层也可以布置在第二主表面的未被粗糙化的区44 上。
粗糙化的表面43可用于增加例如漏极接触焊盘35之类的接触焊盘中的一个或多个与半导体本体31的粘附力（adhesion）。
图3示出了半导体本体的后表面上的不连续绝缘部分的实施例。作为示例，示出了图2的半导体本体31的后表面32。作为示例示出了不连续绝缘区37的三种不同形式。在实施例中，不连续绝缘区37'具有闭合的均匀结构，并且可以具有正方形或矩形形式。不连续部分37'可以具有从正方形或矩形变化的横向形式，例如，它可以具有圆形、椭圆形、六边形区或不规则形式。
在另一实施例中，不连续绝缘区37’’具有围绕开口42的环形式47，其中半导体本体的第二主表面32的一部分暴露于该开口42中。在另一实施例中，不连续部分37’’’具有环形形式47以及整体延长48，环形形式47具有开口42，在开口42中暴露第二主表面32。延长48可以具有基本上正方形或矩形形状。然而，延长48可以具有其他形式，例如圆形或半圆形。在一些实施例中，不连续部分37’’’的横向轮廓可以是L形的，具有位于分支（limb）之一中的开口42。
在其中两个或更多不连续的绝缘区布置在表面上的实施例中，两个或更多不连续的绝缘区可以具有相同或不同的形状。
图4示出了安装在封装52中的半导体器件51的布置50的透视图。封装52包括导电再分布结构53，其可以具有位于绝缘板上的导电迹线或引线框架的形式。封装52还包括模制（moulding）形式的壳体，其可以包括例如环氧树脂，其在图4中未示出。半导体器件51包括在图4中不能看到的晶体管器件结构、在其第一主表面54上的栅极焊盘和源极焊盘以及在其第二主表面56上的漏极焊盘55。半导体器件51的第一主表面54向下面向再分布结构53的上表面59，使得在图4的透视图中不能看到源极焊盘和栅极焊盘。半导体器件51安装在再分布衬底53上，使得栅极焊盘通过例如焊接连接之类的导电连接安装在第一迹线57上，并且使得通过诸如焊接连接之类的导电连接使源极焊盘安装在第二迹线58上并连接到第二迹线58。导电迹线57与导电迹线58间隔开。
第二主表面56上的漏极焊盘55背离再分布结构53面向上并且电连接到再分布结构53的第三导电部分59，该第三导电部分59通过导电连接器60与半导体器件51间隔开并且与半导体器件51相邻。例如，导电连接器60可以具有接触夹或一个或多个接合线的形式。
半导体器件51具有包括漏极焊盘55和连接到半导体器件51内的一个或多个另外的器件结构的一个或多个另外的接触焊盘61、62的第二主表面56。因此，第二主表面56提供除了半导体器件51的晶体管器件的漏极焊盘55的功能之外的附加功能。
除了漏极焊盘55之外，半导体器件51的第二主表面56包括两个另外的接触焊盘61、62。第一接触焊盘61位于具有环形式的不连续绝缘区63上。接触焊盘61布置在绝缘区63上并延伸到由环形式限定的开口64中。接触焊盘64的外表面基本上是平面的，使得由环形不连续部分63限定的开口64基本上填充有导电材料。接触焊盘61电耦合到半导体器件51内的另外的器件结构。接触焊盘61通过接合线59电耦合到再分布结构53的未示出的部分。
接触焊盘62布置在绝缘层的不连续部分65上。不连续部分65具有有环形式66的一部分和从环66的一侧延伸的延长67。环形式66限定开口68，接触焊盘62延伸到开口68中。接触焊盘62在延长部分67之上延伸，这提供了用于附接接合线69的增加的面积。接合线69定位在接触焊盘62上并且与环部分66中的开口68横向相邻并且与接触焊盘62和第二主表面56之间形成的电连接横向相邻定位。通过延长67 使能的接触焊盘62的增加的面积使得能够更容易地形成接合线69。不连续绝缘部分65、接触焊盘62和接合线69的该布置可以用于避免在形成接合线69期间对接触焊盘62电耦合到的下面的器件结构的损坏，因为接合线69位于绝缘层65上，绝缘层65位于接触焊盘62和半导体器件51的第二主表面56之间。
可以使用不同类型的电连接将第二后表面56上的接触焊盘61、62连接到再分布层的部分。例如，漏极焊盘55可以通过诸如接触夹之类的大面积导电连接器连接到再分布结构53的部分59，并且接触焊盘61、62中的每个可以通过接合线耦合到再分布结构53的部分。在其他实施例中，相同类型的连接器可以用于每个接触焊盘。在一些实施例中，对于每个接触焊盘，连接器的类型可以基本上相同，但大小不同。例如，接合线的直径可以针对接触焊盘中的一个或多个而变化。例如，一个或多个另外的接触焊盘61、62可通过具有比将漏极焊盘55连接到再分布结构53的接合线或导线更小的直径的接合线连接到再分布结构53。
图5a和5b示出了不同形式的两个另外的接触焊盘的截面视图。图4中示出的另外的接触焊盘61、62用作不同形式的示例。
图5a示出了另外的接触焊盘62的截面视图，并且示出了接触焊盘62的导电材料延伸到绝缘层65中的开口68中并且延伸到与开口68横向相邻布置的延长部分67上。接触焊盘62具有少于不连续绝缘部分65的横向范围的横向范围，使得不连续绝缘部分65从另外的接触焊盘62的导电材料横向向外突出。该布置可以用于辅助增加接触焊盘62与半导体器件51的电隔离。
不连续绝缘部分65中的开口68具有宽度β。根据另外的接触焊盘62应该耦合到的半导体本体51中的结构70的横向大小来选择宽度β。例如，在接触焊盘62下面的结构70可以包括耦合到另外的器件结构的导电接触通孔。该类型的结构70相对小，使得绝缘层的不连续部分65和接触焊盘62的横向形状增加了接合线69可以连接到的可用面积。接合线69与结构70横向相邻定位并与结构70间隔开。另外的接触焊盘62和不连续的绝缘层65与漏极接触焊盘55分离距离γ。可以根据接触焊盘55、62在操作中所经受的电位差异来选择距离γ。
图5b示出了接触焊盘61和绝缘部分63的截面视图。接触焊盘61在孔64的大小β方面相对于接合线69的大小和下面的结构70与接触焊盘62不同。在图5B所示的实施例中，结构70和开口64大于接合线69所需的接合面积。在该实施例中，接合线69直接位于结构70的上方。
参考图6a至6f描述了一种制造具有功能化后表面的半导体器件的方法。
图6a至6f示出了包括多个器件位置81的半导体晶片80，多个器件位置81通过切口区82横向分离。可以以行和网格布置器件位置81，使得切口区82形成为正方形或矩形网格。
在一些实施例中，切口区82可以包括晶片80的半导体材料。在其他实施例中，切口区82'可以包括绝缘材料，其可以延伸遍及半导体晶片80的整个厚度。
图6a示出了位于载体83上的半导体晶片80，使得例如使用粘合剂将通常称为前侧的其第一主表面84固定到载体83的表面85上。已经处理了半导体晶片80的器件位置81，使得第一主表面84包括源极焊盘86和漏极焊盘87。在该阶段可以完成前侧84的处理。
如图6b中所示，绝缘介电层88被施加到半导体晶片80的第二主表面89并且然后被构造成在每个器件位置81中提供一个或多个不连续部分90，如图6c中所示。
在一些实施例中，然后将第二主表面89粗糙化。在一些实施例中，第二主表面89的选择的区域被粗糙化。如图6d中所示，在这些实施例中，结构化掩模91可以被施加到第二主表面89，以覆盖还未被处理、即未被粗糙化的第二主表面89的区。例如，掩模91可以覆盖切口区82和器件位置81的外围边缘区。掩模91还可以覆盖绝缘层的不连续部分90。然后可以使第二主表面89遭受粗糙化处理，使得保持未被掩模91覆盖的区92具有与由掩模91覆盖的第二主表面89的区93相比增加的表面粗糙度。
在一些实施例中，通过施加光致抗蚀剂层并在空间上不均匀地固化光致抗蚀剂层来进行粗糙化过程，从而增加光致抗蚀剂层的表面粗糙度。然后使晶片80经受等离子蚀刻过程，使得光致抗蚀剂层的粗糙化的表面的表面轮廓被转移到第二主表面89。将第二主表面89粗糙化的该方法将参考图7a至7e更详细地描述。
如图6e中所示，如果使用掩模，则用于制造半导体器件的方法通过在粗糙化过程之后去除掩模91来继续。例如通过溅射，将种子层93沉积到第二主表面89并且通过将另外的导电层94施加到种子层93来增加种子层93的厚度。
例如，可以通过溅射或电镀来沉积另外的导电层94。种子层93和导电层94沉积在绝缘层的不连续部分90上以及沉积在第二主表面89的暴露部分上。如图6f中所示，导电层94和种子层93可以被构造为在每个器件位置81中在第二后表面89上产生一个或多个另外的接触焊盘96和漏极接触焊盘95。切口区82保持没有导电层。
替代地，可以使用单个导电层形成接触焊盘55、61、62。替代地，可以选择性地沉积导电层94以在连续种子层93上或在选择性沉积的种子层上形成接触焊盘55、61、62。
图7a至7e示出了用于参照图6a至6f的半导体晶片80的用于控制表面的预定区的表面粗糙区域的方法的实施例。
如图7a中所示，将掩模91施加到已经沉积在半导体晶片80的表面89上的光致抗蚀剂层98的最外表面97，由此光致抗蚀剂层98的表面97和衬底80的表面89两者都具有初始的表面粗糙度。掩模91包括开口92，光致抗蚀剂层98的区暴露在该开口92中。使该布置经受照射（illumination），由此通过掩模91暴露的并形成开口92的基部的光致抗蚀剂层98的区域92在空间上被不均匀地照射并且在空间上被不均匀地固化，使得掩模91中的开口92中的光致抗蚀剂层98的表面粗糙度增加。被掩模91覆盖的光致抗蚀剂层98的区域93基本上不受等离子蚀刻过程的影响。在去除掩模91之后，光致抗蚀剂层98具有表面轮廓97'，其具有预定义区域99、100，其具有不同的表面粗糙度。由掩模91覆盖的区域99具有比在掩模91的开口92中被照射和定位的区域100更低的表面粗糙度。如图7b中所示，沉积后，区域100具有比光致抗蚀剂层98的表面97的初始表面粗糙度更高的表面粗糙度。
然后使图7b中所示的中间产品经受等离子蚀刻，使得光致抗蚀剂层91的表面轮廓97'转移到晶片80的表面89，因此产生具有比晶片80的第二主表面89的其他区域101更高的表面粗糙度的一个或多个区域102，如图7c中所示。
在一些实施例中，在晶片80的粗糙化的区域102中形成的表面轮廓可以由具有不同比例的尺寸的两种不同类型的特征来表征。
图7d示出了平面视图并且图7e示出了根据参照图7a至7c描述的方法已经被粗糙化的表面89的截面视图。第二主表面89的粗糙化区域102包括第一类型的特征103和第二类型的特征104。第一类型的特征103比第二类型的特征104粗糙得多。第一类型的特征103由形成大峰和谷的多个坑（crater）形成的。第二类型的特征104在粗糙的第一表面特征103上形成表面特征。例如，第一表面特征103可以具有5
Figure DEST_PATH_IMAGE001
的平均大小，并且第二特征104具有200 nm的平均大小。
在一些实施例中，第一特征103具有在区域A1之上测量的表面粗糙度Ra1，并且第二表面特征104具有在区域A2之上测量的第二表面粗糙度Ra2。区域A2完全位于区域A1内，使得区域A1大于区域A2。在一些实施例中，Ra1≠Ra2。在一些实施例中，Ra1大于Ra2。在一些实施例中，第二主表面89具有在区域A1外部的表面粗糙度Ra3，由此，表面粗糙度Ra3小于表面粗糙度Ra2并且小于表面粗糙度Ra1。例如，切口区82可以具有粗糙度Ra3，并且晶片80的区域102可以具有如图7d和7e中所示的表面形态。
衬底80的表面89可以具有初始粗糙度Rai，其在在一些实施例中位于1至10 nm的范围内。表面89的粗糙化的区域102可以具有算术表面粗糙度Ra，其位于10 nm至500 nm或75nm至350 nm的范围内。
如本文所用，表面粗糙度或Ra是指算术粗糙度。这里给出的表面粗糙度的任何值都是指算术粗糙度。算术粗糙度Ra是绝对测量的轮廓值的算术平均值，并且可以用作表面轮廓的粗糙度幅度的整体测量。针对线轮廓计算算术平均Ra。区域的算术平均值表示为Ra2D。
该表面粗糙化方法包括增加沉积在衬底的表面上的光致抗蚀剂层的初始表面粗糙度，从而增加光致抗蚀剂层的表面粗糙度，以产生然后转移到衬底的表面的光致抗蚀剂层上的表面轮廓，使得衬底的表面被粗糙化并且具有高于衬底的初始表面粗糙度的表面粗糙度。
光致抗蚀剂层98的光可限定（photodefinable）或光致结构化（photostructurable）性质可用于增加光致抗蚀剂层98的最外表面97的表面粗糙度。
用于增加光致抗蚀剂层98的表面粗糙度的装置可以包括用于照射位于晶片80的表面89上的光致抗蚀剂层98 的光源。滤光器可以放置在光源和光致抗蚀剂层98之间，并且来自光源的光通过滤波器21被引导并且被引导到达光致抗蚀剂层98的最外表面97上，使得光致抗蚀剂层98在空间上非均匀地受到来自光源的光的照射并因此在空间上不均匀地固化。
如本文所用，在空间上不均匀地指面积以及深度，并因此在三维上非均匀地固化光致抗蚀剂层98。根据光致抗蚀剂是正还是负抗蚀剂，可以例如使用合适的化学溶液去除光致抗蚀剂层98的固化的或未固化的区。
因此，该方法利用光致抗蚀剂层98 的材料性质，即其光可限定性（photodefinability），产生表面轮廓97'，然后将其转移到晶片80的表面89上，在等离子蚀刻过程期间，光致抗蚀剂层98位于该表面98上。
图8示出了用于制造半导体器件的方法的流程图110。提供半导体本体。半导体本体包括第一主表面、与第一主表面相对的第二主表面、至少一个晶体管器件结构、另外的器件结构、布置在第一主表面上的源极焊盘和栅极焊盘以及包括布置在第二主表面上的一个或多个不连续部分的绝缘层。在框111中，将光致抗蚀剂层沉积到半导体本体的第二主表面上。在框112中，增加光致抗蚀剂层的预定义区域的表面粗糙度并产生表面轮廓。表面轮廓向光致抗蚀剂层提供外表面，其具有在光致抗蚀剂层的外表面的初始粗糙度之上的增加的粗糙度。通过在空间上不均匀地照射光致抗蚀剂层以产生光致抗蚀剂层的空间上不均匀的固化可以增加光致抗蚀剂层的表面粗糙度。在框113中，对半导体本体进行等离子蚀刻，其中光致抗蚀剂层就位于第二主表面上，由此光致抗蚀剂层的表面轮廓被转移到半导体本体的第二主表面，使得第二主表面与绝缘层的不连续部分横向相邻的区中被粗糙化。在一些实施例中，将结构掩模施加到光致抗蚀剂层，使得光致抗蚀剂层的预定义区被粗糙化，并且光致抗蚀剂层的被覆盖区保持未被粗糙化。在框114中，将种子层沉积在粗糙化的区上并且沉积在绝缘层的不连续部分上。在框115中，在种子层上沉积导电层。在一些实施例中，种子层和导电层在单个过程中形成。种子层和导电层可以形成在绝缘层的不连续部分上以及形成在半导体器件的第二主表面上。在框116中，构造种子层和导电层，并且在第二主表面上形成漏极焊盘和至少一个另外的接触焊盘，该另外的接触焊盘电耦合到另外的器件结构。漏极焊盘可以在其整个横向区域上与第二主表面直接接触，而另外的接触焊盘的至少一部分通过绝缘层的不连续部分与第二主表面间隔开。
为了便于描述，使用诸如“下面”、“下”、“下部”、“上面”、“上”以及诸如此类的空间相对术语来解释一个元素相对于第二元素的定位。除了与图中所示的取向不同的取向之外，这些术语旨在包括器件的不同取向。此外，诸如“第一”、“第二”以及诸如此类的术语也用于描述各种元素、区域、部分等，并且也没有意图进行限制。相同的术语贯穿说明书指代相同的元素。
如本文所用，术语“具有”、“含有”、“包括”、“包含”以及诸如此类是开放式术语，其表明所述元素或特征的存在，但不排除附加元素或特征。除非上下文另有明确说明，否则冠词“一”、“一个”和“该”旨在包括复数以及单数。应当理解，除非另外特别说明，否则本文描述的各种实施例的特征可以彼此组合。
尽管这里已经说明和描述了特定实施例，但是本领域普通技术人员应当理解，在不脱离本发明范围的情况下，可以用各种替代和/或等同实现方案来替代所示出和描述的特定实施例。本申请旨在涵盖本文所讨论的具体实施例的任何改编或变化。因此，本发明旨在仅由权利要求书及其等同物限制。

Claims (15)

1.一种半导体器件，包括：
半导体本体，包括第一主表面、与第一主表面相对的第二主表面和至少一个晶体管器件结构；
布置在第一主表面上的源极焊盘和栅极焊盘；
耦合到另外的器件结构的至少一个另外的接触焊盘和漏极焊盘，漏极焊盘和至少一个另外的接触焊盘被布置在第二主表面上。
2.根据权利要求1所述的半导体器件，还包括绝缘层，其中另外的接触焊盘通过布置在另外的接触焊盘和第二主表面之间的绝缘层的不连续部分与半导体本体电绝缘。
3.根据权利要求1或权利要求2所述的半导体器件，还包括导电通孔，所述导电通孔电耦合到另外的接触焊盘并且与半导体本体电绝缘。
4.根据权利要求2或权利要求3所述的半导体器件，其中绝缘层包括包含孔的不连续部分，并且另外的接触焊盘延伸到孔中并与第二主表面接触。
5.根据权利要求2至4中任一项所述的半导体器件，其中绝缘层的不连续部分包括环形。
6.根据权利要求5所述的半导体器件，其中不连续部分还包括从环形的至少一侧延伸的延长。
7. 根据权利要求2至6中任一项所述的半导体器件，其中第二主表面还包括：
在未被绝缘层覆盖的区中的粗糙化的表面，和
在粗糙化的表面上的种子层，
其中，另外的接触焊盘布置在种子层上。
8.根据权利要求7所述的半导体器件，其中第二主表面还包括至少一个未被粗糙化的区。
9.根据权利要求8所述的半导体器件，其中未被粗糙化的区布置在切口区中和/或绝缘层下方。
10. 一种半导体部件，包括：
根据权利要求1至9中任一项所述的半导体器件，以及
具有导电再分布结构的衬底，
其中，
半导体本体的第一主表面面向导电再分布结构，
漏极焊盘通过接合线或接触夹被电耦合到导电再分布结构的第一部分，
另外的接触焊盘通过接合线被电耦合到导电再分布结构的第二部分。
11.一种制造半导体器件的方法，包括：
提供半导体本体，所述半导体本体包括第一主表面、与第一主表面相对的第二主表面、至少一个晶体管器件结构、另外的器件结构、布置在第一主表面上的源极焊盘和栅极焊盘以及布置在第二主表面上的包括一个或多个不连续部分的绝缘层；
将光致抗蚀剂层沉积到半导体本体的第二主表面上，
增加光刻胶层的预定义区域的表面粗糙度并产生表面轮廓；
等离子蚀刻半导体本体，由此光致抗蚀剂层的表面轮廓被转移到半导体本体的第二主表面，使得第二主表面在与绝缘层的不连续部分横向相邻的区中被粗糙化；
在粗糙化的区上并且在绝缘层的不连续部分上沉积种子层；
在种子层上沉积导电层；
构造种子层和导电层并在第二主表面上形成漏极焊盘和至少一个另外的接触焊盘，另外的接触焊盘电耦合到另外的器件结构。
12.根据权利要求11所述的方法，还包括在空间上不均匀地照射光致抗蚀剂层以增加光致抗蚀剂层的表面粗糙度。
13. 根据权利要求12所述的方法，其中，在空间上不均匀地照射光致抗蚀剂层包括：
在光源和光致抗蚀剂层之间放置滤光器，以及
通过滤光器将光引导到光致抗蚀剂层上。
14.根据权利要求13所述的方法，其中滤光器是不透明玻璃。
15.根据权利要求11至14中任一项所述的方法，还包括：
将掩模施加到第二主表面并覆盖绝缘层的不连续部分和第二主表面的预定义区；
照射掩模未覆盖的光致抗蚀剂层的区域以增加光致抗蚀剂层的这些区域的表面粗糙度。
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