CN110892513B - 具有相等栅极堆叠厚度的垂直传输晶体管 - Google Patents

具有相等栅极堆叠厚度的垂直传输晶体管 Download PDF

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CN110892513B
CN110892513B CN201880026997.4A CN201880026997A CN110892513B CN 110892513 B CN110892513 B CN 110892513B CN 201880026997 A CN201880026997 A CN 201880026997A CN 110892513 B CN110892513 B CN 110892513B
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CN110892513A (zh
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鲍如强
李忠贤
徐铮
毕振兴
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International Business Machines Corp
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Abstract

半导体器件及其形成方法包括在第一类型区域和第二类型区域中的底部源极/漏极层上形成垂直半导体沟道。栅极介电层形成在垂直半导体沟道的侧壁上。在第一类型区域中形成第一类功函数层。在第一类型区域和第二类型区域中形成第二类功函数层。在第二类型区域中形成厚度匹配层，使得第一类型区域中的层堆叠具有与第二类型区域中的层堆叠相同的厚度。顶部源极/漏极区域形成在垂直沟道的顶部部分上。

Description

具有相等栅极堆叠厚度的垂直传输晶体管
技术领域
本发明一般涉及晶体管制造，更具体地，涉及在器件类型之间具有一致的栅极厚度的垂直传输晶体管的制造。
背景技术
随着制造技术的改进，已经采用场效应晶体管(FET)来缩小器件尺寸。垂直传输FET为进一步的器件缩放提供了机会。然而，形成具有相等栅极厚度的器件在用于垂直传输FET的高k/金属栅极制造工艺中特别重要，以减少栅极凹陷期间的栅极变化。这限定了栅极长度，并且具有一致的栅极长度有助于减少栅极封装和栅极隔离的挑战。
发明内容
一种用于形成半导体器件的方法包括在第一类型区域和第二类型区域中的底部源极/漏极层上形成垂直半导体沟道。栅极介电层被形成在垂直半导体沟道的侧壁上。第一类功函数层被形成在第一类型区域中。第二类功函数层被形成在第一类型区域和第二类型区域两者中。厚度匹配层被形成在第二类型区域中，使得第一类型区域中的层堆叠具有与第二类型区域中的层堆叠相同的厚度。顶部源极/漏极区域被形成在垂直沟道的顶部部分上。
一种用于形成半导体器件的方法包括在第一类型区域和第二类型区域中的底部源极/漏极层上形成垂直半导体沟道。栅极介电层被形成在垂直半导体沟道的侧壁上。第一类功函数层被形成在第一类型区域中。第二类功函数层被形成在第一类型区域和第二类型区域两者中。厚度匹配层被形成在第二类型区域中，使得第一类型区域中的层堆叠具有与第二类型区域中的层堆叠相同的厚度。由第一类功函数层和第二类功函数层形成的第一类型堆叠被凹陷在垂直半导体沟道的高度之下。由第二类功函数层和厚度匹配层形成的第二类型堆叠被凹陷在垂直半导体沟道的高度之下。间隔物被形成在垂直半导体沟道的暴露的侧壁上。隔离物被蚀刻以暴露每个垂直沟道的顶部部分。顶部源极/漏极区域被形成在垂直沟道的顶部部分上。
集成芯片包括第一类型的第一半导体器件和第二类型的第二半导体器件。第一半导体器件包括垂直半导体沟道、被形成在垂直半导体沟道的侧壁上的栅极介电层、被形成在栅极介电层上的第一类功函数层，以及被形成在第一类功函数层上的第二类功函数层。第二半导体器件包括垂直半导体沟道、被形成在垂直半导体沟道的侧壁上的栅极介电层、被形成在栅极介电层上的第二类功函数层，以及被形成在第二类功函数层上的厚度匹配层，该厚度匹配层的厚度大致等于第一类功函数层的厚度。
从以下对其说明性实施例的详细描述中，这些和其他特征和优点将变得明显，该详细描述将结合附图来阅读。
附图说明
图1是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直场效应晶体管(FET)的步骤的横截面图；
图2是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图3是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图4是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图5是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图6是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图7是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图8是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图9是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图10是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图11是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图12是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图13是根据本发明的实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图14是根据本发明替代实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图15是根据本发明替代实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；
图16是根据本发明替代实施例的形成具有相等栅极厚度的不同类型的垂直FET的步骤的横截面图；和
图17是根据本发明的实施例的用于形成具有相等栅极厚度的不同类型的垂直FET的工艺的框图/流程图。
具体实施方式
本发明的实施例提供垂直传输场效应晶体管(VTFET)结构，其通过使用相对于n型FET和p型FET之间的其他栅极堆叠中的金属的一个栅极金属的选择性蚀刻而具有相等的栅极厚度。每种器件类型都可以使用具有不同金属的不同栅极堆叠，从而可以蚀刻更厚的栅极堆叠以匹配其他器件类型所使用的栅极堆叠的厚度。
现在参考附图，其中相同的数字表示相同或相似的元件，并且首先参考图1，其示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。使用例如浅沟槽隔离工艺将衬底102划分为第一区域116和第二区域118，该浅沟槽隔离工艺切入衬底102并在沟槽中沉积介电阻挡层108。在一些实施例中，衬底102可以是半导体衬底。介电阻挡层108可以由例如二氧化硅或任何其他适当的材料形成。
半导体衬底102可以是体半导体衬底。在一个示例中，体半导体衬底可以是含硅材料。适用于体半导体衬底的含硅材料的说明性示例包括但不限于硅，硅锗，碳化硅锗，碳化硅，多晶硅，外延硅，非晶硅及其多层。虽然硅是晶片制造中主要使用的半导体材料，但是可以使用替代的半导体材料，诸如但不限于锗，砷化镓，氮化镓，碲化镉和硒化锌。尽管未在本图中示出，但半导体衬底102也可以是绝缘体上半导体(SOI)衬底。
底部源极/漏极层104被形成在衬底104上。底部源极/漏极层104由例如掺杂的半导体材料形成。半导体材料可以是与衬底102中使用的材料相同的材料，或者可以是不同的半导体材料。底部源极/漏极层104中使用的掺杂剂将取决于所形成的器件的类型。例如，n型器件可以被形成在第一区域116中并且将使用n型掺杂剂。可以在第二区域118中形成p型器件并使用p型掺杂剂。区域116和118中的每一个将具有不同的掺杂剂材料。掺杂剂材料可以通过例如注入添加。
如本文所用，“p型”是指向本征半导体中添加杂质，其产生价电子的缺陷。在含硅衬底中，p型掺杂剂(即杂质)的示例包括但不限于：硼，铝，镓和铟。如本文所用，“n型”是指向本征半导体中添加贡献自由电子的杂质。在含硅衬底中，n型掺杂剂(即杂质)的示例包括但不限于锑，砷和磷。
沟道鳍片112被形成在底部源极/漏极区104上。特别预期沟道鳍片112可以由硅形成，但是可以替代地使用任何其他适当的半导体材料。可以通过在底部源极/漏极层104上沉积半导体材料层，在层上沉积鳍状掩模114，并且各向异性地蚀刻鳍状掩模114周围的层来形成沟道鳍片。反应离子蚀刻(RIE)是一种形式的等离子体蚀刻，其中在蚀刻期间，将待蚀刻的表面放置在射频供电的电极上。在RIE期间，待蚀刻的表面具有加速从等离子体朝向表面提取的蚀刻物质的电势，其中化学蚀刻反应在垂直于表面的方向上发生。可以在本发明的这一点使用的各向异性蚀刻的其他示例包括离子束蚀刻，等离子体蚀刻或激光烧蚀。或者，沟道鳍片112可以通过间隔物成像转移形成。
在底部源极/漏极层104上方沉积隔离层106，以在沟道鳍片112之间提供电隔离。可以将任何适当的介电材料用于隔离层106，例如二氧化硅。然后在沟道鳍片112和隔离层106上共形地沉积一层栅极介电材料110。栅极介电材料层可以是任何适当的介电，包括例如高k介电。
如本文所用，术语“高k”是指介电常数k高于二氧化硅的介电常数的材料。高k材料的示例包括但不限于金属氧化物，例如氧化铪，氧化铪硅，氧氮化铪，氧化镧，氧化镧铝，氧化锆，氧化锆硅，氧氮化锆硅，氧化钽，氧化钛，钡锶钛氧化物，钡钛氧化物，锶钛氧化物，氧化钇，氧化铝，铅钪钽氧化物和铌酸铅锌。高k介电材料还可以包括掺杂剂，例如镧和铝。
可以通过任何适当的共形工艺来沉积栅极介电材料层110，包括例如化学气相沉积(CVD)，物理气相沉积(PVD)，原子层沉积(ALD)或气体团簇离子束(GCIB)沉积。CVD是一种沉积方法，其中由于气态反应物之间的化学反应在高于室温(例如，从约25℃至约900℃)下形成沉积物质。将反应的固体产物沉积在要在其上形成固体产物的膜、涂层或层的表面上。CVD工艺的变化包括但不限于大气压CVD(APCVD)，低压CVD(LPCVD)，等离子体增强CVD(PECVD)和金属有机CVD(MOCVD)，并且也可以采用它们的组合。在使用PVD的替代实施例中，溅射设备可以包括直流二极管系统，射频溅射，磁控溅射或电离金属等离子体溅射。在使用ALD的替代实施例中，化学前体一次一个地与材料表面反应以在表面上沉积薄膜。
现在参考图2，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横横截面图。在第二区域118中沉积p型栅极金属层202。该材料可以使用共形工艺沉积，诸如CVD，ALD或PVD，并且可以由适当的p型功函数材料形成，诸如例如，氮化钛。其他类型的p型功函数材料包括例如钛铝氮化物，钌，铂，钼，钴及其合金。p型栅极金属层可以被沉积在区域116和118中，并且随后通过掩蔽第二区域118而从第一区域116被蚀刻掉。
功函数材料是提供晶体管器件的阈值电压的偏移的层。特别地，p型功函数材料可以是使电压阈值朝向硅的价带移动的材料。在一个实施例中，p型功函数金属层的功函数范围为4.9eV至5.2eV。如本文所用，“阈值电压”是可达到的最低栅极电压，其通过使器件的沟道导电而导通半导体器件，例如晶体管。这里使用的术语“p型阈值电压偏移”是指p型半导体器件的费米能量朝向p型半导体器件的含硅衬底中的硅的价带的偏移。“价带”是电子能量的最高范围，其中电子通常以绝对零度存在。
本实施例利用不同区域中的不同功函数金属，其中一些层在不同区域中的器件之间共享。以这种方式，可以通过使用适当的金属来控制每个器件的电压阈值，而不会损害栅极厚度均匀性。
现在参考图3，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。n型功函数堆叠由例如氮化钛层302和钛铝碳化物层304形成。使用任何适当的工艺，诸如CVD，ALD或PVD，共形地沉积堆叠。n型功函数材料可以是在n型半导体器件中朝向硅的导带移动电压阈值的材料。
“导带”是掺杂材料的最低位电子能带，其未完全被电子填充。在一个实施例中，n型功函数金属层的功函数范围为4.1eV至4.3eV。在替代实施例中，n型功函数堆叠可以包括钛铝，氮化钽，氮化铪，铪硅或其组合的层。n型功函数堆叠的层可以通过任何适当的沉积工艺形成，包括例如CVD，ALD或PVD。
现在参考图4，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。匹配层402在第一区域116中由例如氮化钛形成。匹配层402可以通过例如在两个区域116和118上共形地沉积材料，掩蔽第一区域116，然后将材料从第二区域118蚀刻掉而形成。匹配层402的厚度被形成为使第一区域116的沟道鳍片112上的材料堆叠的厚度等于第二区域的沟道鳍片112上的堆叠材料的厚度。值得注意的是，匹配层的厚度将大致等于p型栅极金属层202的厚度。
在一个示例性实施例中，p型栅极金属层202可以具有介于约3nm与约5nm之间的示例性厚度，氮化钛层可以具有介于约0.5nm与约1.5nm之间的示例性厚度，钛铝碳化物层304可以具有介于约3nm和约5nm之间的示例性厚度，并且匹配层可以具有介于约3nm和约5nm之间的示例性厚度。第一区域116中的总厚度将是层302、304和402的总和，在该实施例中具有介于约6.5nm和约11.5nm之间的示例性范围。第二区域118中的总厚度将是层202、302和304的总和，具有与第一区域116中的层堆叠相同的厚度。
现在参考图5，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。在第一区域116和第二区域118上沉积一层平坦化材料。平坦化材料可以是例如有机平坦化层。将栅极金属层和功函数金属层与平坦化材料一起回蚀刻以形成蚀刻的栅极堆叠502。然后蚀刻掉平坦化材料以暴露栅极堆叠502。平坦化材料的使用用于保护鳍片112周围的栅极堆叠的水平部分。
现在参考图6，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。封装层602被共形地沉积在鳍片112和凹陷栅极堆叠502上。封装层602可以通过任何适当的沉积工艺形成，诸如CVD，PVD或ALD。封装层602提供对下游工艺中使用的氧气的屏障。封装层602可以由例如氮化硅、氮氧化硅或碳氮化硼硅形成。
现在参考图7，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。间隙电介质702被沉积在封装层602上方并且被凹陷回到栅极堆叠502的高度。特别考虑二氧化硅可以用于此目的，但是可以替代地使用任何适当的介电材料。间隙电介质702填充两个鳍片112之间的空间，并且可以使用任何适当的工艺沉积，包括例如CVD，PVD，ALD或具有可流动介电材料的旋涂工艺。
现在参考图8，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。在封装层602的暴露部分周围形成间隔物802。间隔物802可以通过例如沉积一层硬掩模材料然后各向异性地蚀刻硬掩模材料以从水平表面去除该材料而形成，仅留下间隔物802形成在封装层602外部的沟道鳍片112的垂直侧壁上。特别考虑间隔物802可以由氮化硅形成，但是可以替代地使用任何适当的介电材料。
现在参考图9，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。间隔物802和鳍状掩模114用作掩模，而栅极堆叠502的水平部分被各向异性地蚀刻掉。结果是在第一区域116中形成n型栅极堆叠902并且在第二区域118中形成p型栅极堆叠904。值得注意的是，n型栅极堆叠902的厚度等于p型栅极堆叠904的厚度，尽管它们的层和组成不同。
现在参考图10，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。在第一区域116和第二区域118上沉积一层介电填充物。特别考虑的是，介电填充物可以由例如二氧化硅形成，但是也可以使用任何适当的介电材料。蚀刻鳍状掩模114、介电填充物和间隔物802以暴露沟道鳍片112的顶部部分，从而在第一区域116和第二区域118之间留下介电层1002。
现在参考图11，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。顶部源极/漏极区域1102和1104被形成在沟道鳍片112的顶部部分上。特别考虑顶部源极/漏极区域1102和1104可以外延生长并且可以具有与沟道鳍片112和底部源极/漏极层104相同的基本组成，但应该理解，顶部源极/漏极区域1102和1104可以由任何适当的材料形成，并且可以通过任何适当的工艺形成。
在第一区域116中形成n型源极/漏极区域1102，并且在第二区域118中形成p型源极/漏极区域1104。应当理解，相应的源极/漏极区域1104是通过原位掺杂或通过注入掺杂适当的n型或p型掺杂剂。
现在参考图12，示出了形成具有相等栅极厚度的垂直晶体管的步骤的横截面图。层间电介质1202由例如二氧化硅形成，使介电填充层1002在顶部源极/漏极区域1102和1104的高度上方延伸。然后形成导电触点1204，穿透层间电介质1202以接触顶部源极/漏极区1102和1104以及底部源极/漏极区104。导电触点可以由任何适当的导电材料形成，包括例如钨，镍，钛，钼，钽，铜，铂，银，金，钌，铱，铼，铑及其合金。
现在参考图13，示出了具有相等栅极厚度的垂直晶体管的替代实施例的横截面图。在该实施例中，连接两个区域116和118的栅极堆叠未被蚀刻掉，在两个区域之间留下导电连接。以这种方式，两个区域中的器件可以由单个共享门触发。这可以通过在形成间隔物802之前在两个区域之间的区域中添加掩模来实现。
现在参考图14，示出了形成具有相等栅极厚度的替代实施例垂直晶体管的步骤的横截面图。该实施例包括在图4的步骤之前的附加步骤，其中在n型功函数金属堆叠中形成附加层1402。附加层1402可以由例如氮化钛形成。在该实施例中，氮化钛匹配层402(其将第一区域116中的栅极堆叠的厚度与第二区域118中的栅极堆叠的厚度相匹配)可以替代地由诸如钨或钴的导体形成以用于匹配层1404。然后，该实施例可以形成为具有如上所述的分离或共用栅极结构的n型和p型晶体管器件。
现在参考图15，示出了形成具有相等栅极厚度的替代实施例垂直晶体管的步骤的横截面图。该实施例首先形成n型功函数金属堆叠并在第二区域118中采用清除层。n型功函数金属堆叠由例如氮化钛层1502，钛铝碳层1504和氮化钛层1506形成。在沉积层之后，图案化堆叠以将其限制在第一区域116上。
然后在区域116和118上沉积p型功函数层1508，其中p型功函数层1508由例如氮化钛形成。在p型功函数层1508上形成清除层1510。然后，在第二区域118中由例如氮化硅形成匹配层1512，使得第二区域118中的层堆叠的厚度等于第一区域116中的层堆叠的厚度。清除层1510可以由例如碳化钛铝形成，并且阻挡来自栅极外部的氧扩散或者从p型功函数层1508中清除氧。
现在参考图16，示出了形成具有相等栅极厚度的替代实施例垂直晶体管的步骤的横截面图。如图15所示，在第一区域116中形成n型功函数金属堆叠。然后在区域116和118上沉积一层例如氮化钛1508和清除层1510。
在两个区域上沉积例如氮化钛的薄层1602，接着在第二区域118中形成匹配层1604，该匹配层1604由例如钴或钨形成。如在其他实施例中，匹配层1604将第二区域118中的栅极堆叠的厚度与第一区域116中的栅极堆叠的厚度匹配。
应该理解，将根据给定的说明性架构来描述本发明的各方面；然而，其他架构、结构、基板材料和工艺特征和步骤可以在本发明的方面的范围内变化。
还应当理解，当诸如层、区域或基板的元件被称为在另一元件“上”或“上方”时，它可以直接在另一元件上，或者也可以存在中间元件。相比之下，当一个元件被称为“直接在”另一元件上或“直接在另一元件上方”时，不存在中间元件。还应该理解，当一个元件被称为“连接”或“耦合”到另一元件时，它可以直接连接或耦合到其他元件，或者可以存在中间元件。相比之下，当一个元件被称为“直接连接”或“直接耦合”到另一元件时，不存在中间元件。
本实施例可以包括用于集成电路芯片的设计，其可以以图形计算机编程语言创建，并且存储在计算机存储介质(诸如磁盘，磁带，物理硬盘驱动器或诸如在存储访问网络中的虚拟硬盘驱动器)。如果设计者不制造芯片或用于制造芯片的光刻掩模，则设计者可以直接或间接地通过物理手段(例如，通过提供存储设计的存储介质的副本)或电子地(例如，通过因特网)向这些实体传送所得到的设计。然后将存储的设计转换成适当的格式(例如，GDSII)，用于制造光刻掩模，其通常包括要在晶片上形成的所讨论的芯片设计的多个副本。利用光刻掩模来限定要蚀刻或以其他方式处理的晶片(和/或其上的层)的区域。
如本文所述的方法可以用于制造集成电路芯片。得到的集成电路芯片可以由制造者以原始晶片形式(即，作为具有多个未封装芯片的单个晶片)、裸芯片或封装形式分配。在后一种情况下，芯片被安装在单个芯片封装中(诸如塑料载体，带有固定在母板或其他更高级别载体上的引线)或多芯片封装(诸如具有任意一个或多个表面互连或埋置互连的陶瓷载体)。在任何情况下，芯片然后与其他芯片、分立电路元件和/或其他信号处理器件集成，作为(a)中间产品(诸如母板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其他低端应用到具有显示器、键盘或其他输入器件的高级计算机产品，以及中央处理器。
还应理解，将根据所列元件(例如SiGe)描述材料化合物。这些化合物包括化合物中不同比例的元件，例如，SiGe包括其中x小于或等于1的SixGe1-x等。此外，化合物中可以包含其他元件并且仍然根据本发明的原理起作用。具有附加元件的化合物在本文中称为合金。
说明书中对“一个实施例”或“实施例”的引用以及其他变型意味着结合该实施例描述的特定特征，结构，特性等包括在至少一个实施例中。因此，在整个说明书中出现在各个地方的短语“在一个实施例中”或“在实施例中”以及任何其他变型的出现不一定都指代相同的实施例。
应当理解，例如，在“A/B”，“A和/或B”和“A和B中的至少一个”的情况下，对以下“/”，“和/或”以及“至少一个”中的任何一个的使用旨在包括仅选择第一个列出的选项(A)，或仅选择第二个列出的选项(B)，或选择两个选项(A和B)。作为另一示例，在“A，B和/或C”和“A，B和C中的至少一个”的情况下，这种措辞旨在包括仅选择第一个列出的选项(A)，或仅选择第二个列出的选项(B)，或仅选择第三个列出的选项(C)，或仅选择第一个和第二个列出的选项(A和B)，或选择仅限第一和第三个列出的选项(A和C)，或仅选择第二个和第三个列出的选项(B和C)，或选择所有三个选项(A和B和C)。对于所列出的许多项目，如对于本领域和相关领域的普通技术人员将明显的，这可以扩展。
这里使用的术语仅用于描述特定实施例的目的，并不旨在限制示例实施例。如这里所使用的，单数形式“一”，“一个”和“该”也旨在包括复数形式，除非上下文另有明确说明。将进一步理解，术语“包括(comprises)”，“包含(comprising)”，“包括(includes)”和/或“包括(including)”，当在本文中使用时，指定所述特征，整数，步骤，操作，元件和/或组件的存在，但是不排除存在或添加一个或多个其他特征，整数，步骤，操作，元件，组件和/或其组。
这里可以使用空间相对术语，诸如“下方(beneath)”，“下方(below)”，“下方(lower)”，“上方(above)”，“上方(upper)”等，以便于描述以描述一个元件或特征与(多个)其他元件或(多个)其他特征的关系)如附图中所示。应当理解，空间相对术语旨在包括除了附图中所示的定向之外的装置在使用或操作中的不同定向。例如，如果附图中的装置被翻转，则被描述为在其他元件或特征“下方(below)”或“下方(beneath)”的元件将被定向在其他元件或特征“之上(above)”。因此，术语“下方(below)”可以包括上方和下方的定向。该装置可以以其他方式定向(旋转90度或在其他定向上)，并且可以相应地解释本文使用的空间相对描述符。另外，还应理解，当层被称为在两个层“之间”时，它可以是两个层之间的唯一层，或者也可以存在一个或多个中间层。
应当理解，尽管这里可以使用术语第一，第二等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开。因此，在不脱离本概念的范围的情况下，下面讨论的第一元件可以被称为第二元件。
现在参考图17，示出了形成晶体管的方法。框1702在下部源极/漏极层104上形成垂直沟道112。下部源极/漏极层104可以分成不同的区域，包括第一区域116和第二区域118，在每个区域中形成相应的垂直沟道112。框1703在垂直沟道112上方形成栅极电介质110，特别是在垂直沟道112的侧壁上形成栅极电介质110。
框1404在两个区域之一中形成第一类型(例如，p型或n型)功函数层。在一些实施例中，p型功函数层可以首先沉积在p型区域中，在其他实施例中，n型功函数层可以沉积在n型区域中。在一些实施例中，框1404可以在两个区域上共形地形成第一类功函数层，并且随后从第二区域蚀刻掉第一类功函数层。
在一个实施例中，第一类功函数层可以是形成在p型区118中的p型氮化钛层。在另一实施例中，第一类功函数层可以是n型堆叠，该n型堆叠包括n型氮化钛层和钛铝碳层并且可选地包括第二氮化钛层，n型堆叠形成在n型区域116中。
框1706在区域116和118上形成第二类功函数层。在一个实施例中，第二类功函数层可以是n型堆叠，该n型堆叠包括n型氮化钛层和钛铝碳层并且可选地包括第二氮化钛层。在另一实施例中，第二类功函数层可以是p型氮化钛层。第二类功函数层的极性与第一类功函数层的极性相反。
框1707任选地在第二类功函数层上形成清除层1510。如上所述，清除层1510可以由碳化钛铝形成，并且可以从外部阻挡氧气和/或可以从下面的第二类功函数层清除氧气。清除层1510可以具有介于约2nm与约5nm之间的示例性厚度。
框1708在不具有第一类功函数层的区域中形成厚度匹配层。匹配层的厚度大致等于第一类功函数层的厚度，使得两个区域中的堆叠的厚度大致相等。在一个实施例中，匹配层可以由氮化钛形成。在另一实施例中，匹配层可以由诸如钴或钨的金属导体形成。
框1710使垂直鳍片112的高度下方的两个区域中的栅极堆叠凹陷。框1712在垂直鳍片112的暴露侧壁上形成间隔物802。框1714可选地蚀刻掉第一区域和第二区域之间的栅极堆叠，以切断这两个区域之间的电连接。在替代实施例中，可以省略框1714以维持两个区域之间的共享栅极。
框1716蚀刻隔离物802以暴露垂直沟道112的顶部部分。框1718在垂直沟道112的顶部部分上形成顶部源极/漏极区域1102和1104。具体地预期顶部源极/漏极区域1102和1104可以通过外延生长形成，其中原位掺杂适合于每个区域的相应器件类型的掺杂剂。框1720完成器件，形成层间电介质1202和电触点1204到顶部和底部源极/漏极区和栅极。
已经描述了具有相等栅极堆叠厚度的垂直传输晶体管的优选实施例(其旨在是说明性的而不是限制性的)，应当注意的是，鉴于上述教导，修改和变型可以由本领域的技术人员进行。因此，应该理解，可以在所公开的特定实施例中进行改变，这些改变在所附权利要求所概述的本发明的范围内。

Claims (20)

1.一种形成半导体器件的方法，包括：
在第一类型区域和第二类型区域中的底部源极/漏极层上形成垂直半导体沟道；
在所述垂直半导体沟道的侧壁上形成栅极介电层；
在所述第一类型区域中形成第一类功函数层；
在所述第一类型区域和所述第二类型区域两者中形成第二类功函数层；
在所述第二类型区域中形成厚度匹配层，使得所述第一类型区域中的层堆叠具有与所述第二类型区域中的层堆叠相同的厚度；以及
在所述垂直半导体沟道的顶部部分形成顶部源极/漏极区域。
2.根据权利要求1所述的方法，还包括在所述第二类功函数层上形成清除层。
3.根据权利要求1所述的方法，其中保留在所述第一类型区域和所述第二类型区域之间的区域中的所述第一类功函数层和所述第二类功函数层的一部分。
4.根据权利要求1所述的方法，还包括使第一类型堆叠和第二类型堆叠凹陷低于所述垂直半导体沟道的高度，所述第一类型堆叠由所述第一类功函数层和所述第二类功函数层形成，所述第二类型堆叠由所述第二类功函数层和所述厚度匹配层形成。
5.根据权利要求4所述的方法，还包括在所述垂直半导体沟道的暴露侧壁上形成间隔物。
6.根据权利要求5所述的方法，还包括从所述第一类型区域和所述第二类型区域之间的区域蚀刻掉所述第一类功函数层和所述第二类功函数层的一部分。
7.根据权利要求5所述的方法，进一步包括在形成所述顶部源极/漏极区域之前回蚀刻所述间隔物。
8.根据权利要求1所述的方法，其中所述厚度匹配层包括氮化钛。
9.根据权利要求1所述的方法，其中所述厚度匹配层包括选自由钴和钨组成的组的材料。
10.一种用于形成半导体器件的方法，包括：
在第一类型区域和第二类型区域中的底部源极/漏极层上形成垂直半导体沟道；
在所述垂直半导体沟道的侧壁上形成栅极介电层；
在所述第一类型区域中形成第一类功函数层；
在所述第一类型区域和所述第二类型区域两者中形成第二类功函数层；
在所述第二类型区域中形成厚度匹配层，使得所述第一类型区域中的层堆叠具有与所述第二类型区域中的层堆叠相同的厚度；
使第一类型堆叠和第二类型堆叠凹陷低于所述垂直半导体沟道的高度，所述第一类型堆叠由所述第一类功函数层和所述第二类功函数层形成，所述第二类型堆叠由所述第二类功函数层和所述厚度匹配层形成；
在所述垂直半导体沟道的暴露侧壁上形成间隔物；
回蚀刻所述间隔物以暴露每个垂直半导体沟道的顶部部分；以及
在所述垂直半导体沟道的所述顶部部分上形成顶部源极/漏极区。
11.一种集成芯片，包括：
第一类型的第一半导体器件，所述第一半导体器件包括：
垂直半导体沟道；
栅极介电层，所述栅极介电层被形成在所述垂直半导体沟道的侧壁上；
被形成在所述栅极介电层上的第一类功函数层；以及
后面被形成在所述第一类功函数上的第二类功函数层；以及第二类型的第二半导体器件，所述第二半导体器件包括：
垂直半导体沟道；
栅极介电层，所述栅极介电层被形成在所述垂直半导体沟道的侧壁上；
被形成在所述栅极介电层上的第二类功函数层；以及
被形成在所述第二类功函数层上的厚度匹配层，所述厚度匹配层的厚度大致等于所述第一类功函数层的厚度。
12.根据权利要求11所述的集成芯片，还包括器件间连接，所述器件间连接连接所述第一半导体器件和所述第二半导体器件，并且包括所述第一类功函数层、所述第二类功函数层和所述厚度匹配层的部分。
13.根据权利要求11所述的集成芯片，其中所述第一半导体器件是n型晶体管，并且其中所述第二半导体器件是p型晶体管。
14.根据权利要求13所述的集成芯片，其中所述第一类功函数层包括n型氮化钛层，钛铝碳层和第二氮化钛层，并且其中所述第二类功函数层包括p型氮化钛层。
15.根据权利要求13所述的集成芯片，其中所述第一半导体器件还包括在所述第二类功函数层上的清除层，并且其中所述第二半导体器件还包括在所述第二类功函数层与所述厚度匹配层之间的清除层。
16.根据权利要求15所述的集成芯片，其中所述厚度匹配层包括选自由氮化钛、钴和钨组成的组的材料。
17.根据权利要求11所述的集成芯片，其中所述第一半导体器件是p型晶体管，并且其中所述第二半导体器件是n型晶体管。
18.根据权利要求17所述的集成芯片，其中所述第一类功函数层包括p型氮化钛层，并且其中所述第二类功函数层包括n型氮化钛层和钛铝碳层。
19.根据权利要求17所述的集成芯片，其中所述厚度匹配层包括选自由氮化钛、钴和钨组成的组的材料。
20.根据权利要求17所述的集成芯片，其中所述第二类功函数层还包括第二氮化钛层。
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