CN110888038A - Standard unit test circuit layout, optimization method thereof and standard unit test structure - Google Patents

Standard unit test circuit layout, optimization method thereof and standard unit test structure Download PDF

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CN110888038A
CN110888038A CN201811055812.0A CN201811055812A CN110888038A CN 110888038 A CN110888038 A CN 110888038A CN 201811055812 A CN201811055812 A CN 201811055812A CN 110888038 A CN110888038 A CN 110888038A
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standard cell
column
standard
row
ith
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CN110888038B (en
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王夺
陈志强
唐伟峰
张凤娟
陈乃霞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2882—Testing timing characteristics

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  • General Engineering & Computer Science (AREA)
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Abstract

A standard unit test circuit layout and an optimization method thereof, and a standard unit test structure are provided, wherein the standard unit test circuit layout comprises: a first unit circuit to be tested; the first unit circuit to be tested includes: a plurality of stages of first standard cells; several levels of first standard cells are arranged into Y1Line X1An array of columns. The connection relations of the first standard units of the plurality of levels are connected in a fishbone shape mode, so that the area of a circuit layout is saved. Second, the accuracy of the delay characteristic of the first standard cell actually tested is improved. In conclusion, the performance of the standard unit test circuit layout is improved.

Description

Standard unit test circuit layout, optimization method thereof and standard unit test structure
Technical Field
The invention relates to the field of integrated circuit performance testing, in particular to a standard unit testing circuit layout, an optimization method thereof and a standard unit testing structure.
Background
With the continuous development of integrated circuit design and manufacture, the design requirement for the standard cell library is larger and larger, and the subsequent test for the delay and power consumption of the standard cell library is indispensable. However, the standard cell has a shorter delay, especially for deep submicron processes below 65 nm, and the requirement of the standard cell on the test accuracy is more and more strict. How to construct the standard cell test structure can effectively and accurately evaluate the delay of the standard cell, so that more accurate design parameters of the standard cell library are given to clients for reference, and the method is an increasingly important research subject.
However, the performance of the existing standard cell test structure is to be improved.
Disclosure of Invention
The invention aims to provide a standard unit test circuit layout, an optimization method thereof and a standard unit test structure so as to improve the performance of the standard unit test circuit layout.
In order to solve the above problems, the present invention provides a standard cell test circuit layout, which includes: a first unit circuit to be tested; the first unit circuit to be tested includes: a plurality of levels of first standard cells, the plurality of levels of first standard cells being Y1Line X1Array of columns, Y1Is an even number of 4 or more, X1Is an integer of 4 or more; in the first standard cells of the first row, adjacent first standard cells are connected; the Y th1In the first standard cells of the row, adjacent first standard cells are connected; ith1Line first row to i1Line j (th)1Adjacent first standard cells in the first standard cells of the column are connected; ith1Line j (th)1+1 columns to ith1Line X1Adjacent first standard cells in the first standard cells of the column are connected; ith1Line j (th)1First standard cell and ith of column1Go to the firstj1The first standard cell of +1 column is off; ith1+1 line first row to ith1Row +1, j1Adjacent first standard cells in the first standard cells of the column are connected; ith1Row +1, j1+1 columns to ith1+1 line X1Adjacent first standard cells in the first standard cells of the column are connected; ith1Row +1, j1First standard cell and ith of column1Row +1, j1The first standard cell of +1 column is off; ith1Line X1First standard cell and ith of column1Line 1, X1The first standard cell of the column is connected, Yth1First standard cell and Y-th standard cell in first row and column1-1 row first column first standard cell connection, Yth1Line X1First standard cell and Y of column1Line 1, X1The first standard cell of the column is connected, the ith1Line j (th)1First standard cell and ith of column1Row +1, j1The first standard cell of the column is connected, the ith1Line j (th)1+1 column of the first standard cell and ith1Row +1, j1The first standard cell of +1 column is connected; the first standard cell of the second row and the first column is disconnected from the first standard cell of the first row and the first column; i.e. i1Is 2 or more and Y or less1An even number of-2, j1Is 2 or more and X or less1-an integer of 2; when i is1Is not less than 4 and not more than Y1Even number of-2, i1First standard cell and ith of row and first column1-1 row first column first standard cell connection.
Optionally, when X1When it is even, j1Is equal to X11/2 of (1).
Optionally, when X1When it is odd, j1Is equal to (X)1-1)/2; or, when X1When it is odd, j1Is equal to (X)1+1)/2。
Optionally, X1*Y1＝N1，N1Is a composite number; m th1Output terminal of the first standard cell and m1+1 st stageInput terminals of a standard cell are connected, m1Is greater than or equal to 1 and less than or equal to N1-an integer of 1; the first standard cell in the first row and the first column is the first-level first standard cell, and the first standard cell in the second row and the first column is the Nth standard cell1The first standard cell is ranked.
Optionally, the first unit circuit to be tested further includes: a first seismic unit having a first seismic connection input, a first seismic signal input, and a first seismic output; the first seismic output end is connected with the input end of the first-stage first standard unit; the first seismic source is connected with the input end and the Nth seismic source1The output ends of the first standard cells are connected; the first seismic signal input is adapted to input a first seismic drive signal.
Optionally, the method further includes: a first frequency-dividing circuit located at a side of the first unit circuit to be tested, the first frequency-dividing circuit including Z1Stage one frequency-dividing unit, Z1Is an integer of 1 or more; z th1The first frequency-dividing unit includes: z th1Stage first timing flip-flop and z1Stage first clock inverter, z1Is greater than or equal to 1 and less than or equal to Z1An integer of (d); the first time sequence trigger of each stage is provided with a first trigger pulse signal end, a first trigger data input end and a first trigger output end; a first trigger pulse signal end of a first timing trigger of the first stage is connected with a first shock output end; z th1The first trigger data input terminal of the first time sequence trigger of the stage is connected with the z < th > signal1An output of a first clock inverter of a stage; z th1The first trigger output terminal of the first time sequence trigger of the stage is connected with the z-th1An input of a first clock inverter of a stage; when Z is1When an integer greater than or equal to 2 is taken, in the first frequency division units of two adjacent stages, the first trigger output end of the first time sequence trigger of the previous stage is connected with the first trigger pulse signal end of the first time sequence trigger of the next stage.
Optionally, the method further includes: a first buffer with its input end connected with the Z-th buffer1First trigger output of stage first timing triggerA terminal, the first buffer being adapted to receive the Z-th buffer1Grading the output signal of the first frequency-dividing unit and correcting the Z-th signal1And (3) the output signal of the first frequency division unit.
Optionally, the method further includes: the second unit circuit to be tested reaches the Q-th unit circuit to be tested, and Q is an integer more than or equal to 2; the kth unit circuit under test includes: a plurality of levels of k standard cells, the k standard cells of the plurality of levels being YkLine XkArray of columns, YkIs an even number of 4 or more, XkIs an integer of 4 or more, k is an integer of 2 or more and Q or less; in the kth standard cell of the first row, adjacent kth standard cells are connected; the Y thkIn the k standard cells of the row, adjacent k standard cells are connected; ithkLine first row to ikLine j (th)kAdjacent kth standard cells in the kth standard cell of the column are connected; ithkLine j (th)k+1 columns to ithkLine XkAdjacent kth standard cells in the kth standard cell of the column are connected; ithkLine j (th)kThe k standard cell and i standard cell of the columnkLine j (th)kThe kth standard cell of +1 column is off; ithk+1 line first row to ithkRow +1, jkAdjacent kth standard cells in the kth standard cell of the column are connected; ithkRow +1, jk+1 columns to ithk+1 line XkAdjacent kth standard cells in the kth standard cell of the column are connected; ithkRow +1, jkThe k standard cell and i standard cell of the columnkRow +1, jkThe kth standard cell of +1 column is off; ithkLine XkThe k standard cell and i standard cell of the columnkLine 1, XkThe kth standard cell of the column is connected, the YthkThe k standard cell and the Y standard cell in the first row and the first columnk-1 row first column kth standard cell connection, YkLine XkThe kth standard cell and the Yth standard cell of the columnkLine 1, XkThe kth standard cell of the column is connected, the ithkLine j (th)kThe k standard cell and i standard cell of the columnkRow +1, jkThe kth standard cell of the column is connected, the ithkLine j (th)k+1 lineThe kth standard cell and the ithkRow +1, jkThe kth standard cell of column +1 is connected; the kth standard cell of the second row and the first column is disconnected from the kth standard cell of the first row and the first column; i.e. ikIs 2 or more and Y or lesskAn even number of-2, jkIs 2 or more and X or lessk-an integer of 2; when i iskIs not less than 4 and not more than YkEven number of-2, ikThe k standard cell and i standard cell in the first row and columnk-1 row and first column of the kth standard cell connection.
The invention also provides an optimization method of the standard unit test circuit layout, which comprises the following steps: providing any one standard unit test circuit layout; obtaining a first difference value, the first difference value being related to X1And Y1A function of (a); the method for acquiring the first difference value comprises the following steps: acquiring the width and the height of a first standard cell, wherein the width direction of the first standard cell is parallel to the row direction of an array formed by a plurality of levels of first standard cells, and the height direction of the first standard cell is parallel to the column direction of the array formed by the plurality of levels of first standard cells; obtaining a first total length according to the width of the first standard unit and the number of columns of the array formed by the plurality of levels of the first standard units, wherein the first total length is equal to the width and X of the first standard unit1The product of (a); obtaining a first total height according to the height of the first standard cell and the number of rows of the array formed by the plurality of levels of the first standard cells, wherein the first total height is equal to the height of the first standard cell and Y1The product of (a); acquiring a first difference value according to the first total height and the first total length, wherein the first difference value is equal to the absolute value of the difference value between the first total height and the first total length; the method for optimizing the standard unit test circuit layout further comprises the following steps: with X1*Y1＝N1Obtaining the minimum value of the first difference, N, as the constraint condition1Is a complex number and is a constant; x when the first difference value is obtained and the minimum value is taken1And Y1The specific numerical value of (1).
The invention also provides a standard unit test structure manufactured according to any standard unit test circuit layout.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the standard unit test circuit layout provided by the technical scheme of the invention comprises a first unit circuit to be tested, wherein the first unit circuit to be tested comprises a plurality of stages of first standard units. Several levels of first standard cells are arranged into Y1Line X1An array of columns. The connection relations of the first standard units of the plurality of levels are connected in a fishbone shape mode, so that the area of a circuit layout is saved. Secondly, because the connection relation of the first standard units of the plurality of stages is connected in a fishbone shape, the distance between the first standard units of the first and last stages is smaller, so that the interconnection line in the circuit of the first unit to be tested is shorter, the interference of the interconnection line on the delay characteristic of the first standard units of the plurality of stages is smaller, and the accuracy of the delay characteristic of the first standard unit actually tested is improved. In conclusion, the performance of the standard unit test circuit layout is improved.
Furthermore, the standard unit test circuit layout not only comprises a first unit circuit to be tested, but also comprises a second unit circuit to be tested and a unit circuit from the second unit circuit to the Q-th unit circuit to be tested, so that the standard unit test structure manufactured according to the standard unit test circuit layout also comprises the first unit circuit to be tested and the second unit circuit to be tested and the Q-th unit circuit to be tested, the performance of various different types of standard units can be tested by adopting one standard unit test structure, the manufacturing process is simplified, and the cost is reduced.
Drawings
FIG. 1 is a layout of standard cells in a standard cell test circuit layout;
FIG. 2 is a layout diagram of standard cells in another standard cell test circuit layout;
FIG. 3 is a layout diagram of a standard cell in yet another standard cell test circuit layout;
FIG. 4 is a layout diagram of a standard cell test circuit layout in an embodiment of the present invention;
FIG. 5 is a layout diagram of a first standard cell of several levels in FIG. 4;
FIG. 6 is a diagram of the connection between a first seismic unit and several levels of first standard units;
fig. 7 is a structural diagram of a first frequency-dividing circuit.
Detailed Description
As mentioned in the background, the performance of the prior art standard cell test structure is yet to be improved.
A standard cell test circuit layout, with reference to fig. 1, comprising: a unit circuit to be tested; the unit circuit to be tested includes: the N-level standard cell 1001, the first-level standard cell 1001 to the Nth-level standard cell 1001 are connected end to end; and the shock-starting unit 1002, the shock-starting unit 1002 is respectively connected with the first-level standard cell 1001 and the Nth-level standard cell 1001, and the layout shapes of the shock-starting unit 1002 and the Nth-level standard cell 1001 form a single ring.
The placement of the plurality of standard cells 1001 in fig. 1 is simple and easy to control. However, as the number of the standard cells 1001 is more and more required, that is, under the condition that the requirement on the test progression of the standard cells 1001 is increased, the length of the single-row ring is too long, and a large space inside the single-row ring is not utilized, which causes a large waste of the circuit layout area.
Another standard cell test circuit layout, referring to fig. 2, includes: a unit circuit to be tested; the unit circuit to be tested includes: the standard cell 1003 comprises N-level standard cells 1003, wherein the first-level standard cell 1003 to the Nth-level standard cell 1003 are connected end to end; and the vibration unit 1004 is connected with the first-level standard cell 1003 and the Nth-level standard cell 1003 respectively, and the layout shapes of the vibration unit 1004 and the N-level standard cell 1003 are progressive ring shapes.
The arrangement mode of the standard cells 1003 in fig. 2 saves the circuit layout area. However, as the requirement for the number of test stages of the standard cell 1003 increases, the number of rings also increases, the first-stage standard cell 1003 is located at the innermost ring, the nth-stage standard cell 1003 is located at the outermost ring, the distance from the first-stage standard cell 1003 to the nth-stage standard cell 1003 is also larger, and the interconnection line between the first-stage standard cell 1003 and the vibration initiating cell 1004 needs to pass through a plurality of rings, so the head-to-tail interconnection line between the first-stage standard cell 1003 and the vibration initiating cell 1004 is longer, the interference of the interconnection line on the delay characteristics of several stages of the first-stage standard cell 1003 is larger, and the delay characteristics of the first standard cell 1003 obtained through testing cannot accurately reflect the delay characteristics of the first standard cell 1003. I.e. the accuracy of the test to obtain the delay characteristic of the first standard cell 1003 is low.
A standard cell test circuit layout, referring to fig. 3, a cell circuit to be tested; the unit circuit to be tested includes: an N-level standard cell 1005, the first-level standard cell 1005 to the nth-level standard cell 1005 being connected end to end; the seismic unit 1006, the seismic unit 1006 is respectively connected with the first-level standard unit 1005 and the nth-level standard unit 1005, and the layout shapes of the seismic unit 1006 and the nth-level standard unit 1005 are in an "S" shape.
The layout area of the circuit is saved by the arrangement of the standard cells 1005 in fig. 3. However, as the requirement for the number of test stages of the standard cells 1005 increases, the distance between the first-stage standard cells 1005 and the nth-stage standard cells 1005 is longer, the interconnection lines between the first-stage standard cells 1005 and the seismic units 1006 greatly interfere with the delay characteristics of the first-stage standard cells 1005 in several stages, and the delay characteristics of the first standard cells 1005 cannot accurately reflect the delay characteristics of the first standard cells 1005 themselves after the test. I.e., the accuracy of the test to obtain the delay characteristic of the first standard cell 1005 is low.
On this basis, the invention provides a standard cell test circuit layout, which comprises: a first unit circuit to be tested; the first unit circuit to be tested includes: a plurality of stages of first standard cells; several levels of first standard cells are arranged into Y1Line X1An array of columns. The connection relations of the first standard units of the plurality of levels are connected in a fishbone shape mode, so that the area of a circuit layout is saved. Second, the accuracy of the delay characteristic of the first standard cell actually tested is improved. In conclusion, the performance of the standard unit test circuit layout is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The present embodiment provides a standard cell test circuit layout, please refer to fig. 4 to fig. 7, which includes: the first unit circuit under test 10.
The first unit circuit under test 10 includes: several levels of first standard cells 100.
In the plurality of levels of the first standard cells 100, the number of the first standard cells 100 is greater, such as: in the order of thousands, thousands or tens of thousands.
In this embodiment, the first standard cell 100 is taken as an example of an inverter to be tested. In other embodiments, the first standard cell may also be other logic devices, such as a nand gate and a nor gate. The present application does not limit the specific structure of the first standard cell 100.
In this embodiment, the operation tool for laying out the first to-be-measured unit circuit 10 is eda (electronic design analysis).
The plurality of stages of the first standard cells 100 are arranged as Y1Line X1Array of columns A1(refer to FIG. 5), Y1Is an even number of 4 or more, X1Is an integer of 4 or more.
In this embodiment, the first standard cells 100 in the plurality of stages are arranged in an array of eight rows by six columns as an example.
For the Y1Line X1The array of columns (see fig. 5), the connection relationship between the first standard cells 100 is as follows:
in the first standard cell 100 of the first row, adjacent first standard cells 100 are connected; the Y th1In the first standard cell 100 of the row, adjacent first standard cells 100 are connected;
ith1First standard cell 100 to ith in row and first column1Line j (th)1Among the first standard cells 100 of the column, adjacent first standard cells 100 are connected; ith1Line j (th)1+1 column of the first standard cell 100 to ith1Line X1Among the first standard cells 100 of the column, adjacent first standard cells 100 are connected; ith1Line j (th)1The first standard cell 100 and the ith of the column1Line j (th)1The first standard cell 100 of the +1 column is off; ith1+1 column first standard cell 100 toIth1Row +1, j1Among the first standard cells 100 of the column, adjacent first standard cells 100 are connected; ith1Row +1, j1+1 column of the first standard cell 100 to ith1+1 line X1Among the first standard cells 100 of the column, adjacent first standard cells 100 are connected; ith1Row +1, j1The first standard cell 100 and the ith of the column1Row +1, j1The first standard cell 100 of the +1 column is off;
ith1Line X1The first standard cell 100 and the ith of the column1Line 1, X1The first standard cell 100 of the column is connected, Yth1The first standard cell 100 and the Yth standard cell in the first column11 rows first column first standard cell 100 connection, Yth1Line X1The first standard cell 100 and the Y-th standard cell of the column1Line 1, X1The first standard cell 100 of the column is connected, the ith1Line j (th)1The first standard cell 100 and the ith of the column1Row +1, j1The first standard cell 100 of the column is connected, the ith1Line j (th)1+1 column of the first standard cell 100 and ith1Row +1, j1The first standard cell 100 of +1 column is connected; the first standard cell 100 of the second row and the first column is disconnected from the first standard cell 100 of the first row and the first column;
wherein i1Is 2 or more and Y or less1An even number of-2, j1Is 2 or more and X or less1-an integer of 2;
when i is1Is not less than 4 and not more than Y1Even number of-2, i1The first standard cell 100 and the ith standard cell in the first column11 row first column first standard cell 100 connection.
In this embodiment, in the first standard cells 100 in the first row, the adjacent first standard cells 100 are connected, that is, the first standard cell 100 in the first column in the first row is connected to the first standard cell 100 in the second column in the first row, the first standard cell 100 in the second column in the first row is connected to the first standard cell 100 in the third column in the first row, the first standard cell 100 in the third column in the first row is connected to the first standard cell 100 in the fourth column in the first row, the first standard cell 100 in the fourth column in the first row is connected to the first standard cell 100 in the fifth column in the first row, and the first standard cell 100 in the fifth column in the first row is connected to the first standard cell 100 in the sixth column in the first row.
In this embodiment, array A in FIG. 51The number of rows in (1) is illustrated by taking eight rows as an example, and accordingly, in the first standard cell 100 in the eighth row, the adjacent first standard cells 100 are connected, that is, the first standard cell 100 in the first column in the eighth row is connected to the first standard cell 100 in the second column in the eighth row, the first standard cell 100 in the second column in the eighth row is connected to the first standard cell 100 in the third column in the eighth row, the first standard cell 100 in the third column in the eighth row is connected to the first standard cell 100 in the fourth column in the eighth row, the first standard cell 100 in the fourth column in the eighth row is connected to the first standard cell 100 in the fifth column in the eighth row, and the first standard cell 100 in the fifth column in the eighth row is connected to the first standard cell 100 in the sixth column in the eighth row.
In this example, the number j1To illustrate as an example, of the first standard cells 100 in the first column and the second row to the first standard cells 100 in the third column and the second row, the adjacent first standard cells 100 are connected, that is, the first standard cell 100 in the first column and the second row is connected to the first standard cell 100 in the second column and the second row, and the first standard cell 100 in the second column and the second row is connected to the first standard cell 100 in the third column and the second row; among the first standard cells 100 in the second row and the fourth column to the first standard cells 100 in the second row and the sixth column, the adjacent first standard cells 100 are connected, that is, the first standard cells 100 in the second row and the fourth column are connected with the first standard cells 100 in the second row and the fifth column, and the first standard cells 100 in the second row and the fifth column are connected with the first standard cells 100 in the second row and the sixth column; the first standard cell 100 of the third column of the second row is disconnected from the first standard cell 100 of the fourth column of the second row; of the first standard cells 100 of the third row and first column to the first standard cells 100 of the third row and third column, the adjacent first standard cells 100 are connected, that is, the first standard cell 100 of the third row and first column is connected with the first standard cell 100 of the third row and second column, and the first standard cell 100 of the third row and second column is connected with the first standard cell 100 of the third row and second columnThe first standard cells 100 of the third row and the third column are connected; of the first standard cells 100 of the third row and the fourth column to the first standard cells 100 of the third row and the sixth column, the adjacent first standard cells 100 are connected, that is, the first standard cells 100 of the third row and the fourth column are connected with the first standard cells 100 of the third row and the fifth column, and the first standard cells 100 of the third row and the fifth column are connected with the first standard cells 100 of the third row and the sixth column; the first standard cell 100 of the third row and the third column is disconnected from the first standard cell 100 of the third row and the fourth column; in the first standard cell 100 of the fourth row and the first column and the first standard cell 100 of the fourth row and the third column, the adjacent first standard cells 100 are connected, that is, the first standard cell 100 of the fourth row and the first column is connected to the first standard cell 100 of the fourth row and the second column, and the first standard cell 100 of the fourth row and the second column is connected to the first standard cell 100 of the fourth row and the third column; of the first standard cells 100 in the fourth row and the fourth column to the first standard cells 100 in the sixth row and the sixth column, the adjacent first standard cells 100 are connected, that is, the first standard cells 100 in the fourth row and the fourth column are connected to the first standard cells 100 in the fifth row and the fifth column, and the first standard cells 100 in the fifth row and the fifth column are connected to the first standard cells 100 in the sixth row and the sixth column; the first standard cell 100 of the fourth row and the third column is disconnected from the first standard cell 100 of the fourth row and the fourth column; in the first standard cell 100 in the first column of the fifth row and the first standard cell 100 in the third column of the fifth row, the adjacent first standard cells 100 are connected, that is, the first standard cell 100 in the first column of the fifth row is connected with the first standard cell 100 in the second column of the fifth row, and the first standard cell 100 in the second column of the fifth row is connected with the first standard cell 100 in the third column of the fifth row; in the first standard cells 100 in the fifth row and the fourth column to the first standard cells 100 in the fifth row and the sixth column, the adjacent first standard cells 100 are connected, that is, the first standard cell 100 in the fifth row and the fourth column is connected to the first standard cell 100 in the fifth row and the fifth column, and the first standard cell 100 in the fifth row and the fifth column is connected to the first standard cell 100 in the fifth row and the sixth column; the first standard cell 100 of the third column of the fifth row is disconnected from the first standard cell 100 of the fourth column of the fifth row; the first standard cell 100 in the first column of the sixth row and the first standard cell 100 in the third column of the sixth rowIn the standard cells 100, adjacent first standard cells 100 are connected, that is, the first standard cell 100 in the first column of the sixth row is connected to the first standard cell 100 in the second column of the sixth row, and the first standard cell 100 in the second column of the sixth row is connected to the first standard cell 100 in the third column of the sixth row; in the first standard cells 100 in the sixth row and the fourth column to the first standard cells 100 in the sixth row and the sixth column, the adjacent first standard cells 100 are connected, that is, the first standard cell 100 in the sixth row and the fourth column is connected to the first standard cell 100 in the sixth row and the fifth column, and the first standard cell 100 in the sixth row and the fifth column is connected to the first standard cell 100 in the sixth row and the sixth column; the first standard cell 100 of the third column in the sixth row is disconnected from the first standard cell 100 of the fourth column in the sixth row; in the first standard cell 100 in the first column on the seventh row and the first standard cell 100 in the third column on the seventh row, the adjacent first standard cells 100 are connected, that is, the first standard cell 100 in the first column on the seventh row is connected with the first standard cell 100 in the second column on the seventh row, and the first standard cell 100 in the second column on the seventh row is connected with the first standard cell 100 in the third column on the seventh row; among the first standard cells 100 in the seventh row and the fourth column to the first standard cells 100 in the seventh row and the sixth column, the adjacent first standard cells 100 are connected, that is, the first standard cell 100 in the seventh row and the fourth column is connected to the first standard cell 100 in the seventh row and the fifth column, and the first standard cell 100 in the seventh row and the fifth column is connected to the first standard cell 100 in the seventh row and the sixth column; the first standard cell 100 of the third column of the seventh row is disconnected from the first standard cell 100 of the fourth column of the seventh row.
In this embodiment, array A in FIG. 51The number of columns of (a) is illustrated by taking a sixth column as an example, and accordingly, the first standard cell 100 in the second row and the sixth column is connected to the first standard cell 100 in the first row and the sixth column, the first standard cell 100 in the fourth row and the sixth column is connected to the first standard cell 100 in the third row and the sixth column, the first standard cell 100 in the sixth row and the sixth column is connected to the first standard cell 100 in the fifth row and the sixth column, and the first standard cell 100 in the eighth row and the sixth column is connected to the first standard cell 100 in the seventh row and the sixth column.
In this embodiment, the first standard cell 100 in the first column of the eighth row is connected to the first standard cell 100 in the first column of the seventh row.
In this example, Y1Equal to 8, respectively, when i1An even number of 4 or more and 6 or less, i-th1The first standard cell 100 and the ith standard cell in the first column1The first standard cell 100 of the first column of the 1 row is connected, that is, the first standard cell 100 of the first column of the sixth row is connected to the first standard cell 100 of the first column of the fifth row, and the first standard cell 100 of the first column of the fourth row is connected to the first standard cell 100 of the first column of the third row.
In this embodiment, the first standard cell 100 in the second row and the first column is disconnected from the first standard cell 100 in the first row and the first column.
In this example, the number j1Is illustrated as an example at 3, i1Line j (th)1The first standard cell 100 and the ith of the column1Row +1, j1The first standard cell 100 of the column is connected, the ith1Line j (th)1+1 column of the first standard cell 100 and ith1Row +1, j1The first standard cell 100 in the +1 column is connected, that is, the first standard cell 100 in the second row and the third column is connected to the first standard cell 100 in the third row and the third column, the first standard cell 100 in the second row and the fourth column is connected to the first standard cell 100 in the third row and the fourth column, the first standard cell 100 in the fourth row and the third column is connected to the first standard cell 100 in the fifth row and the third column, the first standard cell 100 in the fourth row and the fourth column is connected to the first standard cell 100 in the fifth row and the fourth column, the first standard cell 100 in the sixth row and the third column is connected to the first standard cell 100 in the seventh row and the third column, and the first standard cell 100 in the sixth row and the fourth column is connected to the first standard cell 100 in the seventh row and the fourth column.
In this example, X1*Y1＝N1，N1Is a composite number and is an even number.
In this embodiment, the first-level first standard cells 100 to Nth1The first standard cell 100 of a stage, the first standard cells 100 of two adjacent stages are connected, specifically, the m-th standard cell1The output terminal of the first standard cell 100 and the m-th1+1 level first standard cell 100 input terminal connection, m1Is greater than or equal to 1 and less than or equal to N1-an integer of 1.
In this embodiment, the first standard cell 100 in the first row and the first column is the first standard cell 100 in the first level, the first standard cell 100 in the first row and the second column is the first standard cell 100 in the second level, the number of the stages of the first standard cell 100 increases with the increase of the number of the connections of the first standard cell 100, and the first standard cell 100 in the first row and the sixth column is the first standard cell 100 in the sixth level.
In this embodiment, the first standard cell 100 in the sixth column of the second row to the first standard cell 100 in the fourth column of the second row are the first standard cell 100 in the seventh level to the first standard cell 100 in the ninth level in sequence. The first standard cell 100 in the third row and the fourth column to the first standard cell 100 in the third row and the sixth column are the first standard cell 100 in the tenth stage to the first standard cell 100 in the tenth stage in sequence. The first standard cells 100 in the fourth row and the sixth column to the first standard cells 100 in the fourth row and the fourth column are the first standard cells 100 in the thirteenth level to the first standard cells 100 in the fifteenth level in this order. The first standard cell 100 in the fifth row and the fourth column to the first standard cell 100 in the fifth row and the sixth column are the first standard cell 100 in the sixteenth level to the first standard cell 100 in the eighteenth level in sequence. The first standard cell 100 in the sixth row and the sixth column to the first standard cell 100 in the fourth row and the sixth column are the first standard cell 100 in the nineteenth stage to the first standard cell 100 in the twenty-ninth stage in sequence. The first standard cell 100 in the seventh row and the fourth column to the first standard cell 100 in the seventh row and the sixth column are the first standard cell 100 in the twenty-second stage to the first standard cell 100 in the twenty-fourth stage in sequence. The first standard cell 100 in the eighth row and the sixth column to the first standard cell 100 in the eighth row and the first column are the first standard cell 100 in the twenty-fifth level to the first standard cell 100 in the thirty-third level in sequence. The first standard cell 100 in the first column of the seventh row to the first standard cell 100 in the third column of the seventh row are the first standard cell 100 of the thirty-first stage to the first standard cell 100 of the thirty-third stage in sequence. The first standard cell 100 in the sixth row and the third column to the first standard cell 100 in the sixth row and the first column are the first standard cell 100 in the thirty-fourth stage to the first standard cell 100 in the thirty-sixth stage in sequence. The first standard cell 100 in the first column of the fifth row to the first standard cell 100 in the third column of the fifth row are the first standard cell 100 in the thirty-seventh level to the first standard cell 100 in the thirty-ninth level in sequence. The first standard cells 100 of the fourth row and the third column to the first standard cells 100 of the fourth row and the first column are the first standard cells 100 of the forty-th stage to the first standard cells 100 of the forty-fourth stage in this order. The first standard cells 100 in the third row and the first column to the first standard cells 100 in the third row and the third column are the first standard cells 100 in the forty-third stage to the first standard cells 100 in the forty-fifth stage in this order. The first standard cell 100 in the third column of the second row to the first standard cell 100 in the first column of the second row are the first standard cell 100 in the fourth sixteenth level to the first standard cell 100 in the fourth eighteenth level in sequence.
The first standard cell 100 in the second row and the first column is the Nth standard cell1The first standard cell 100 is ranked. In this example, N1And 48, the first standard cell 100 in the second row and the first column is correspondingly the first standard cell 100 in the forty-eight level.
In this example, when X is1When it is even, j1Is equal to X11/2, such benefits include: the accuracy of subsequently calculating the minimum value of the first difference is improved.
In other embodiments, when X1When it is even, j1Is 2 or more and X or less1-2 is any integer.
In this example, when X is1When it is odd, j1Is equal to (X)1-1)/2, or, when X is1When it is odd, j1Is equal to (X)1+1)/2. Such benefits include: the accuracy of subsequently calculating the minimum value of the first difference is improved.
In other embodiments, when X1When it is odd, j1Is 2 or more and X or less1-2 is any integer.
In the EDA tool, the TCL scripting language is used to realize the placement position of the first standard cells 100, and the Verilog language is used to realize the connection relationship between the first standard cells 100.
The first unit circuit under test 10 further includes: a first seismic unit 200 (refer collectively to fig. 4 and 6), said first seismic unit 200 having a first seismic connection input, a first seismic signal input, and a first seismic output; the first seismic output end is connected with the input end of the first-stage first standard unit 100; the first seismic source is connected with the input end and the Nth seismic source1The output of the first standard cell 100 of the stage is connected; the first seismic signal input is adapted to input a first seismic drive signal.
In this example, N1And 48, respectively, the first seismic connection input is connected to the output of the forty-eighth stage first standard cell 100.
After the first seismic signal input end receives the input of the first seismic driving signal, the first seismic unit 200 starts to work and outputs a signal to the first-stage first standard unit 100.
It should be noted that, in other embodiments, the first unit circuit to be tested further includes: several poles first additional standard cells (W)1Stage one additional standard cell, W1Is an integer greater than or equal to 1), the first additional standard cell is the same structure and the same type as the first standard cell 100. The number of the first additional standard cells is small, such as several, dozens or dozens.
The role of the first additional standard cell arrangement includes: the sum of the number of first additional standard cells and the number of first standard cells 100 is a more computationally convenient value. For example, when the number of the first standard cells 100 in the first standard cells 100 of the several stages is 986, the number of the first additional standard cells is 14. So that the accuracy of the subsequent delay calculation for a single first standard cell is improved.
W th1Output terminal of first additional standard cell and w-th standard cell of stage1Input connection of the first additional standard cell of stage +1, w1Is 1 or more and W or less1-an integer of 1. N th1The output of the first standard cell 100 of the stage and the input of the first additional standard cell of the first stageAnd (4) connecting.
When the first additional standard unit is arranged, the first shock starting output end is connected with the input end of the first-stage first standard unit; the first shock absorber is connected with the W-th input end1The outputs of the first additional standard cells of the stage are connected. The first seismic signal input is adapted to input a first seismic drive signal.
In this embodiment, the standard cell test circuit layout further includes: a first frequency-dividing circuit 11 (refer to fig. 4 and 7 in combination), the first frequency-dividing circuit 11 being located at a side of the first unit circuit to be tested 10, the first frequency-dividing circuit 11 including Z1A first fractional frequency unit 112, Z1Is an integer of 1 or more; z th1The stage first frequency-dividing unit 112 includes: z th1Stage first timing flip-flop 110 and z1Stage first clock inverter 111, z1Is greater than or equal to 1 and less than or equal to Z1An integer of (d); the first timing flip-flop 110 of each stage has a first trigger pulse signal terminal, a first trigger data input terminal, and a first trigger output terminal; the first trigger pulse signal end of the first timing trigger 110 of the first stage is connected with the first shock output end; z th1The first trigger data input of the first timing flip-flop 110 of the stage is connected to the z-th trigger data input1The output of the first clock inverter 111 of the stage; z th1The first trigger output terminal of the first timing flip-flop 110 of the stage is connected to the z-th1The input of the first clock inverter 111 of the stage.
In FIG. 7, Z1Taking an integer greater than or equal to 2, in the first frequency-dividing unit 112 of two adjacent stages, the first trigger output end of the first timing flip-flop 110 of the previous stage is connected to the first trigger pulse signal end of the first timing flip-flop 110 of the next stage. Specifically, the first trigger output end of the first stage first timing trigger 110 is connected to the first trigger pulse signal end of the second stage first timing trigger 110, the first trigger output end of the second stage first timing trigger 110 is connected to the first trigger pulse signal end of the third stage first timing trigger 110, and the first trigger output end of the third stage first timing trigger 110 is connected to the first trigger pulse signal end of the fourth stage first timing trigger 110 sequentiallyAnd so on. In other embodiments, Z1Is 1.
In this embodiment, the first frequency divider 11 functions as: amplifying the delay of the first plurality of standard cells 100 when the first frequency-dividing circuit 11 includes Z1The delay of the first standard cells 100 is amplified by Z of 2 when the first frequency-division cell 112 is staged1To the power.
It should be noted that, when the first additional standard cell is provided, the function of the first frequency-dividing circuit includes: amplifying the total delay of the number of first standard cells and the number of first additional standard cells.
The standard cell test circuit layout further comprises: a first buffer 12, wherein the input end of the first buffer 12 is connected with the Z-th buffer1A first trigger output of the first timing flip-flop 110, said first buffer 12 being adapted to receive the Z-th signal1The output signal of the first frequency-division unit 112 is stepped and the Z-th frequency is corrected1The output signal of the stage first frequency-dividing unit 112.
In this embodiment, the delayed signal output from the first buffer 12 is divided by (Z of 2)1Power and N1The product of) is the delay of a single first standard cell 100.
When a first additional standard cell is set, the delay signal output from the first buffer is divided by (Z of 2)1Power of (N)1+W1) The product of) is the delay of a single first standard cell.
In this embodiment, the standard cell test circuit layout further includes: the second to qth unit circuits (not shown), Q is an integer greater than or equal to 2.
The kth unit circuit under test includes: and a plurality of stages of kth standard units, wherein k is an integer greater than or equal to 2 and less than or equal to Q.
The types of the first through Q-th standard cells are different, that is, the structures of the first through Q-th standard cells are different. The first labeled cells 100 have the same structure, and the k-th standard cells have the same structure.
In this embodiment, the operation tool for laying out the second to-be-tested unit circuit to the qth to-be-tested unit circuit is EDA.
The k-th standard cells of the plurality of levels are arranged into YkLine XkArray of columns, YkIs an even number of 4 or more, XkIs an integer of 4 or more.
For the YkLine XkThe array of columns, the connection relationship between the k standard cells is as follows:
in the kth standard cell of the first row, adjacent kth standard cells are connected; the Y thkIn the k standard cells of the row, adjacent k standard cells are connected; ithkLine first row to ikLine j (th)kAdjacent kth standard cells in the kth standard cell of the column are connected; ithkLine j (th)k+1 columns to ithkLine XkAdjacent kth standard cells in the kth standard cell of the column are connected; ithkLine j (th)kThe k standard cell and i standard cell of the columnkLine j (th)kThe kth standard cell of +1 column is off; ithk+1 line first row to ithkRow +1, jkAdjacent kth standard cells in the kth standard cell of the column are connected; ithkRow +1, jk+1 columns to ithk+1 line XkAdjacent kth standard cells in the kth standard cell of the column are connected; ithkRow +1, jkThe k standard cell and i standard cell of the columnkRow +1, jkThe kth standard cell of +1 column is off; ithkLine XkThe k standard cell and i standard cell of the columnkLine 1, XkThe kth standard cell of the column is connected, the YthkThe k standard cell and the Y standard cell in the first row and the first columnk-1 row first column kth standard cell connection, YkLine XkThe kth standard cell and the Yth standard cell of the columnkLine 1, XkThe kth standard cell of the column is connected, the ithkLine j (th)kThe k standard cell and i standard cell of the columnkRow +1, jkThe kth standard cell of the column is connected, the ithkLine j (th)k+1 th standard cell and ithkRow +1, jkThe kth standard cell of column +1 is connected; the kth standard cell of the second row and the first column and the first row and the first columnThe kth standard cell of (1) is off; i.e. ikIs 2 or more and Y or lesskAn even number of-2, jkIs 2 or more and X or lessk-an integer of 2; when i iskIs not less than 4 and not more than YkEven number of-2, ikThe k standard cell and i standard cell in the first row and columnk-1 row and first column of the kth standard cell connection.
In this example, Xk*Yk＝Nk，NkIs a composite number and is an even number.
In this embodiment, the k-th standard cell to the N-th standard cell of the first stagekThe kth standard cell of a stage, the kth standard cells of two adjacent stages being connected, specifically, the mth standard cellkOutput terminal of the kth standard cell and the mth standard cellkInput terminals of the kth standard cell of +1 stage are connected, mkIs greater than or equal to 1 and less than or equal to Nk-an integer of 1.
In this embodiment, the kth standard cell in the first row and the first column is the kth standard cell in the first level, and the kth standard cell in the second row and the first column is the nth standard cell in the second levelkStage kth standard cell.
In this example, when X iskWhen it is even, jkIs equal to Xk1/2, such benefits include: the accuracy of the subsequent calculation of the minimum value of the kth difference is improved.
In other embodiments, when XkWhen it is even, jkIs 2 or more and X or lessk-2 is any integer.
In this example, when X iskWhen it is odd, jkIs equal to (X)k-1)/2, or, when X iskWhen it is odd, jkIs equal to (X)k+1)/2. Such benefits include: the accuracy of the subsequent calculation of the minimum value of the kth difference is improved.
In other embodiments, when XkWhen it is odd, jkIs 2 or more and X or lessk-2 is any integer.
In the EDA tool, the position of the k standard unit is realized by adopting TCL scripting language, and the connection relation between the k standard units is realized by adopting Verilog language.
In this embodiment, the kth unit circuit to be tested further includes: the kth seismic unit is provided with a kth seismic connection input end, a kth seismic signal input end and a kth seismic output end; the kth vibration starting output end is connected with the input end of the kth standard unit of the first stage; the first seismic source is connected with the input end and the Nth seismic sourcekThe output ends of the kth standard unit of the stage are connected; the kth seismic signal input is adapted to input a kth seismic drive signal.
After the kth vibration starting signal input end receives the kth vibration starting driving signal input, the kth vibration starting unit starts to work and outputs a signal to the Nth vibration starting unitkStage kth standard cell.
In this embodiment, the standard cell test circuit layout further includes: a kth frequency dividing circuit located at a side of the kth unit-under-test circuit, the kth frequency dividing circuit including ZkStage kth frequency-dividing unit, ZkIs an integer of 1 or more; z thkThe stage kth frequency division unit includes: z thkStage kth timing flip-flop and zthkStage k clock inverter, zkIs greater than or equal to 1 and less than or equal to ZkAn integer of (d); the kth time sequence trigger of each stage is provided with a kth trigger pulse signal end, a kth trigger data input end and a kth trigger output end; a first trigger pulse signal end of a kth time sequence trigger of the first stage is connected with a kth vibration starting output end; z thkThe kth trigger data input terminal of the kth time sequence trigger of the stage is connected with the zkAn output of a kth clock inverter of a stage; z thkThe first trigger output terminal of the kth time sequence trigger of the stage is connected with the zkThe input of the kth clock inverter of a stage.
In one embodiment, ZkAnd taking an integer more than or equal to 2, and connecting a kth trigger output end of a kth time sequence trigger of a previous stage with a kth trigger pulse signal end of a kth time sequence trigger of a next stage in the kth frequency division unit of two adjacent stages. In other embodiments, ZkIs 1.
The standard cell test circuit layout further comprises: a kth buffer with an input terminal connected with the Z-th bufferkStage kth sequenceA kth trigger output of a flip-flop, the kth buffer adapted to receive the Z < th > signalkStage of output signal of kth frequency dividing unit and correcting the Z-th frequencykThe output signal of the kth frequency-dividing unit of the stage.
In this embodiment, the delay signal output from the kth buffer is divided by (Z of 2)kPower and x Nk) Is the delay of a single kth standard cell.
In this embodiment, the standard cell test circuit layout includes not only the first to-be-tested cell circuit but also the second to-be-tested cell circuit to the qth to-be-tested cell circuit, so that the standard cell test structure manufactured according to the standard cell test circuit layout also includes the first to-be-tested cell circuit and the second to-be-tested cell circuit to the qth to-be-tested cell circuit, and thus, the performance of various types of standard cells can be tested in one standard cell test structure, the manufacturing process is simplified, and the cost is reduced.
In other embodiments, the second to the qth cell circuits to be tested are not laid out in the standard cell test circuit layout.
It should be noted that, in other embodiments, the kth unit-under-test circuit further includes: several poled kth additional standard cells (W)kStage kth additional standard cell, WkIs an integer of 1 or more), the kth additional standard cell has the same structure and the same type as the kth standard cell. The number of kth additional standard cells is small, such as a few, a dozen or a dozen.
W thkThe output of the kth additional standard cell of a stage and the wkInput connection of kth additional standard cell of +1 stage, wkIs 1 or more and W or lessk-an integer of 1. N thkThe output of the kth standard cell of a stage is connected to the input of the kth additional standard cell of the first stage.
When the kth additional standard unit is arranged, the kth vibration starting output end is connected with the input end of the kth standard unit of the first stage; connecting the kth seismic input end with the Wth seismic input endkThe outputs of the kth additional standard cell of the stage are connected. The kth seismic signal input is adapted to input a kth seismic drive signal.
When the kth additional standard cell is set, the delay signal output from the kth buffer is divided by (Z of 2)kPower of (N)k+Wk) The product of) is the delay of a single kth standard cell.
Correspondingly, the present embodiment further provides a method for optimizing a standard cell test circuit layout, including:
providing the standard unit test circuit layout;
obtaining a first difference value C1First difference C1About X1And Y1Function of C1＝f(X1，Y1)。
Obtaining a first difference value C1The method comprises the following steps: the width W of the first standard cell 100 is acquired1And height H1The width direction of the first standard cell 100 is parallel to the row direction of the array formed by the plurality of levels of first standard cells 100, and the height direction of the first standard cell 100 is parallel to the column direction of the array formed by the plurality of levels of first standard cells 100; according to the width W of the first standard cell 1001And the number of columns X of the array formed by the plurality of levels of the first standard cells 1001Obtaining a first total length x1First total length x1Is equal to the width W of the first standard cell 1001And X1Product of (a), x1＝W1*X1(ii) a According to the height H of the first standard cell 1001And a number of rows Y of the array formed by the plurality of levels of the first standard cells 1001Obtaining a first total height y1First total height y1Equal to the height H of the first standard cell 1001And Y1Product of (a), y1＝H1*Y1(ii) a According to a first total height y1And a first total length x1Obtaining a first difference value C1First difference C1Equal to the absolute value of the difference between the first total height and the first total length, C1＝│x1-y1│。
From x1＝W1*X1、y1＝H1*Y1And C1＝│x1-y1| DeKnown as C1＝f(X1，Y1) The specific expression of (A) is as follows: c1＝│W1*X1-H1*Y1│。
The method for optimizing the standard unit test circuit layout further comprises the following steps: with X1*Y1＝N1Obtaining a first difference C as a constraint condition1Minimum value of, N1Is a complex number and is a constant; obtaining a first difference value C1Taking the minimum value X1And Y1The specific numerical value of (1).
Specifically, a first difference value C is obtained1The method of (3) comprises: with X1*Y1＝N1For constraint conditions, vary X1Value of (A) and Y1A value of (A), obtaining a number of X1A value of and a number of Y1A number of C under the condition of value of1A value of, comparing a number of C1To obtain C1Is measured.
When C is present1When the minimum value is obtained, the peripheral shape of the array formed by the plurality of first standard cells 100 is closer to a square, and the circuit layout area occupied by the plurality of first standard cells 100 is the minimum.
The method for optimizing the standard unit test circuit layout further comprises the following steps: obtaining the k-th difference CkThe k-th difference CkAbout XkAnd YkFunction of Ck＝f(Xk，Yk)。
Obtaining the k-th difference CkThe method comprises the following steps: obtaining the width W of the k standard cellkAnd height HkThe width direction of the kth standard unit is parallel to the row direction of the array formed by the plurality of levels of kth standard units, and the height direction of the kth standard unit is parallel to the column direction of the array formed by the plurality of levels of kth standard units; width W according to k standard cellkAnd the number of columns X of the array formed by the k standard cells of a plurality of levelskObtaining the kth total length xkK total length xkIs equal to the width W of the k standard cellkAnd XkProduct of (a), xk＝Wk*Xk(ii) a Height H according to k standard cellkAnd ifLine number Y of array formed by dry level k standard cellskTo obtain the k total height ykTotal k height ykIs equal to the height H of the kth standard cellkAnd YkProduct of (a), yk＝Hk*Yk(ii) a According to the k total height ykAnd k total length xkObtaining the k-th difference CkThe k-th difference CkEqual to the k total height ykAnd k total length xkAbsolute value of difference, Ck＝│xk-yk│。
From xk＝Wk*Xk、yk＝Hk*YkAnd Ck＝│xk-ykL is known, Ck＝f(Xk，Yk) The specific expression of (A) is as follows: ck＝│Wk*Xk-Hk*Yk│。
The method for optimizing the standard unit test circuit layout further comprises the following steps: with Xk*Yk＝NkObtaining the k-th difference value C as the constraint conditionkMinimum value of, NkIs a complex number and is a constant; obtaining the k-th difference CkTaking the minimum value XkAnd YkThe specific numerical value of (1).
Specifically, a kth difference value C is obtainedkThe method of (3) comprises: with Xk*Yk＝NkFor constraint conditions, vary XkValue of (A) and YkA value of (A), obtaining a number of XkA value of and a number of YkA number of C under the condition of value ofkA value of, comparing a number of CkTo obtain CkIs measured.
When C is presentkWhen the minimum value is obtained, the peripheral shape of the array formed by the plurality of kth standard cells is closer to a square, and the circuit layout area occupied by the plurality of kth standard cells is the minimum.
Correspondingly, the embodiment also provides a standard unit test structure manufactured according to the standard unit test circuit layout.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A standard cell test circuit layout, comprising:
a first unit circuit to be tested;
the first unit circuit to be tested includes: a plurality of levels of first standard cells, the plurality of levels of first standard cells being Y1Line X1Array of columns, Y1Is an even number of 4 or more, X1Is an integer of 4 or more;
in the first standard cells of the first row, adjacent first standard cells are connected; the Y th1In the first standard cells of the row, adjacent first standard cells are connected;
ith1Line first row to i1Line j (th)1Adjacent first standard cells in the first standard cells of the column are connected; ith1Line j (th)1+1 columns to ith1Line X1Adjacent first standard cells in the first standard cells of the column are connected; ith1Line j (th)1First standard cell and ith of column1Line j (th)1The first standard cell of +1 column is off; ith1+1 line first row to ith1Row +1, j1Adjacent first standard cells in the first standard cells of the column are connected; ith1Row +1, j1+1 columns to ith1+1 line X1Adjacent first standard cells in the first standard cells of the column are connected; ith1Row +1, j1First standard cell and ith of column1Row +1, j1The first standard cell of +1 column is off;
ith1Line X1First standard cell and ith of column1Line 1, X1The first standard cell of the column is connected, Yth1First standard cell and Y-th standard cell in first row and column1-1 row first column first standard cell connection, Yth1Line X1First standard cell and Y of column1Line 1, X1The first standard cell of the column is connected, the ith1Line j (th)1First standard cell and ith of column1Row +1, j1The first standard cell of the column is connected, the ith1Line j (th)1+1 column of the first standard cell and ith1Row +1, j1The first standard cell of +1 column is connected; the first standard cell of the second row and the first column is disconnected from the first standard cell of the first row and the first column;
i1is 2 or more and Y or less1An even number of-2, j1Is 2 or more and X or less1-an integer of 2;
when i is1Is not less than 4 and not more than Y1Even number of-2, i1First standard cell and ith of row and first column1-1 row first column first standard cell connection.
2. The standard cell test circuit layout of claim 1, wherein when X is1When it is even, j1Is equal to X11/2 of (1).
3. The standard cell test circuit layout of claim 1, wherein when X is1When it is odd, j1Is equal to (X)1-1)/2; or, when X1When it is odd, j1Is equal to (X)1+1)/2。
4. The standard cell test circuit layout of claim 1, wherein X is1*Y1＝N1，N1Is a composite number; m th1Output terminal of the first standard cell and m1Input terminals of + 1-stage first standard cells are connected, m1Is greater than or equal to 1 and less than or equal to N1-an integer of 1; the first standard cell in the first row and the first column is the first-level first standard cell, and the first standard cell in the second row and the first column is the Nth standard cell1The first standard cell is ranked.
5. According to the claimsSolving 4 the standard cell test circuit layout, wherein the first cell circuit to be tested further comprises: a first seismic unit having a first seismic connection input, a first seismic signal input, and a first seismic output; the first seismic output end is connected with the input end of the first-stage first standard unit; the first seismic source is connected with the input end and the Nth seismic source1The output ends of the first standard cells are connected; the first seismic signal input is adapted to input a first seismic drive signal.
6. The standard cell test circuit layout of claim 5, further comprising: a first frequency-dividing circuit located at a side of the first unit circuit to be tested, the first frequency-dividing circuit including Z1Stage one frequency-dividing unit, Z1Is an integer of 1 or more; z th1The first frequency-dividing unit includes: z th1Stage first timing flip-flop and z1Stage first clock inverter, z1Is greater than or equal to 1 and less than or equal to Z1An integer of (d); the first time sequence trigger of each stage is provided with a first trigger pulse signal end, a first trigger data input end and a first trigger output end;
a first trigger pulse signal end of a first timing trigger of the first stage is connected with a first shock output end;
z th1The first trigger data input terminal of the first time sequence trigger of the stage is connected with the z < th > signal1An output of a first clock inverter of a stage; z th1The first trigger output terminal of the first time sequence trigger of the stage is connected with the z-th1An input of a first clock inverter of a stage;
when Z is1When an integer greater than or equal to 2 is taken, in the first frequency division units of two adjacent stages, the first trigger output end of the first time sequence trigger of the previous stage is connected with the first trigger pulse signal end of the first time sequence trigger of the next stage.
7. The standard cell test circuit layout of claim 6, further comprising: a first buffer, saidThe input end of the first buffer is connected with the Z-th buffer1A first trigger output of the first timing flip-flop, the first buffer being adapted to receive the Z-th signal1Grading the output signal of the first frequency-dividing unit and correcting the Z-th signal1And (3) the output signal of the first frequency division unit.
8. The standard cell test circuit layout of claim 1, further comprising: the second unit circuit to be tested reaches the Q-th unit circuit to be tested, and Q is an integer more than or equal to 2;
the kth unit circuit under test includes: a plurality of levels of k standard cells, the k standard cells of the plurality of levels being YkLine XkArray of columns, YkIs an even number of 4 or more, XkIs an integer of 4 or more, k is an integer of 2 or more and Q or less;
in the kth standard cell of the first row, adjacent kth standard cells are connected; the Y thkIn the k standard cells of the row, adjacent k standard cells are connected;
ithkLine first row to ikLine j (th)kAdjacent kth standard cells in the kth standard cell of the column are connected; ithkLine j (th)k+1 columns to ithkLine XkAdjacent kth standard cells in the kth standard cell of the column are connected; ithkLine j (th)kThe k standard cell and i standard cell of the columnkLine j (th)kThe kth standard cell of +1 column is off; ithk+1 line first row to ithkRow +1, jkAdjacent kth standard cells in the kth standard cell of the column are connected; ithkRow +1, jk+1 columns to ithk+1 line XkAdjacent kth standard cells in the kth standard cell of the column are connected; ithkRow +1, jkThe k standard cell and i standard cell of the columnkRow +1, jkThe kth standard cell of +1 column is off;
ithkLine XkThe k standard cell and i standard cell of the columnkLine 1, XkThe kth standard cell of the column is connected, the YthkThe k standard cell and the Y standard cell in the first row and the first columnk-1 row first column kth standard cell connection, YkLine XkThe kth standard cell and the Yth standard cell of the columnkLine 1, XkThe kth standard cell of the column is connected, the ithkLine j (th)kThe k standard cell and i standard cell of the columnkRow +1, jkThe kth standard cell of the column is connected, the ithkLine j (th)k+1 th standard cell and ithkRow +1, jkThe kth standard cell of column +1 is connected; the kth standard cell of the second row and the first column is disconnected from the kth standard cell of the first row and the first column;
ikis 2 or more and Y or lesskAn even number of-2, jkIs 2 or more and X or lessk-an integer of 2;
when i iskIs not less than 4 and not more than YkEven number of-2, ikThe k standard cell and i standard cell in the first row and columnk-1 row and first column of the kth standard cell connection.
9. A method for optimizing a standard cell test circuit layout is characterized by comprising the following steps:
providing a standard cell test circuit layout according to any one of claims 1 to 8;
obtaining a first difference value, the first difference value being related to X1And Y1A function of (a);
the method for acquiring the first difference value comprises the following steps: acquiring the width and the height of a first standard cell, wherein the width direction of the first standard cell is parallel to the row direction of an array formed by a plurality of levels of first standard cells, and the height direction of the first standard cell is parallel to the column direction of the array formed by the plurality of levels of first standard cells; obtaining a first total length according to the width of the first standard unit and the number of columns of the array formed by the plurality of levels of the first standard units, wherein the first total length is equal to the width and X of the first standard unit1The product of (a); obtaining a first total height according to the height of the first standard cell and the number of rows of the array formed by the plurality of levels of the first standard cells, wherein the first total height is equal to the height of the first standard cell and Y1The product of (a); according to a first total height and a firstAcquiring a first difference value of the total length, wherein the first difference value is equal to the absolute value of the difference value of the first total height and the first total length;
the method for optimizing the standard unit test circuit layout further comprises the following steps: with X1*Y1＝N1Obtaining the minimum value of the first difference, N, as the constraint condition1Is a complex number and is a constant; x when the first difference value is obtained and the minimum value is taken1And Y1The specific numerical value of (1).
10. A standard cell test structure fabricated according to the standard cell test circuit layout of any of claims 1 to 8.
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