JP2014011768A - A/d converter and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter that implements improved conversion accuracy, and a semiconductor device having the A/D converter.SOLUTION: A DAC 10 has a plurality of capacitive elements Cu connected to a high side reference voltage AVRTC or a low side reference voltage AVRBC in response to a value of a successive approximation register. A reference voltage generation circuit 50 has a first capacitive element connected to the high side reference voltage AVRTC, and a second capacitive element connected to the low side reference voltage AVRBC. A comparator 30 compares an output of the DAC 10 and an output of the reference voltage generation circuit 50.

Description

  The present invention relates to a semiconductor device including an A / D (Analog / Digital) converter and an A / D converter, for example, a semiconductor including a successive approximation type A / D converter and a successive approximation type A / D converter. Relates to the device.

  A system (for example, a mobile phone, a smartphone, an audio device, etc.) equipped with an A / D (Analog / Digital) converter is widely used. For A / D converters, improvement in conversion performance is required. For example, as a technique related to the conversion accuracy of A / D conversion, Patent Document 1 discloses an A / D converter that significantly reduces the number of external terminals and performs highly accurate A / D conversion.

  Here, a general single-end input type charge redistribution successive approximation A / D converter will be considered. The A / D converter samples an analog input signal with a local DAC (Digital / Analog Converter), and generates a difference voltage between the sampled voltage value and a voltage value generated by the local DAC according to the successive approximation register. . A reference voltage generation circuit (CIN) generates a reference voltage to be compared with the difference voltage. The preamplifier amplifies the difference voltage and the reference voltage and supplies an amplified signal to the comparator. The comparator performs comparison processing according to the input signal and reflects the comparison result in the successive approximation register.

JP 2011-82879 A

  The local DAC has a plurality of capacitive elements (Cu), and each capacitive element is connected to the Lo-side reference potential AVRBC or the Hi-side reference potential AVRTC according to the comparison result of the comparator. Here, the larger the digital value (hereinafter also referred to as a code) output from the A / D converter, the more capacitive elements are connected to the Hi-side reference potential AVRTC. On the other hand, the smaller the code, the more capacitive elements are connected to the Lo-side reference potential AVRBC. Therefore, when the code is small, the amount of noise due to the Lo-side reference voltage AVRBC increases. On the other hand, the larger the code, the larger the amount of noise caused by the Hi-side reference voltage AVRTC.

  Since the noise sensitivity in the local DAC is determined according to the connection destination of each capacitive element, it has the same characteristics as the noise amount described above. That is, when the code is small, the noise sensitivity related to the Lo-side reference voltage AVRBC increases, and as the code increases, the noise sensitivity related to the Hi-side reference voltage AVRTC increases.

  On the other hand, the reference voltage generation circuit (CIN) generally has only a capacitive element connected to the Lo-side reference voltage AVRBC. Therefore, the noise sensitivity in the reference voltage generation circuit (CIN) is constant regardless of the size of the code.

  That is, the noise sensitivity in the local DAC and the noise sensitivity in the reference voltage generation circuit (CIN) have different characteristics. In general, the difference between the noise amount of the output signal of the reference voltage generation circuit (CIN) and the noise amount of the output signal of the local DAC appears as an error in the A / D converter. Therefore, there has been a problem that the larger the code, the larger the A / D conversion error.

  The problem is not limited to the single-ended input type charge redistribution successive approximation A / D converter, but the successive approximation A / D conversion using a reference voltage generation circuit (CIN) having a capacitive element therein. It is a problem common to circuits.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the A / D converter in the semiconductor device includes a first capacitor element connected to the Hi-side reference voltage in the reference voltage generation circuit, and a second capacitor element connected to the Lo-side reference voltage. Is provided.

  According to the embodiment, a successive approximation A / D converter with improved conversion accuracy can be provided.

1 is a block diagram showing an overall configuration of a successive approximation A / D (Analog / Digital) converter according to a first embodiment; 2 is a diagram illustrating an internal configuration (DAC 10 and a reference voltage generation circuit 50) of a successive approximation A / D converter according to a first embodiment; FIG. FIG. 3 is a diagram illustrating an operation of the successive approximation A / D converter according to the first embodiment. 2 is a diagram illustrating a layout example of a successive approximation A / D converter according to a first embodiment; FIG. 2 is a diagram illustrating a layout example of a successive approximation A / D converter according to a first embodiment; FIG. FIG. 3 is a diagram illustrating a mechanism of noise propagation of the successive approximation A / D converter according to the first embodiment. FIG. 3 is a diagram illustrating a mechanism of noise propagation of the successive approximation A / D converter according to the first embodiment. FIG. 6 is a diagram showing a modification of the internal configuration (DAC 10 and reference voltage generation circuit 50) of the successive approximation A / D converter according to the first embodiment. It is a figure which shows the example of a layout of the successive approximation type A / D converter shown in FIG. It is a figure which shows the example of a layout of the successive approximation type A / D converter shown in FIG. FIG. 6 is a diagram showing a modification of the internal configuration (DAC 10 and reference voltage generation circuit 50) of the successive approximation A / D converter according to the first embodiment. 2 is a diagram illustrating an internal configuration (DAC 10 and a reference voltage generation circuit 50) of a successive approximation A / D converter according to a first embodiment; FIG. FIG. 3 is a diagram illustrating an operation of the successive approximation A / D converter according to the first embodiment. 3 is a diagram showing a configuration of a semiconductor integrated circuit on which the successive approximation A / D converter 1 described in the first or second embodiment is mounted. FIG.

<Embodiment 1>
The configuration of the A / D converter according to this embodiment will be described below with reference to the drawings. First, the successive approximation A / D converter according to the present embodiment will be described. An example of the successive approximation A / D converter according to this embodiment is a single-ended input type charge redistribution successive approximation A / D converter.

  FIG. 1 is a block diagram showing the overall configuration of a successive approximation A / D (Analog / Digital) converter. The successive approximation type A / D converter 1 includes a DAC (Digital / Analog Converter) 10, a preamplifier 20, a comparator 30, a SAR (Successive Application Register) logic unit 40, and a reference voltage generation circuit 50. The successive approximation A / D converter 1 is supplied with a Hi-side reference voltage AVRTC and a Lo-side reference voltage AVRBC (not shown). The successive approximation A / D converter 1 samples an input analog signal (Ain) and calculates a digital value by performing a successive approximation process using the sampled value.

  The preamplifier 20 has two input terminals. One input terminal of the preamplifier 20 is connected to the output (DACOUTP) of the DAC 10. The other input terminal of the preamplifier 20 is connected to the output (DACOUTN) of the reference voltage generation circuit 50. The output terminals of the preamplifier 20 are connected to the input terminals of the comparator 30 respectively.

  The comparator 30 compares the two input voltage values, and writes a value to the successive approximation register in the SAR logic unit 40 according to the comparison result.

  The SAR logic unit 40 has a successive approximation register therein. This successive approximation register is rewritten according to the comparison result of the comparator 30. The SAR logic unit 40 outputs a control signal Ctr for controlling a switch (a switch SW5 described later) in the DAC 10 using the value of the successive approximation register. Further, the SAR logic unit 40 supplies the calculated digital value (code) to an arbitrary processing unit (not shown) after calculating the digital value (code). The configuration of the preamplifier 20, the comparator 30, and the SAR logic unit 40 may be any configuration that is generally used in a successive approximation A / D converter.

  Next, the internal configuration of the DAC 10 and the reference voltage generation circuit 50 according to FIG. 1 will be described with reference to FIG. In FIG. 2, the DAC 10 is a charge redistribution type DAC having a sampling capacitor Cs. The analog signal Ain is input to the DAC 10 via the signal source resistor Rsig.

  The DAC 10 includes a cell having one switch SW3, SW4, and SW5 for each unit capacitive element Cu, as many as the required number of bits (according to the resolution). The switch SW3 (third switch) is turned on during the sampling process and turned off during the successive approximation process. Thereby, all the switches SW3 are connected to the analog signal Ain during the sampling process, and the input voltage is charged to the unit capacitive element Cu. In this way, the DAC 10 realizes a sampling function.

  The switch SW4 (second switch) is turned off during the sampling process and turned on during the successive approximation process. Each of the switches SW5 (first switch) is connected to either the Hi-side reference voltage AVRTC or the Lo-side reference voltage AVRBC in accordance with the control signal Ctr supplied from the SAR logic unit 40. Here, the number of switches SW5 connected to the Hi-side reference voltage AVRTC (or Lo-side reference voltage AVRBC) is determined according to the code size when the analog signal Ain is digitized. Specifically, as the code when digitized becomes larger, the number of switches SW5 connected to the Hi-side reference voltage AVRTC increases. On the other hand, as the code when digitized becomes smaller, the number of switches SW5 connected to the Lo-side reference voltage AVRBC increases. The switch SW5 is switched to the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC according to the control signal Ctr to generate a comparison voltage used for the next successive comparison. Then, the digital value to be output is sequentially determined from the MSB (Most Significant Bit) by performing the successive comparison process in the comparator 30 described above.

  Next, the configuration of the reference voltage generation circuit 50 will be described. A general reference voltage generation circuit includes a single capacitive element Cs having a capacitance value approximately equal to the total value of all the unit capacitive elements Cu in the DAC 10. On the other hand, the reference voltage generation circuit 50 (FIG. 2) according to the present embodiment has two capacitive elements (hereinafter also referred to as a first capacitive element and a second capacitive element). The first capacitive element and the second capacitive element each have a capacitance value that is approximately ½ of the total capacitance value of all the capacitive elements Cu in the DAC 10. In other words, the first capacitive element and the second capacitive element each have a capacitance value (Cs / 2) that is approximately ½ of the capacitive element Cs in the general reference voltage generation circuit 50. Furthermore, the reference voltage generation circuit 50 includes switches SW3-1, SW3-2, SW4-1, and SW4-2. One set (switches SW3-1 and SW4-1) is connected to one end of the first capacitive element. The other set (switches SW3-2 and SW4-2) is connected to one end of the second capacitive element.

  Further, a resistor simulating the signal source resistor Rsig is inserted in the reference voltage generation circuit 50. The resistor Rsig is disposed between the switch SW3 and the Lo side reference voltage AVRBC. The resistance Rsig can improve noise resistance during the sampling process.

  The reference voltage generation circuit 50 is supplied with a Hi-side reference voltage AVRTC and a Lo-side reference voltage AVRBC. The Hi-side reference voltage AVRTC is supplied to one end of the first capacitive element via the switch SW3-1 (fourth switch) or the switch SW4-1 (sixth switch). More specifically, the Hi-side reference voltage AVRTC is supplied to one end of the first capacitor element via the signal source resistor Rsig and the switch SW3-1 during sampling, and the switch SW4-1 is turned on during the successive approximation process. The Hi-side reference voltage AVRTC is supplied through

  The Lo-side reference voltage AVRBC is supplied to one end of the second capacitive element via the switch SW3-2 (fifth switch) or the switch SW4-2 (sixth switch). Specifically, the Lo-side reference voltage AVRBC is supplied to one end of the second capacitor element via the signal source resistor Rsig and the switch SW3-2 during the sampling procedure, and the switch SW4-2 is turned on during the successive approximation process. Through this, the Lo-side reference voltage AVRBC is supplied.

  The other end of the first capacitive element and the other end of the second capacitive element are connected in parallel and connected to the input terminal (DACOUTN) of the preamplifier 20. A voltage source (not shown) (for example, 1/2 * VCCA) is connected to the first capacitor element and the second capacitor element. The first capacitor element and the second capacitor element generate a reference voltage to be input to the comparator 30 by sampling the output value of the voltage source. Note that a similar voltage source is also connected to the DAC 10 during the above-described sampling by the first capacitor element and the second capacitor element.

  Next, the operation of the successive approximation A / D converter 1 according to the present embodiment will be described with reference to FIG. As described above, the successive approximation type A / D converter 1 first performs sampling processing of the analog signal Ain, and then performs successive comparison processing. During the sampling process, the switches SW3 (3-1, 3-2) in the DAC 10 and the reference voltage generation circuit 50 are turned on, and the switches SW4 (4-1, 4-2) are turned off.

  When shifting from the sampling process to the successive approximation process, the switches SW3, 3-1, 3-2 are turned off, and the switches SW4, 4-1, 4-2 are turned on. Each of the switches SW5 in the DAC 10 is connected to either the Hi-side reference voltage AVRTC or the Lo-side reference voltage AVRBC according to the control signal Ctr supplied from the SAR logic unit 40. The connection destination of the switch SW5 can be switched by the number of times corresponding to the bit width of the output code of the successive approximation A / D converter 1. Noise is generated at the timing when the connection destination of the switch SW5 is switched according to the control signal Ctr as shown in FIG.

  Next, an example of a layout in a part of the successive approximation A / D converter 1 according to the above-described embodiment will be described. FIG. 4 is a diagram illustrating a first layout example of the semiconductor device including the successive approximation A / D converter 1 according to the first embodiment.

  In FIG. 4, the DAC 10 is laid out above, and the reference voltage generation circuit 50 is laid out below. In the DAC 10, the switches SW3, SW4, and SW5 are arranged in a straight line over a plurality of rows. The unit capacitive elements Cu are arranged linearly over a plurality of rows below the switch group. In the reference voltage generation circuit 50, the switches SW3-1 and 3-2 and SW4-1 and 4-2 are arranged on the left side, and the first capacitor element (Cs / 2) and the second capacitor element (Cs) on the right side. / 2) is arranged.

  FIG. 5 is a diagram illustrating a second layout example of the semiconductor device including the successive approximation A / D converter 1 according to the first embodiment. In the DAC 10, the columns of the switches SW3, SW4, and SW5 and the rows of the unit capacitive elements Cu are alternately arranged. In the reference voltage generation circuit 50, the switches SW3-1, 3-2, 4-1, and 4-2 are arranged on the left side, and the first capacitor element (Cs / 2) and the second capacitor element (Cs) are arranged on the right side. / 2) is arranged.

  4 and 5, the first capacitor element and the second capacitor element are arranged in the vertical direction (column direction). However, the present invention is not limited to this, and the first capacitor element and the second capacitor element may be arranged in the horizontal direction (row direction). May be aligned. Similarly, the switches SW3, SW4, and SW5 and the unit capacitance elements in the DAC 10 may be aligned in the row direction or in the column direction.

  Next, with reference to FIGS. 6 and 7, the effects of the present embodiment will be described by describing the noise propagation of the successive approximation A / D converter 1 shown in FIGS. In the following description, for the sake of clarity of explanation, only noise generated in the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC is handled. Further, noise propagation when the switches SW4, 4-1, and 4-2 are ON (that is, during the successive comparison process) is targeted.

  FIG. 6A is a diagram illustrating a relationship between a code (an output digital value of the successive approximation A / D converter 1) and a noise amount caused by each reference voltage. Noise of the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC is generated in the DAC 10. As the code becomes smaller, the number of switches SW5 connected to the Lo-side reference voltage AVRBC increases. Therefore, when the code is small, the amount of noise due to the Lo-side reference voltage AVRBC increases. On the other hand, as the code increases, the number of switches SW5 connected to the Hi-side reference voltage AVRTC increases. Therefore, the larger the code, the larger the amount of noise caused by the Hi-side reference voltage AVRTC.

  FIG. 6 (2) shows the noise sensitivity of the DAC 10. The noise sensitivity of the DAC 10 is determined by the connection destination of the switch SW5. Therefore, FIG. 6 (2) has the same characteristics as FIG. 6 (1). Specifically, the noise sensitivity of the Lo side reference voltage AVRBC increases as the code becomes smaller. On the other hand, the noise sensitivity of the Hi-side reference voltage AVRTC increases as the code increases.

  FIG. 6 (3) shows the noise sensitivity of the reference voltage generation circuit 50. FIG. 6 (3) also shows the noise sensitivity (AVRBC ′) of a general reference voltage generation circuit 50 (a configuration having only a capacitive element Cs connected to the Lo-side reference voltage AVRBC ′) (one point). (Indicated by a chain line). In the reference voltage generation circuit 50, the connection destination is not switched by the switch SW5 regardless of the configuration of the present embodiment or the general configuration. For this reason, the noise sensitivity of the Lo-side reference voltage AVRBC ′ of the reference voltage generation circuit 50 having a general configuration is constant as shown (one-dot chain line in the figure). Since the reference voltage generation circuit 50 having a general configuration does not have a capacitive element connected to the Hi-side reference voltage AVRTC, it is not affected by noise due to the Hi-side reference voltage AVRTC.

  The reference voltage generation circuit 50 according to the present embodiment includes a first capacitor element and a second capacitor element having a capacitance value that is ½ of the total capacitance value of the unit capacitor elements Cu in the DAC 10. The first capacitor element and the second capacitor element are connected to the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC, respectively. Therefore, the reference voltage generation circuit 50 has noise sensitivity characteristics regarding both the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC. Here, the first capacitive element and the second capacitive element have a capacitance value that is ½ of the capacitive element Cs in the reference voltage generation circuit in a general configuration. Therefore, as shown in FIG. 6 (3), the noise sensitivities of the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC are about ½ of the noise sensitivities of the Lo-side reference voltage AVRBC ′ having a general configuration.

  FIG. 7 (4) shows the amount of noise generated in DACOUTP (the amount of noise generated in the output of DAC 10). This noise amount (FIG. 7 (4)) is a value obtained by multiplying the noise amount shown in FIG. 6 (1) by the noise sensitivity shown in FIG. 6 (2).

  FIG. 7 (5) shows the amount of noise generated at DACOUTN (noise generated at the output of the reference voltage generation circuit 50). FIG. 7 (5) also displays the amount of noise generated at the output of the reference voltage generation circuit 50 in a general configuration (displayed with a one-dot chain line). The noise amount (FIG. 7 (5)) is a value obtained by multiplying the noise amount shown in FIG. 6 (1) by the noise sensitivity shown in FIG. 6 (3). Therefore, the maximum noise amount of the Lo-side reference voltage AVRBC in the present embodiment is ½ of the maximum noise amount of a general configuration.

  FIG. 7 (6) shows the difference in noise amount between DACOUTP and DACOUTN (noise difference of the input to the preamplifier 20). 7 (6) is a noise amount obtained by subtracting the noise amount shown in FIG. 7 (5) from the noise amount shown in FIG. 7 (4). The noise amount appears as an A / D conversion error of the successive approximation type A / D converter 1 as a whole. FIG. 7 (6) also shows the difference in noise amount between DACOUTP and DACOUTN in a general configuration. In the following description, the noise difference according to the former (this embodiment) is N, and the noise difference according to the latter (general configuration) is N ′.

  In a general configuration, noise sensitivity differs between the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC. Due to the difference in noise sensitivity, the larger the code to be output, the greater the noise difference (N ′), and the greater the A / D conversion error.

  In the configuration according to the present embodiment, as described above, the reference voltage generation circuit 50 has noise sensitivity characteristics related to both the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC. Therefore, in the configuration according to the present embodiment (FIG. 2), even when the code is large, the noise sensitivity due to the Hi-side reference voltage AVRTC is close to the characteristic between the DAC 10 and the reference voltage generation circuit 50. . As a result, the noise difference (N) when the code is maximum is ½ of the noise difference (N ′) of the general configuration. When the code is an intermediate value (I in FIG. 7 (6)), the noise sensitivity of the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC match, so that the best characteristic (noise amount is minimized) can be obtained. . The ideal value of the noise difference (N) when the code is an intermediate value (I in FIG. 7 (6)) is 0 as shown.

  As shown in FIG. 7 (6), the maximum value of the noise difference (N) is ½ of the maximum value of the noise difference (N ′), and the amount of noise decreases as the code approaches the intermediate value. Therefore, in the configuration of the present embodiment, the total noise amount can be reduced as compared with the general configuration (FIG. 7 (6) the area of the hatched portion is larger than the area surrounded by the one-dot chain line in FIG. 7 (6). small). Since the noise output from the A / D converter is reduced, the accuracy of A / D conversion can be improved. By improving the A / D conversion accuracy, it is possible to share the power supply pins and improve the conversion speed.

(Modification 1)
A first modification of the successive approximation A / D converter 1 according to the first embodiment will be described below. FIG. 8 is a block diagram showing a configuration of a first modification of the successive approximation A / D converter 1. The successive approximation A / D converter 1 according to this example has a configuration in which the unit capacitor element Cu is also applied to the reference voltage generation circuit 50. The configuration of the DAC 10 is the same as that shown in FIG.

  The reference voltage generation circuit 50 has the same number of unit capacitive elements Cu as the DAC 10 inside. The reference voltage generation circuit 50 has two cell groups (51, 52). The cell group 51 is composed of ½ unit capacitors Cu of the total number of unit capacitors Cu in the DAC 10. Each unit capacitor Cu in the cell group 51 is connected to the Hi-side reference voltage AVRTC via the switch SW3 or the switch SW4. Similarly, the cell group 52 is composed of ½ unit capacitors Cu of the total number of unit capacitors Cu in the DAC 10. Each unit capacity Cu in the cell group 52 is connected to the Lo side reference voltage AVRBC via the switch SW3 or the switch SW4. Since the opening / closing operation of each switch (SW3, SW4, SW5) is the same as that of the switch having the same symbol in FIG. 2, detailed description thereof is omitted.

  Even in this configuration, the reference voltage generation circuit 50 has a capacitive element connected to the Lo-side reference voltage AVRBC and the Hi-side reference voltage AVRTC, and thus relates to both the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC. Has noise sensitivity characteristics. Thereby, as shown in FIG.6 and FIG.7, an A / D conversion error can be reduced compared with a general structure.

  FIG. 9 is a diagram showing a first layout example of Modification 1 shown in FIG. In FIG. 9, the DAC 10 is laid out above, and the reference voltage generation circuit 50 is laid out below. In the DAC 10, the switches SW3, SW4, and SW5 are arranged in a straight line on a plurality of rows in the upper part. The unit capacitive elements Cu are arranged linearly over a plurality of rows below the switch group. In the reference voltage generation circuit 50, unit capacitive elements Cu are arranged in a straight line over a plurality of columns. Below that, switches SW3 and SW4 are arranged linearly over a plurality of rows.

  FIG. 10 is a diagram showing a second layout example of Modification 1 shown in FIG. In the DAC 10, the rows of switches SW3, SW4, and SW5 and the rows of unit capacitive elements Cu are alternately arranged. Even in the reference voltage generation circuit 50, the columns of the switches SW3 and SW4 and the column of the unit capacitor elements Cu are alternately arranged.

  Next, the layout of the configuration shown in FIG. 2 (FIGS. 4 and 5) and the layout of the configuration shown in FIG. 8 (FIGS. 9 and 10) are compared. As shown in the figure, in the layout of the configuration shown in FIG. 8 (FIGS. 9 and 10), it is necessary to arrange a plurality of unit capacitance elements Cu and switches SW3 and SW4 in the reference voltage generation circuit 50. At this time, it is necessary to provide a certain gap between each unit capacitive element Cu and the switches (SW3, SW4). The gap becomes a dead space that cannot be effectively used, and causes an increase in chip area.

  On the other hand, in the layout of the configuration shown in FIG. 2 (FIGS. 4 and 5), the first capacitor element, the second capacitor element, and the switch SW3-1 connected to these capacitor elements in the reference voltage generation circuit 50, Only SW3-2, SW4-1, and SW4-2 are arranged. Since the reference voltage generation circuit 50 is configured based on such a small number of elements (two capacitors + switches corresponding to the capacitors), the layout of the configuration shown in FIG. 9 and FIG. 10), and the chip area can be minimized.

(Modification 2)
A second modification of the successive approximation A / D converter 1 according to the first embodiment will be described below. FIG. 11 is a block diagram illustrating a configuration of a second modification of the successive approximation A / D converter 1. The successive approximation A / D converter 1 includes a sample and hold circuit 60 whose configuration substantially corresponds to the reference voltage generation circuit 50. The successive approximation A / D converter 1 samples an analog signal (Ain) through a signal source resistor Rsig in a sample and hold circuit 60. The preamplifier 20 amplifies the difference between the sampled analog signal (Ain) and the output voltage of the DAC 10 generated by the control by the control signal Ctr.

  The sample and hold circuit 60 has a switch SW3 therein. An analog signal (Ain) is input to one end of the switch SW3, and the other end is connected to the input terminal of the preamplifier 20 (DACOUTN). The switch SW3 is turned on during the sampling process and turned off during the successive comparison process. Thereby, the sample & hold circuit 60 samples the analog signal (Ain). At the time of successive comparison processing, comparison processing using the sampled charges is performed.

  The sample and hold circuit 60 includes a first capacitor element and a second capacitor element as in FIG. A Hi-side reference voltage AVRTC is supplied to one end of the first capacitive element. The Lo-side reference voltage AVRBC is supplied to one end of the second capacitor element. The other end of the first capacitive element and the other end of the second capacitive element are connected in parallel and connected to the input terminal of the preamplifier 20.

  Even in this configuration, the sample-and-hold circuit 60 connects the Lo-side reference voltage AVRBC and the Hi-side reference voltage AVRTC to the capacitor. Therefore, the sample and hold circuit 60 has noise sensitivity characteristics regarding both the Hi-side reference voltage AVRTC and the Lo-side reference voltage AVRBC. Thereby, as shown in FIG.6 and FIG.7, an A / D conversion error can be reduced compared with a general structure.

<Embodiment 2>
The successive approximation A / D converter 1 according to the present embodiment is characterized in that the equivalence between the DAC 10 and the reference voltage generation circuit 50 is further improved. Hereinafter, the difference between the successive approximation A / D converter according to the present embodiment and the first embodiment will be described.

  The overall configuration of the successive approximation A / D converter 1 according to the present embodiment may be substantially the same as that shown in FIG. FIG. 12 is a diagram illustrating a configuration of the DAC 10 and the reference voltage generation circuit 50 according to the present embodiment. The configuration and operation of the DAC 10 are substantially the same as those in FIG.

  In addition to the configuration shown in FIG. 2 (Embodiment 1), the reference voltage generation circuit 50 includes switches SW6-1 (eighth switch) and SW6-2 (ninth switch). One end of the switch SW6-1 is connected to the Hi-side reference voltage AVRTC. The other end of the switch SW6-1 is connected to a switch SW4-1 (sixth switch) connected to the first capacitor. One end of the switch SW6-2 is connected to the Lo side reference voltage AVRBC. The other end of the switch SW6-2 is connected to a switch SW4-2 (seventh switch) connected to the second capacitor element. The switches SW6-1 and SW6-2 are turned on during the successive comparison process.

  The switch SW6-1 is about half of the total W value of each switch SW5 in the DAC 10. That is, the switch SW6-1 has a gate width that is about ½ of the total gate width of all the switches SW5 in the DAC 10. The switch SW6-2 is about half the total W value of the switch SW5 in the DAC 10. That is, the switch SW6-2 has a gate width that is approximately ½ of the total gate width of all the switches SW5 in the DAC 10.

  The switch SW3-1 (fourth switch) connected to the first capacitive element is about half the total W value of the switch SW3 in the DAC 10. That is, the switch SW3-1 connected to the first capacitor element has a gate width that is approximately ½ of the total gate width of all the switches SW3 in the DAC 10. Similarly, the switch SW3-2 (fifth switch) connected to the second capacitor element has a gate width that is about ½ of the total gate width of all the switches SW3 in the DAC 10. The switch SW4-1 connected to the first capacitive element has a gate width that is approximately ½ of the total gate width of all the switches SW4 in the DAC 10. Similarly, the switch SW4-2 connected to the second capacitor element has a gate width that is about ½ of the total gate width of all the switches SW4 in the DAC 10. The opening / closing operation of each switch is the same as that of each switch given the same reference numeral in the first embodiment.

  The first capacitive element is connected to the Hi-side reference voltage AVRTC via the signal source resistor Rsig and the switch SW3-1 at the time of sampling. Each unit capacitor Cu in the DAC 10 is also connected to the Hi-side reference voltage AVRTC via the signal source resistor Rsig and the switch SW3 during sampling.

  The first capacitor element is connected to the Hi-side reference voltage AVRTC via the switch 6-1 (having a gate width of about ½ of the gate width of all the switches SW5 in the DAC 10) and the switch SW4-1 during the successive approximation process. Connecting. Each unit capacitor Cu in the DAC 10 is also connected to the Hi-side reference voltage AVRTC or the Lo-side reference voltage AVRBC via the switch SW5 and the switch SW4 at the time of successive comparison.

  That is, the first capacitor element is connected to the Hi-side reference voltage AVRTC by the same connection method as each unit capacitor element Cu in the DAC 10 at the time of sampling and successive approximation processing. For example, both the unit capacitive element and the first capacitive element in the DAC 10 are connected to the signal resistance source Rsig and the switch SW3 (SW3-1) during sampling. By matching the connection method in the DAC 10 and the connection method in the reference voltage generation circuit 50, the equivalence between the DAC 10 and the reference voltage generation circuit 50 can be further increased as compared with the first embodiment. By increasing the equivalence, the noise sensitivity of the DAC 10 and the noise sensitivity of the reference voltage generation circuit 50 can be made more approximate.

  Further, each of the switches SW3-1, SW4-1, and SW6-1 has a gate width determined according to the gate width of the switch in the DAC 10. The second capacitor element is exactly the same as the first capacitor element. Thus, by making the gate width of the switch in the DAC 10 correspond to the gate width of the switch in the reference voltage generation circuit 50, the equivalence between both circuits is further increased, and the noise sensitivity of the DAC 10 and the noise of the reference voltage generation circuit 50 are increased. Sensitivity can be more approximate

  FIG. 13 is a time chart illustrating an operation image of the successive approximation A / D converter 1 according to the first embodiment. At the time of sampling, the switches SW3, SW3-1, and SW3-2 are turned on, and the switches SW4, SW4-1, SW4-2, switch SW5, switch SW6-1, and SW6-2 are turned off. When sampling is completed, the switches SW3, SW3-1, and SW3-2 are turned off, and the switches SW4, SW4-1, SW4-2, SW6-1, and SW6-2 are turned on. The switch SW5 is connected to the Hi-side reference voltage AVRTC or the Lo-side reference voltage AVRBC according to the control signal Ctr. Noise is generated when each comparison value is generated in accordance with the control signal Ctr (arrow part in FIG. 13).

<Usage example of successive approximation type A / D converter>
FIG. 14 is a diagram illustrating a configuration of a data processing device in which the successive approximation A / D converter 1 described in the first or second embodiment is mounted. As illustrated, the semiconductor chip IC_Chip 100 of the data processing apparatus includes an analog core unit 110 and a digital core unit 120. The data processing device is, for example, a general audio device or a mobile terminal device.

  The analog core unit 110 includes an MPX 111 and an A / D conversion unit 112. The A / D conversion unit 112 includes the successive approximation A / D converter 1 according to the first or second embodiment and the data register 113. The MPX (analog multiplexer) 111 has analog input terminals AN0 to AN7, and supplies the selected analog signal to the successive approximation A / D converter 1. The successive approximation A / D converter 1 converts an analog signal into a digital signal and writes the digital signal in the data register 113 as described above.

  The digital core unit 120 includes a CPU (Central Processing Unit) 121, a BSC (Bus Switch Controller) 122, a ROM (Read Only Memory) 123, a RAM (Random Access Memory) 124, and an NVFlash (flash nonvolatile memory device). 125. The CPU 121 is connected to peripheral devices Periph_Cir 130 and Periph_Cir 140 via a CPU bus CPU_Bus, a control line Cntr_Lines, and a peripheral bus Periph_Bus.

  The digital signal output from the successive approximation A / D converter 1 can be supplied to the CPU 121 via the peripheral buses Periph_Bus, BSC 122, and the CPU bus CPU_Bus. The CPU 121 performs control of the plurality of peripheral devices Periph_Cir 130 and 140, other arithmetic processing, and the like using the supplied digital signal.

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and can be made by those skilled in the art within the scope of the invention of the claims of the claims of the present application. It goes without saying that various modifications, corrections, and combinations are included.

  For example, the DAC 10 shown in FIG. 2 includes a plurality of unit capacitive elements Cu having the same capacitance value, but is not necessarily limited thereto. The DAC 10 may include a capacitive element weighted to a power of 2, for example. Even in this case, the reference voltage generation circuit 50 may include first and second capacitive elements having a capacitance value that is half the total capacitance value of all the capacitive elements in the DAC 10. Even if it is the said structure, there can exist the effect (improvement of A / D conversion precision) mentioned above.

  In FIG. 2, noise can be reduced most when the capacitance value of the first capacitor element in the reference voltage generation circuit 50 is equal to the capacitance value of the second capacitor element. However, from the viewpoint of reducing noise as compared with the configuration illustrated in FIG. 2, the capacitance value of the first capacitor element and the capacitance value of the second capacitor element may not be exactly the same. For example, even when the ratio between the capacitance value of the first capacitor element and the capacitance value of the second capacitor element is 6: 4, noise can be reduced compared to a general configuration.

1 successive approximation A / D converter 10 DAC
20 Preamplifier 30 Comparator 40 SAR Logic Unit 50 Reference Voltage Generation Circuit 51 Cell Group 52 Cell Group 60 Sample & Hold Circuit SW3 to SW5 Switch SW6-1, 6-2 Switch AVRTC Hi Side Reference Voltage AVRBC Lo Side Reference Voltage 100 Semiconductor Device 110 Analog core 111 MPX
112 A / D conversion unit 113 Data register 120 Analog core unit 121 CPU
122 BSC
123 ROM
124 RAM
125 NV Flash
130 Perich Cir
140 Perich Cir

Claims (14)

A successive approximation A / D converter that performs analog signal sampling processing and successive approximation processing to convert an analog signal into a digital signal,
Having a plurality of capacitive elements, one end of each of the plurality of capacitive elements is connected to a high-side reference voltage or a low-side reference voltage based on the successive approximation process, and a comparison voltage used for the next successive comparison process is generated. A D / A converter to
A first capacitor element that is a single capacitor element having one end connected to the high-side reference voltage; and a second capacitor element that is a single capacitor element having one end connected to the low-side reference voltage; A reference voltage generation unit configured to connect the other end of the first capacitive element and the other end of the second capacitive element in parallel to output a reference voltage used for the successive approximation process;
An A / D converter.   The total value of the capacitance value of the first capacitance element and the capacitance value of the second capacitance element is substantially equal to the total value of the capacitance values of the plurality of capacitance elements in the D / A converter. A / D converter of description.   2. The A / D converter according to claim 1, wherein a capacitance value of the first capacitance element and a capacitance value of the second capacitance element are substantially equal. The D / A converter is
A plurality of first switches connected to a high-side reference voltage or a low-side reference voltage during the successive approximation process;
A plurality of second switches provided between each of the plurality of first switches and each of the corresponding plurality of capacitance elements, and turned on during the successive approximation process and turned off during the sampling process;
A plurality of third switches provided between the input of the analog signal and the plurality of capacitive elements, turned on during the sampling process, and turned off during the successive comparison process;
The reference voltage generator is
A fourth switch, one end of which is connected to the first capacitive element, turned off during the successive approximation process, and turned on during the sampling process;
A fifth switch, one end of which is connected to the second capacitive element, turned off during the successive approximation process, and turned on during the sampling process;
A sixth switch, one end of which is connected to the first capacitive element, turned on during the successive approximation process, and turned off during the sampling process;
A seventh switch, one end of which is connected to the second capacitive element, turned on during the successive approximation process, and turned off during the sampling process;
An eighth switch connected to the other end of the sixth switch and connected to the high-side reference voltage during the successive approximation process;
The A / D converter according to claim 1, further comprising: a ninth switch connected to the other end of the seventh switch and connected to the low-side reference voltage during the successive approximation process.   5. The A / D converter according to claim 4, wherein the eighth switch and the ninth switch have a gate width that is approximately half of a total gate width of the plurality of first switches.   5. The A / D converter according to claim 4, wherein the sixth switch and the seventh switch have a gate width that is approximately half of a total gate width of the plurality of second switches.   5. The A / D converter according to claim 4, wherein the fourth switch and the fifth switch have a gate width that is approximately half of a total gate width of the plurality of third switches. An A / D converter according to any one of claims 1 to 8,
A data processing apparatus comprising: an arithmetic unit that performs an operation using a digital signal output from the A / D converter. A semiconductor device including a successive approximation A / D converter that performs analog signal sampling processing and successive approximation processing to convert an analog signal into a digital signal,
The successive approximation A / D converter is
Having a plurality of capacitive elements, one end of each of the plurality of capacitive elements is connected to a high-side reference voltage or a low-side reference voltage based on the successive approximation process, and a comparison voltage used for the next successive comparison process is generated. A D / A converter to
A first capacitor element that is a single capacitor element having one end connected to the high-side reference voltage; and a second capacitor element that is a single capacitor element having one end connected to the low-side reference voltage; A semiconductor device comprising: a reference voltage generator configured to connect the other end of the first capacitor element and the other end of the second capacitor element in parallel to output a reference voltage used for the successive approximation process.   The semiconductor device has a layout in which the plurality of capacitive elements in the D / A converter are arranged and arranged, and the first capacitive element and the second capacitive element in the reference voltage generation unit are arranged. The semiconductor device according to claim 9.   The semiconductor device according to claim 10, wherein in the layout, the plurality of capacitive elements in the D / A converter are arranged in a plurality of columns or rows. The D / A converter is
A plurality of first switches connected to a high-side reference voltage or a low-side reference voltage during the successive approximation process;
A plurality of second switches provided between each of the plurality of first switches and each of the corresponding plurality of capacitance elements, and turned on during the successive approximation process and turned off during the sampling process;
A plurality of third switches provided between the input of the analog signal and the plurality of capacitive elements, turned on during the sampling process, and turned off during the successive comparison process;
The reference voltage generator is
A fourth switch, one end of which is connected to the first capacitive element, turned off during the successive approximation process, and turned on during the sampling process;
A fifth switch, one end of which is connected to the second capacitive element, turned off during the successive approximation process, and turned on during the sampling process;
A sixth switch, one end of which is connected to the first capacitive element, turned on during the successive approximation process, and turned off during the sampling process;
12. The semiconductor device according to claim 11, further comprising: a seventh switch, one end of which is connected to the second capacitive element, and is turned on during the successive approximation process and turned off during the sampling process. The semiconductor device includes:
The plurality of capacitive elements in the D / A converter and the plurality of first to third switches are aligned, and the first capacitive element, the second capacitive element, the first capacitive element in the reference voltage generation unit are arranged. The semiconductor device according to claim 12, wherein the semiconductor device has a layout in which fourth to seventh switches are arranged. In the layout, the plurality of capacitor elements are arranged in a plurality of columns or rows, the plurality of first to third switches are arranged in a plurality of columns or rows, and the first capacitor element and the second capacitor element are The semiconductor device according to claim 13, wherein the semiconductor devices are arranged in one column or one row.

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