WO2011048725A1

WO2011048725A1 - Solid state image capture device, a/d conversion method, and a/d conversion device

Info

Publication number: WO2011048725A1
Application number: PCT/JP2010/004199
Authority: WO
Inventors: 石井基範; 春日繁孝; 加藤剛久; 鵜川三蔵; 岡田雄介
Original assignee: パナソニック株式会社
Priority date: 2009-10-21
Filing date: 2010-06-24
Publication date: 2011-04-28
Also published as: JP2011091573A

Abstract

Disclosed is a solid state image capture unit (100), comprising a first A/D conversion unit (121), which converts a differential voltage (V0) to a first digital signal (130) of M bits and generates a residual voltage (131) that signifies the difference between the differential voltage (V0) and the analog voltage corresponding to the first digital signal (130), and a second A/D conversion unit (122) that converts the residual voltage (131) to a second digital signal of N bits. The first A/D conversion unit (121) further comprises residual voltage generating units (160A and 160B) that generate 2^M output voltages (Vout) that signify the difference between the differential voltage (V0) and each of 2^M threshold voltages, a comparison unit (161) and a decoder/selection circuit (156), which employ the 2^M output voltages (Vout) to generate the first digital signal (130), and a selection unit (152) that outputs the output voltages (Vout) that correspond to the first digital signal (130) as the residual voltage (131).

Description

Solid-state imaging device, AD conversion method, and AD converter

The present invention relates to a solid-state imaging device, an AD conversion method, and an AD converter, and more particularly, to a solid-state imaging device including an AD conversion unit.

In recent years, it has become common sense to use a solid-state imaging device for electronically capturing and recording images. Solid-state imaging devices are generally called image sensors, CCD (Charge Coupled Device) type sensors (or simply called CCDs), MOS (Metal Oxide Semiconductor) sensors, and CMOS (Complementary Metal Oxide Sensors). Are simply referred to as CMOS sensors).

In these solid-state imaging devices, a large number of minute portions (which are called pixels) that output electrical signals corresponding to the intensity of incident light are two-dimensionally arranged. In addition, the solid-state imaging device determines the order of the signals by scanning the signals output from these pixels in each row and each column, and serially outputs the signals in the determined order to the outside of the solid-state imaging device. It has means to transfer.

The signal directly output from the pixel is naturally an analog signal. However, an imaging device such as a digital still camera to which a solid-state imaging device is applied is required to output an image signal as digital data. Therefore, such an imaging apparatus needs to convert an analog signal into a digital signal (AD conversion).

In conventional imaging devices, the solid-state imaging device often outputs an analog signal to the outside, and the analog signal is AD converted by an external circuit in many cases. In this case, there is a problem that noise is superimposed on the analog signal outside, or the analog signal changes depending on the method of coupling the solid-state imaging device and the external device. Therefore, recently, it has begun to incorporate an AD converter in a solid-state imaging device and output a digital signal to the outside.

It is generally difficult for a CCD to incorporate an AD converter in a solid-state imaging device. There are two reasons for this.

First, in order to manufacture an AD converter, a circuit of a certain scale is required, so in reality, a CMOS using a certain amount of fine wiring rules is essential. However, a CCD is generally manufactured using a special process that is not a CMOS process. Therefore, it is difficult to mount an AD converter on the CCD.

Another reason is that an analog-to-digital signal (charge corresponding to light intensity) from a pixel is sequentially transferred to the output amplifier in a bucket relay manner in the CCD, so the AD converter must be placed behind the output amplifier. Therefore, the AD converter needs to perform AD conversion processing at high speed according to the transfer rate of the signal from each pixel. However, since it is difficult to realize such high-speed AD conversion processing, it is difficult to mount an AD converter on the CCD.

On the other hand, since a CMOS process is used in the CMOS sensor, it is possible to produce a circuit of a certain scale without any problem. Further, in the CMOS sensor, the signal output path is not fixed as in the bucket relay in the CCD, and therefore the AD converter may be arranged in any path from the pixel to the output terminal. Therefore, in reality, an A / D converter is not built in a CCD, and only a CMOS sensor is built in.

An example of a solid-state imaging device incorporating such an AD converter is disclosed in Patent Document 1. FIG. 14 is a diagram illustrating a configuration of a solid-state imaging device 500 described in Patent Document 1.

As shown in FIG. 14, the solid-state imaging device 500 described in Patent Document 1 includes pixels 501 arranged in a two-dimensional manner, and AD converters 502 arranged corresponding to the columns (in this document, “column AD circuit”). ). Each AD converter 502 includes a comparator 503.

The signal from the pixels 501 in each column is input to one input terminal of the comparator 503, and the ramp voltage RAMP (voltage that changes at a constant speed with time) is input to the other input terminal of the comparator 503. Then, the ramp voltage RAMP input to the comparator 503 is changed by a DA converter 504 (DAC) in a minute step shape every clock, and whether or not this voltage matches the voltage from the pixel 501 is determined by the comparator 503. By determining, the AD converter 502 can obtain a digital value.

In the case of a CMOS sensor, noise generated due to variations in threshold voltage (generally referred to as Vt) of a source follower transistor provided independently for each pixel is superimposed on the signal voltage. Therefore, the CMOS sensor needs a noise canceling function for reducing this noise. In order to realize this function, it is generally performed to subtract an output voltage (hereinafter simply referred to as a reset voltage) from a pixel when the pixel is reset from a signal voltage from the pixel. The AD converter 502 implements a noise canceling function by down-counting by the count number proportional to the reset voltage and then counting up by the count number proportional to the signal voltage.

However, although the method of Patent Document 1 can perform AD conversion with high linearity, it takes time by the number of clocks corresponding to the resolution of the AD converter 502. For example, when 10-bit AD conversion processing is desired, there are 1024 possible digital values. Accordingly, the lamp voltage RAMP needs to be changed 1024 times (or the lamp voltage is continuously changed for a time of 1024 clocks or more) accordingly, and 1024 clocks are required for AD conversion processing. In practice, more time is required for noise cancellation.

As described above, the method of Patent Document 1 has a problem that it takes time to perform AD conversion processing.

A technique for solving this problem is disclosed in Patent Document 2. FIG. 15 is a diagram illustrating a configuration of a solid-state imaging device 600 described in Patent Document 2.

The AD converter 502 in Patent Document 1 has only one stage. However, in the solid-state imaging device 600 shown in FIG. 15, the AD converter includes an AD converter 601 that converts the upper N bits and an AD converter that converts the lower M bits. It is divided into two stages with the container 602. This solid-state imaging device 600 converts the upper N bits, and then converts the difference (analog residual) between the analog value corresponding to the upper N bit value and the analog value of the differential voltage into the lower M bits. To perform the entire AD conversion.

For example, when N = 3 and M = 7, since the lower M bits have only 128 values, AD conversion processing is completed in 128 clocks. Therefore, the solid-state imaging device 600 described in Patent Document 2 can improve the speed of AD conversion processing while ensuring the accuracy of 3 + 7 = 10 bits as a whole.

FIG. 16 is a diagram illustrating a specific circuit configuration of the upper N-bit AD converter 601. This is the case when N = 2. First, the AD converter 601 performs AD conversion by a 2-bit ADC 603 and outputs a 2-bit digital value, and a logic circuit (not described in Patent Document 2, but generally uses a logic circuit). To generate control signals φA to φD to control the switches. Thereafter, the AD converter 601 obtains an analog residual output by controlling φ1 to φ4.

On the other hand, Patent Document 3 discloses a technique for reducing the area of the AD converter.

FIG. 17 is a diagram illustrating a configuration of a solid-state imaging device 700 described in Patent Document 3. The solid-state imaging device 700 reduces the total area of the plurality of AD converters 701 by arranging one AD converter 701 (one AD converter 701 in two columns in FIG. 17) common to the plurality of columns. be able to.

JP 2005-323331 A Japanese Patent No. 4069203 US Patent Application Publication No. 2008/0019208

However, although the speed of AD conversion processing can be realized by the technique described in Patent Document 2, further speedup of AD conversion processing is desired.

Therefore, an object of the present invention is to provide a solid-state imaging device, an AD conversion method, and an AD converter that can further speed up AD conversion processing.

In order to achieve the above object, a solid-state imaging device according to an aspect of the present invention is arranged in a matrix and outputs a reset voltage and a signal voltage corresponding to the amount of incident light, and the signal AD that converts the voltage into an M + N-bit third digital signal including a first digital signal of M (M is an integer of 1 or more) bits and a second digital signal of N (N is an integer of 1 or more) bits. A conversion circuit, wherein the AD conversion circuit calculates a differential voltage indicating a difference between the reset voltage and the signal voltage, AD-converts the calculated differential voltage into the first digital signal, and the differential voltage And a first AD converter for performing a first AD conversion process for generating a first residual voltage indicating a difference between the analog voltage corresponding to the digital value of the first digital signal, and the first residual voltage as the second digital signal. Signal And a second 2AD conversion unit that performs first 2AD conversion process D conversion, the first 1AD conversion unit is configured to calculate the difference voltage indicates a difference between each of the difference voltage and the 2 ^M-number of threshold voltage, a residual voltage generator for generating a 2 ^M-number of the second residue voltage corresponding to each of the 2 ^M pieces of digital values represented by M bits, a and each of the 2 ^M-number of the second residue voltage A first comparison unit that generates a 2 ^M- bit first comparison result signal by comparing with one reference voltage; and converts the 2 ^M- bit first comparison result signal into the M-bit first digital signal. A decoder and a second residual voltage corresponding to a digital value of the first digital signal converted by the decoder are selected from the 2 ^M second residual voltages, and the selected second residual voltage is selected. And a selection unit that outputs the first residual voltage.

According to this configuration, in the solid-state imaging device according to an aspect of the present invention, the residual voltage generator generates 2 ^M second residual voltages, and N bits are generated using the generated second residual voltages. AD conversion processing is performed. Accordingly, for example, after performing N-bit AD conversion processing, the first digital signal generated by the AD conversion processing is DA-converted, and the residual voltage is calculated using the DA-converted analog signal. In comparison, the solid-state imaging device according to an aspect of the present invention can generate the first residual voltage at high speed. Therefore, the solid-state imaging device according to one embodiment of the present invention can speed up AD conversion processing.

The second AD conversion unit includes a plurality of second column AD conversion units, one for each column, and one first AD conversion unit is provided for each Q column and arranged in the corresponding Q column. A plurality of first column AD conversion units that perform the first AD conversion processing on the reset voltage and the signal voltage output by the plurality of pixels, and each of the first column AD conversion units includes Q columns A first selection circuit that selects one of the columns and outputs the reset voltage and the differential voltage output by the pixels arranged in the selected column; the reset voltage output by the first selection circuit; and A first AD converter that performs the first AD conversion processing on the signal voltage, and one of the Q columns are selected, and the first residual voltage generated by the first AD converter is selected in the selected column. Output to the second row AD converter provided Each of the second column AD conversion units is configured to perform the second AD conversion process on the first residual voltage output by the second selection circuit provided in the corresponding Q column. May be performed.

According to this configuration, since it is only necessary to provide one first AD converter in the Q column, the solid-state imaging device according to one embodiment of the present invention can reduce the circuit area of the AD conversion circuit.

Further, the solid-state imaging device further causes the first column AD conversion unit to select each column of the Q columns by causing the first selection circuit and the second selection circuit to sequentially select the columns of the Q column. A first control unit configured to sequentially generate the corresponding first residual voltage and the first digital signal, wherein the first control unit includes a first column included in the Q column in the first column AD conversion unit; At the same time as generating the corresponding first residual voltage, the first column AD conversion unit is included in the second column AD conversion unit provided in the second column different from the first column included in the Q column. The second AD conversion process may be performed on the first residual voltage of the corresponding column already generated by

According to this configuration, the solid-state imaging device according to an aspect of the present invention can speed up the AD conversion process by simultaneously performing the first AD conversion process and the second AD conversion process.

In addition, the solid-state imaging device further includes a column scanning circuit that sequentially transfers the third digital signal AD-converted by the AD conversion circuit to the outside, and the first control unit further includes the first column. The AD conversion unit sequentially generates the first residual voltage and the first digital signal corresponding to the first column group included in the Q column, and the second column AD conversion provided in the first column group The second digital signal is sequentially generated by causing the unit to perform the second AD conversion processing on the first residual voltage corresponding to the first column group, and the first column AD conversion unit The first residual voltage and the first digital signal corresponding to a second column group different from the first column group included in the Q column are sequentially generated, and the second provided in the second column group Corresponds to the second column group in the column AD converter The second AD conversion processing may be performed on the first residual voltage, and the third digital signal corresponding to the first column group may be sequentially transferred to the outside simultaneously with the column scanning circuit. .

According to this configuration, the solid-state imaging device according to an aspect of the present invention performs the AD conversion process and the third digital signal transfer process at the same time until the third digital signal is output from the imaging operation to the outside. The processing speed can be improved.

Further, the solid-state imaging device further causes the first column AD conversion unit to select each column of the Q columns by causing the first selection circuit and the second selection circuit to sequentially select the columns of the Q column. A first control unit configured to sequentially generate the corresponding first residual voltage and the first digital signal, wherein the first control unit includes the first column AD conversion unit in all columns included in the Q column; After generating the corresponding first residual voltage, the second column AD conversion unit may simultaneously perform the second AD conversion processing on the first residual voltage corresponding to all the columns.

According to this configuration, the solid-state imaging device according to an aspect of the present invention can use the same lamp voltage in all the second column AD conversion circuits, and thus the circuit scale can be reduced.

The first AD converter is provided for each column, and performs a plurality of first AD conversion processes on the reset voltage and the signal voltage output by the pixels arranged in the corresponding column. 1st column AD conversion part is provided, and the 2nd AD conversion part is provided for every column, and with respect to the 1st residual voltage generated by the 1st column AD conversion part provided in the corresponding column A plurality of second column AD conversion units that perform the second AD conversion processing may be provided.

According to this configuration, the solid-state imaging device according to one aspect of the present invention can simultaneously perform the first AD conversion processing on each column, and therefore can speed up the first AD conversion processing.

The second AD conversion unit compares the ramp voltage and the first residual voltage with a reference signal generation unit that generates a ramp voltage whose voltage value changes with time from a first time, and compares A second comparison unit that generates a second comparison result signal indicating a result; a first holding unit that holds, as the second digital signal, a time from the first time until the logic of the second comparison result signal is inverted; May be provided.

According to this configuration, the solid-state imaging device according to an aspect of the present invention can ensure linearity with respect to, for example, AD conversion processing of lower N bits that requires accuracy.

The residual voltage generation unit includes a first residual voltage generation unit that generates one of the 2 ^M second residual voltages, and (2 ^M −1) second residuals. The first residual voltage generator includes a first terminal to which the second residual voltage generated by the first residual voltage generator is output, and one end connected to the first terminal. A first capacitor connected to the first capacitor, a first switch that switches between a closed state in which the reset voltage is supplied to the first terminal and an open state in which the reset voltage is not supplied, and one of the signal voltage and the first reference voltage is selected A second switch for supplying the selected voltage to the other end of the first capacitor, and each of the second residual voltage generators generates the second residual generated by the second residual voltage generator. A second terminal for outputting a voltage; a second capacitor and a third capacitor having one end connected to the second terminal; and the signal A third switch that selects one of the voltage, the first reference voltage, and the second reference voltage, and supplies the selected voltage to the other end of the second capacitor; and the signal voltage and the second reference voltage A fourth switch that selects one and supplies the selected voltage to the other end of the third capacitor; a fifth switch that switches between a closed state in which the reset voltage is supplied to the second terminal and an open state in which the reset voltage is not supplied; May be provided.

According to this configuration, the solid-state imaging device according to an aspect of the present invention uses, for example, a method that is inferior in linearity but high in speed for AD conversion processing of upper M bits that do not require high accuracy. Higher speed can be realized while suppressing a decrease in accuracy of the entire AD conversion process.

The solid-state imaging device further includes a second control unit that controls the first switch, the second switch, the third switch, the fourth switch, and the fifth switch, and the second control unit includes: In the first period, the first switch and the fifth switch are closed, the second switch, the third switch, and the fourth switch select the signal voltage, and the second switch after the first period is selected. In two periods, the first switch and the fifth switch are opened, the second switch selects the first reference voltage, and the third switch and the fourth switch select the second reference voltage. In a third period after the second period, the first switch and the fifth switch are opened, and the first reference voltage is selected by the second switch and the third switch. , May be selecting the second reference voltage to the fourth switch.

The residual voltage generation unit includes a first residual voltage generation unit that generates one of the 2 ^M second residual voltages, and (2 ^M −1) second residuals. The first residual voltage generator includes a first terminal from which the second residual voltage generated by the first residual voltage generator is output, a first node, A first capacitor having one end connected to the first node; a first switch that switches between a closed state in which the reset voltage is supplied to the first node and an open state in which the reset voltage is not supplied; and the signal voltage and the first reference voltage A second switch that supplies the selected voltage to the other end of the first capacitor, an inverting input terminal is connected to the first node, the reset voltage is applied to a non-inverting input terminal, and an output A first operational amplifier having a terminal connected to the first terminal, and the first operational amplifier A fourth capacitor and a sixth switch connected in parallel with each other are provided between the inverting input terminal and the output terminal, and each of the second residual voltage generators is generated by the second residual voltage generator. A second terminal from which the second residual voltage is output, a second node, a second capacitor and a third capacitor having one end connected to the second node, the signal voltage, and the first reference voltage, One of the second reference voltages is selected, a third switch for supplying the selected voltage to the other end of the second capacitor, one of the signal voltage and the second reference voltage is selected, and the selected voltage Is supplied to the other end of the third capacitor, a fifth switch for switching between a closed state for supplying the reset voltage to the second node and an open state for not supplying the second node, and an inverting input terminal for the second switch The reset voltage is applied to the non-inverting input terminal. A second operational amplifier having an output terminal connected to the second terminal, and a fifth capacitor and a seventh switch connected in parallel with each other between the non-inverting input terminal and the output terminal of the second operational amplifier. You may prepare.

The solid-state imaging device further includes a second control for controlling the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch. And the second control unit closes the first switch, the fifth switch, the sixth switch, and the seventh switch in the first period, and sets the second switch and the third switch to the closed state. Selecting the first reference voltage, causing the fourth switch to select the second reference voltage, and in a second period after the first period, the first switch, the fifth switch, the sixth switch, and Opening the seventh switch, causing the second switch to select the signal voltage, causing the third switch and the fourth switch to select the second reference voltage, and the second period. In the subsequent third period, the first switch, the fifth switch, the sixth switch, and the seventh switch are opened, and the signal voltage is applied to the second switch, the third switch, and the fourth switch. It may be selected.

In the AD converter according to one embodiment of the present invention, the signal voltage includes a first digital signal having M (M is an integer of 1 or more) bits and a second digital signal having N (N is an integer of 1 or more) bits. AD converter for AD conversion into an M + N-bit third digital signal including A, and AD converting the signal voltage into the first digital signal and corresponding to the signal voltage and the digital value of the first digital signal A first AD conversion unit that performs a first AD conversion process that generates a first residual voltage that indicates a difference from the analog voltage to be converted, and a second AD conversion process that performs an AD conversion of the first residual voltage into the second digital signal A second AD converter, wherein the first AD converter calculates the differential voltage and indicates a difference between the differential voltage and each of the 2 ^M threshold voltages, and is represented by 2 ^M represented by M bits. Each of the digital values of By comparing each of the 2 ^M second residual voltages with the first reference voltage, 2 ^M bits by generating a corresponding 2 ^M second residual voltage, respectively. A first comparison unit that generates the first comparison result signal, a decoder that converts the 2 ^M- bit first comparison result signal into the M-bit first digital signal, and the 2 ^M second residual voltages. A selection unit that selects a second residual voltage corresponding to a digital value of the first digital signal converted by the decoder and outputs the selected second residual voltage as the first residual voltage. Prepare.

According to this configuration, in the AD converter according to an aspect of the present invention, the residual voltage generator generates 2 ^M second residual voltages, and N bits are generated using the generated second residual voltages. AD conversion processing is performed. Accordingly, for example, after performing N-bit AD conversion processing, the first digital signal generated by the AD conversion processing is DA-converted, and the residual voltage is calculated using the DA-converted analog signal. As compared with the above, the AD converter according to an aspect of the present invention can generate the first residual voltage at high speed. Thus, the AD converter according to one embodiment of the present invention can speed up AD conversion processing.

Note that the present invention can be realized not only as such a solid-state imaging device but also as a solid-state imaging device control method and a solid-state imaging device driving method in which some or all of characteristic means included in the solid-state imaging device are steps. Alternatively, it can be realized as an AD conversion method in a solid-state imaging device, or as a program for causing a computer to execute some or all of such characteristic steps. Needless to say, such a program can be distributed via a recording medium such as a CD-ROM and a transmission medium such as the Internet.

Furthermore, the present invention can be realized as a semiconductor integrated circuit (LSI) that realizes part or all of the functions of such a solid-state imaging device, or a digital still camera or digital video camera equipped with such a solid-state imaging device. It can be realized as a camera, can be realized as an AD converter included in such a solid-state imaging device, or can be realized as an AD conversion method using characteristic means included in such an AD converter as steps.

As described above, the present invention can provide a solid-state imaging device, an AD conversion method, and an AD converter that can further speed up AD conversion processing.

FIG. 1 is a diagram showing a configuration of a solid-state imaging apparatus according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing a configuration of the pixel according to Embodiment 1 of the present invention. FIG. 3 is a diagram showing AD conversion processing of upper bits according to Embodiment 1 of the present invention. FIG. 4 is a diagram showing a configuration of the first AD converter according to Embodiment 1 of the present invention. FIG. 5 is a circuit diagram of the first AD converter according to Embodiment 1 of the present invention. FIG. 6 is a timing chart of the first AD converter according to Embodiment 1 of the present invention. FIG. 7 is a circuit diagram of the comparator according to Embodiment 1 of the present invention. FIG. 8 is a timing chart of AD conversion processing by the solid-state imaging device according to Embodiment 1 of the present invention. FIG. 9 is a diagram showing a configuration of the solid-state imaging apparatus according to Embodiment 2 of the present invention. FIG. 10 is a timing chart of AD conversion processing by the solid-state imaging device according to Embodiment 2 of the present invention. FIG. 11 is a circuit diagram of the first AD converter according to Embodiment 3 of the present invention. FIG. 12 is a timing chart of the first AD converter according to Embodiment 3 of the present invention. FIG. 13 is a timing chart of AD conversion processing by the solid-state imaging device according to Embodiment 4 of the present invention. FIG. 14 is a diagram illustrating a configuration of a conventional solid-state imaging device. FIG. 15 is a diagram illustrating a configuration of a conventional solid-state imaging device. FIG. 16 is a diagram showing a configuration of a conventional AD converter. FIG. 17 is a diagram illustrating a configuration of a conventional solid-state imaging device.

Embodiments according to the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals denote the same components.

(Embodiment 1)
The solid-state imaging device 100 according to Embodiment 1 of the present invention generates 2 ^M output voltages Vout indicating the difference between the differential voltage V0 and each of the 2 ^M threshold voltages, and generates the generated 2 ^M outputs. The first M-bit first digital signal 130 is generated using the voltage Vout. Thereby, since the solid-state imaging device 100 according to Embodiment 1 of the present invention can generate the first residual voltage at high speed, the AD conversion processing can be speeded up.

First, the configuration of the solid-state imaging device 100 according to Embodiment 1 of the present invention will be described.

FIG. 1 is a diagram showing a configuration of a solid-state imaging device 100 according to Embodiment 1 of the present invention.

1 includes an imaging unit 101, an AD conversion circuit 120, a row scanning circuit 103, a column scanning circuit 109, and a timing control unit 112. The solid-state imaging device 100 illustrated in FIG.

The imaging unit 101 includes pixels 102 (pixel circuits) arranged in a two-dimensional matrix and a plurality of vertical signal lines 104.

Each vertical signal line 104 is arranged along the vertical direction for each column.

A signal line from the row scanning circuit 103 and a vertical signal line 104 are connected to each pixel 102.

Each pixel 102 photoelectrically converts incident light into an analog signal voltage (pixel signal). Each pixel 102 outputs a reset voltage Vres to the corresponding vertical signal line 104 in the reset state, and outputs a signal voltage Vsig corresponding to the amount of incident light in the data output state.

The row scanning circuit 103 selects each row of the imaging unit 101 in order. Each pixel 102 in the selected row performs an imaging operation within a certain time (this is called a horizontal blanking period), and sequentially outputs the obtained reset voltage Vres and signal voltage Vsig to the vertical signal line 104. To do.

Next, the configuration of the pixel 102 will be described. FIG. 2 is a circuit diagram of the pixel 102.

As shown in FIG. 2, the pixel 102 includes a reset transistor 201, a photodiode (PD) 202, a transfer transistor 203, a floating diffusion (FD) 204, an amplification transistor 205, and a pixel selection transistor 206.

The reset transistor 201 is connected between the FD 204 and the power supply line VDD. The gate terminal of the reset transistor 201 is connected to the reset signal line RSCELL.

PD 202 generates a signal charge corresponding to the intensity of received light and accumulates the signal charge.

The transfer transistor 203 is connected between the PD 202 and the FD 204. The gate terminal of the transfer transistor 203 is connected to the transfer signal line TRANS.

FD 204 accumulates signal charges transferred from PD 202. The FD 204 is connected to the gate terminal of the amplification transistor 205.

The amplification transistor 205 is connected between the vertical signal line 104 and the power supply line VDD.

The pixel selection transistor 206 is connected in series with the amplification transistor 205 between the vertical signal line 104 and the power supply line VDD. The gate terminal of the pixel selection transistor 206 is connected to the selection signal line SELECT.

With the above configuration, the pixel 102 outputs a signal corresponding to the potential of the FD 204 to the vertical signal line 104 when the pixel selection transistor 206 is selected (on state). Specifically, the pixel 102 outputs the reset voltage Vres to the vertical signal line 104 in a state where the reset transistor 201 is turned on. Further, the pixel 102 outputs the signal voltage Vsig to the vertical signal line 104 in a state where the signal charges accumulated in the PD 202 are transferred to the FD 204 via the transfer transistor 203.

The amplification transistor 205 forms a source follower circuit together with a load transistor (not shown) connected to the vertical signal line 104.

Referring back to FIG.

The AD conversion circuit 120 converts the signal voltage Vsig output from the plurality of pixels 102 into a first digital signal 130 of M (M is an integer of 1 or more) bits and a second of N (N is an integer of 1 or more) bits. AD conversion to a third digital signal of M + N bits including the digital signal. For example, the first digital signal 130 corresponds to the upper M-bit digital signal included in the M + N-bit third digital signal, and the second digital signal is the lower N-bit digital signal included in the M + N-bit third digital signal. Corresponds to the signal.

The AD conversion circuit 120 includes a first AD conversion unit 121 and a second AD conversion unit 122.

The first AD converter 121 calculates a differential voltage V0 indicating a difference between the reset voltage Vres and the signal voltage Vsig, and AD converts the calculated differential voltage V0 into an M-bit first digital signal 130. The first AD converter 121 holds the generated M-bit first digital signal 130.

Also, the first AD converter 121 generates a residual voltage 131 indicating a difference between the differential voltage V0 and an analog voltage corresponding to the digital value of the M-bit first digital signal 130. Here, the residual voltage 131 corresponds to the first residual voltage of the present invention, and corresponds to the analog voltage value for the lower N bits of the M + N-bit third digital signal.

In the following, the first AD converter 121 calculates the differential voltage V0, AD converts the calculated differential voltage V0 into the M-bit first digital signal 130, and generates the residual voltage 131. This is referred to as conversion processing.

The first AD converter 121 includes a reference voltage generator 107 and a plurality of first column AD converters 123, one for each column.

The reference voltage generator 107 generates a first reference voltage VH and a second reference voltage VL. The first reference voltage VH corresponds to the upper limit value of the differential voltage V0, and the second reference voltage VL corresponds to the lower limit value of the differential voltage V0.

Each first column AD conversion unit 123 performs a first AD conversion process on the reset voltage Vres and the signal voltage Vsig generated by the pixels 102 arranged in the corresponding column, thereby performing the first AD conversion processing corresponding to each column. 1 digital signal 130 and residual voltage 131 are generated.

Each first column AD conversion unit 123 includes a reset voltage holding unit 105, a first AD converter 106, and a first storage unit 108.

The reset voltage holding unit 105 is connected to the vertical signal line 104 in the corresponding column, and holds the reset voltage Vres output by the pixel 102 in the corresponding column. Note that the reset voltage holding unit 105 may hold the reset voltage Vres output from the pixel 102, or may hold a voltage obtained by adding a certain offset value to the reset voltage Vres. Further, the reset voltage holding unit 105 may add a certain offset value to the held reset voltage Vres and output the result.

In the first AD converter 106, the reset voltage Vres held by the reset voltage holding unit 105, the signal voltage Vsig from the vertical signal line 104, the first reference voltage VH generated by the reference voltage generation unit 107, and the second voltage A reference voltage VL is input.

The first AD converter 106 performs a first AD conversion process on the reset voltage Vres held in the reset voltage holding unit 105 and the signal voltage Vsig of the vertical signal line 104.

Also, the first AD converter 106 performs upper M-bit AD conversion processing on the voltage value of the signal voltage Vsig that is equal to or higher than the second reference voltage VL and equal to or lower than the first reference voltage VH.

The first storage unit 108 holds the first digital signal 130 generated by the first AD converter 106.

Also, the first AD converter 106 outputs the residual voltage 131 to the second AD converter 122.

The second AD converter 122 performs a second AD conversion process in which the residual voltage 131 generated by the first AD converter 121 is AD converted into an N-bit second digital signal.

The second AD converter 122 includes a reference signal generator 113 and a second column AD converter 124 provided for each column.

The reference signal generator 113 generates a ramp voltage RAMP whose voltage value changes with time. Note that the voltage value of the ramp voltage RAMP may change continuously at a constant speed with time, or may change in a minute step shape every clock.

Each second column AD converter 124 AD converts the residual voltage 131 generated by the first column AD converter 123 of the corresponding column into an N-bit second digital signal. Each second column AD conversion unit 124 holds the AD converted second digital signal.

Each second column AD conversion unit 124 includes a comparator 110 and a counter latch unit 111.

The comparator 110 corresponds to the second comparison unit of the present invention, compares the residual voltage 131 generated by the first AD converter 106 with the ramp voltage RAMP generated by the reference signal generation unit 113, and compares the result. A comparison result signal 133 (corresponding to the second comparison result signal of the present invention) is generated. The comparator 110 outputs the generated comparison result signal 133 to the counter latch unit 111.

The counter latch unit 111 corresponds to the first holding unit of the present invention, and latches (holds) the counter value CNT generated by the timing control unit 112 at the timing when the logic of the comparison result signal 133 is inverted. The counter value held by the counter latch unit 111 corresponds to the lower N bits included in the M + N-bit third digital signal generated by the AD conversion circuit 120.

The column scanning circuit 109 sequentially transfers the third digital signal AD-converted by the AD conversion circuit 120 to the outside. That is, the column scanning circuit 109 sequentially outputs the M-bit first digital signals 130 held in the plurality of first storage units 108 and the N-bit second digital signals held in the plurality of counter latch units 111 to the outside. Forward.

The timing control unit 112 corresponds to the first control unit and the second control unit of the present invention, and controls the row scanning circuit 103, the column scanning circuit 109, and the AD conversion circuit 120. Further, the timing control unit 112 counts the counter value CNT.

Hereinafter, the operation of the second column AD conversion unit 124 will be described.

First, the residual voltage 131 is input to one input terminal of the comparator 110. Thereafter, the timing control unit 112 starts to linearly change the ramp voltage RAMP output from the reference signal generation unit 113, and at the same time increases or decreases the counter value CNT by 1 every time one clock time elapses. . Then, the comparator 110 inverts the logic of the comparison result signal 133 when the voltage values of both input terminals match (this actually has a delay time). The counter latch unit 111 stores the counter value CNT at this time. That is, the counter latch unit 111 holds the time from when the change of the ramp voltage RAMP starts until the logic of the comparison result signal 133 is inverted as the second digital signal.

As described above, the AD conversion circuit 120 is configured such that the first column AD conversion unit 123 performs upper M-bit AD conversion and the second column AD conversion unit 124 performs lower N-bit AD conversion, whereby an M + N-bit AD conversion is performed. Conversion is possible. Further, the first column AD conversion unit 123 and the second column AD conversion unit 124 are arranged in each column. Therefore, the AD conversion circuit 120 can simultaneously AD convert the signal voltage Vsig output from all the pixels 102 in the row selected by the row scanning circuit 103.

Actually, it is not possible to obtain an accurate digital value with such an operation, and a calibration process for separately calibrating the digital value is required. This calibration processing may be performed inside the solid-state imaging device 100, or only a digital value necessary for calibration is generated inside the solid-state imaging device 100, and the calibration processing itself may be performed outside the solid-state imaging device 100. Good. In any case, since a digital value is output from the solid-state imaging device 100 to the outside, there is no problem that noise is superimposed on the output path and outside on the signal output by the solid-state imaging device 100.

Next, the first AD converter 106 will be described in detail.

FIG. 3 is a diagram for explaining the upper bit AD conversion operation by the first AD converter 106.

The following operations are required to perform AD conversion of upper bits. First, the first AD converter 106 performs a noise canceling operation by subtracting the signal voltage Vsig from the reset voltage Vres. The differential voltage V0 (= Vres−Vsig) obtained here does not include noise and an offset voltage due to individual variations in the circuit in the pixel 102, and almost depends only on the light intensity incident on the pixel 102.

Here, the first reference voltage VH and the second reference voltage VL generated by the reference voltage generation unit 107 and the voltage value between the first reference voltage VH and the second reference voltage VL are equally divided into 2 ^M ( Consider 2 ^M −1) voltage values (the 2 ^M +1 voltage values will be referred to as threshold voltages). The respective threshold voltages are described as VL, V1, V2,..., V2 ^M −1, VH in FIG. The threshold voltage corresponds to a digital value in which the lower N bits are 0. The threshold voltage Vl is expressed by the following (formula 1). Here, l is an integer of 0 ≦ l ≦ 2 ^M.

The first AD converter 106 compares the magnitude relationship between the respective threshold voltages and the differential voltage V0. Then, the first AD converter 106 outputs the upper M-bit digital value corresponding to the largest threshold voltage not exceeding the differential voltage V 0 as the first digital signal 130.

Furthermore, the first AD converter 106 needs to have a function of calculating and outputting the residual voltage 131 corresponding to the lower bits. The residual voltage 131 is a difference between the differential voltage V0 and the largest threshold voltage that does not exceed the differential voltage V0. This residual voltage 131 corresponds to the analog voltage of the lower N bits.

For example, as shown in FIG. 3, when the differential voltage V0 is Va, the largest threshold voltage that does not exceed the differential voltage Va is the threshold voltage V2 ^M −1, and the residual voltage 131 is Vb.

FIG. 4 is a diagram showing a schematic configuration of the first AD converter 106.

4, the first AD converter 106 includes a calculation unit 151, a selection unit 152, an impedance converter 155, and a decoder / selection circuit 156.

Calculation unit 151, a first calculation unit 153-1, the second calculation unit 153-2, the third calculation unit 153-3, ..., the second ^M computing unit 153-2 ^M in total 2 ^M pieces of computing units 153. Note that these first when calculating unit 153-1 and the second calculation unit 153-2 not particularly distinguished second ^M computing units 153-2 ^M ~ is referred computation unit 153.

The first reference voltage VH and the second reference voltage VL generated by the reference voltage generation unit 107, the signal voltage Vsig, and the reset voltage Vres are input to each calculation unit 153.

Each calculation unit 153 corresponds to 2 ^M threshold voltages of VL, V1, V2,..., V2 ^M −1 excluding VH. Each calculation unit 153 compares the corresponding threshold voltage with the difference voltage V0 and outputs a 1-bit comparison result signal b (b0, b1, b2,..., B2 ^M −1). . Each calculation unit 153 calculates a residual voltage indicating a difference between the differential voltage V0 and a corresponding threshold voltage, and outputs an output voltage Vout (Vout (1) to Vout (2 ^M )) indicating the residual voltage. Is output. This output voltage Vout corresponds to the second residual voltage of the present invention.

The selection unit 152 selects any one of 2 ^M output voltages Vout and outputs the selected output voltage Vout to the impedance converter 155. This selection operation is performed by a selection signal sel described later. The selection unit 152 includes 2 ^M switches 154 each corresponding to each calculation unit 153. Each switch 154 is connected between the output terminal of the corresponding calculation unit 153 (the terminal from which the output voltage Vout is output) and the input terminal of the impedance converter 155.

The impedance converter 155 outputs the output voltage Vout output by the selection unit 152 as a residual voltage 131 with low impedance. The impedance converter 155 may amplify the output voltage Vout.

Decoder selection circuit 156, by decoding the comparison result signal b 2 ^M bits generated by 2 ^M pieces of computing units 153 to generate a first digital signal 130 of upper M bits. Further, the decoder / selection circuit 156 uses the 2 ^M- bit comparison result signal b to close (turn on) the switch 154 corresponding to the calculation unit 153 corresponding to the largest threshold voltage not exceeding the differential voltage V0, In addition, a 2 ^M- bit selection signal sel is generated to open the other switch 154 (off). Each bit of the 2 ^M- bit selection signal sel is input to the control terminal of the corresponding switch 154.

That is, the selection unit 152 selects the output voltage Vout corresponding to the digital value of the first digital signal 130 converted by the decoder / selection circuit 156 from the 2 ^M output voltages Vout, and selects the selected output voltage Vout. The residual voltage 131 is output.

Here, the calculation units 153 are connected in parallel, and the comparison operation and the operation of generating the output voltage Vout are simultaneously executed by all the calculation units 153. Therefore, the speed can be increased as compared with the case where the residual voltage 131 is generated using the results of all the comparison operations. The decoder / selection circuit 156 operates after obtaining the comparison result signal b generated by the calculation unit 153. The decoder / selection circuit 156 can be composed of at most M stages of logic gates. In particular, in the case of a solid-state imaging device, M + N ≦ 14, and M is practically about 5 at most. In this case, since the decoder / selection circuit 156 can be composed of at most five stages of logic gates, it operates at high speed. That is, the first AD converter 106 can complete the AD conversion processing of the upper bits and the output processing of the residual voltage 131 at the same time as the operation of the calculation unit 153 is almost completed, thereby realizing high-speed AD conversion. it can. Further, the first AD converter 106 can realize noise cancellation at the same time.

Hereinafter, the first AD converter 106 will be described in more detail.

FIG. 5 is a diagram showing a detailed configuration of the first AD converter 106.

In the following, description will be made including the capacitance value of the capacitor, but the capacitance value of each capacitor may be different from the following description. However, depending on the capacitance value, there may be a case where a correct AD conversion result cannot be obtained, but if a means for calibrating it is prepared separately, it is possible to correctly perform AD conversion as a result.

As shown in FIG. 5, the first AD converter 106 further includes a switch 157 connected between the input terminal of the impedance converter 155 and the signal line to which the first reference voltage VH is applied.

The configuration of the first calculation unit 153-1 and the other calculation units 153 (from the second calculation unit 153-2 to the second ^M calculation unit 153-2 ^M ) is different. Specifically, the first calculation unit 153-1 includes a residual voltage generation unit 160A and a comparator 161. The second ^M computing unit 153-2 ^M from the second computing unit 153-2 includes a residual voltage generating unit 160B, and a comparator 161.

A total of 2 ^M

residual voltage generators

160A and 160B generate 2 ^M output voltages Vout. Here, 2 ^M output voltages Vout correspond to each of 2 ^M digital values represented by the M-bit first digital signal 130. Vout is expressed by (Expression 2) described later.

The 2 ^M comparators 161 correspond to the first comparison unit of the present invention, and each of the 2 ^M output voltages Vout and the first reference voltage VH are compared, thereby comparing the 2 ^M bit comparison result signal b. Is generated.

The residual voltage generator 160A corresponds to the first residual voltage generator of the present invention, and includes a first switch 164, a second switch 162, and a capacitor 163.

The capacitor 163 corresponds to the first capacitor of the present invention, and one end (right end) is connected to the node 165 and the other end (left end) is connected to the second switch 162. The node 165 corresponds to an output terminal (a first terminal and a second terminal of the present invention) from which the output voltage Vout is output. The node 165 includes a first switch 164, a first input terminal of the comparator 161, and a corresponding switch 154. Connected to.

The second switch 162 selects one of the signal voltage Vsig and the first reference voltage VH, and supplies the selected voltage to the left end of the capacitor 163. Here, when C is an arbitrary positive real number, the capacitance value of the capacitor 163 is 2 ^MC .

The first switch 164 switches between a closed state (ON) in which the reset voltage Vres is supplied to the node 165 and an open state (OFF) in which the reset voltage Vres is not supplied to the node 165.

The residual voltage generator 160B corresponds to a second residual voltage generator of the present invention, and includes a first switch 164 (corresponding to a fifth switch of the present invention), a third switch 166, a fourth switch 168, Capacitors 167 and 169.

The capacitor 167 corresponds to the second capacitor of the present invention, and has one end (right end) connected to the node 165 and the other end (left end) connected to the third switch 166. The capacitor 169 corresponds to the third capacitor of the present invention, and has one end (right end) connected to the node 165 and the other end (left end) connected to the fourth switch 168.

The third switch 166 selects any one of the signal voltage Vsig, the first reference voltage VH, and the second reference voltage VL, and supplies the selected voltage to the left end of the capacitor 167. The fourth switch 168 selects one of the second reference voltage VL and the signal voltage Vsig and supplies the selected voltage to the left end of the capacitor 169.

The capacitance value of the capacitor 167 and 169 included from the second calculation unit 153-2 to the second ^M computing unit 153-2 ^M are different. Specifically, when k is an integer greater than or equal to 2 and less than or equal to 2 ^M , the capacitance value of the capacitor 167 included in the k th calculation unit 153 is (2 ^M −k + 1) C, and the capacitance value of the capacitor 169 is ( k-1) C.

Further, the opening / closing and selection of the first switch 164, the second switch 162, the third switch 166, the fourth switch 168, and the switch 157 are controlled by a control signal generated by the timing control unit 112.

Hereinafter, the operation of the first AD converter 106 will be described. In the following, the case of M = 2, VL = 0V, VH = 1V, Vres = 1.5V, and Vsig = 1.2V will be described as an example, but it goes without saying that the same operation is performed in other cases. FIG. 6 is a timing chart showing the operation of the first AD converter 106. FIG. 6 shows the time in the horizontal direction, and shows how time elapses from left to right. Moreover, the vertical direction of FIG. 6 is a voltage value. In FIG. 6, the output voltages Vout (1) to Vout (4) (voltage of the node 165) of the first calculation unit to the fourth calculation unit and the residual voltage 131 (voltage of the input terminal of the impedance converter 155) are the same. ) And the value at each time. Further, the description here is a case where no offset voltage is applied to the reset voltage Vres. When applying, an offset voltage may be added to the first reference voltage VH applied to the second input terminal of each comparator 161.

First, in the period from time t1 to time t2, the timing control unit 112 closes the first switch 164 and causes the second switch 162, the third switch 166, and the fourth switch 168 to select Vsig. At this time, since the voltages at the right ends (nodes 165) of the

capacitors

163, 167, and 169 are Vres, the output voltages Vout of the respective calculation units 153 are all Vres.

Further, since the voltages at the left ends of the

capacitors

163, 167, and 169 are Vsig, the voltage difference between both ends of the

capacitors

163, 167, and 169 is Vres−Vsig. Actually, when charging / discharging of the

capacitors

163, 167, and 169 is completed and a steady state is reached, the voltage difference between both ends of the

capacitors

163, 167, and 169 becomes the above value.

In the period from time t1 to time t4, the timing control unit 112 turns on the switches 157 and turns off all the switches 154. As a result, the first reference voltage VH is supplied to the input terminal of the impedance converter 155. Therefore, the residual voltage 131 is VH.

Next, in the period from time t2 to time t3, the timing control unit 112 turns off the first switch 164 and causes the second switch 162 to select the first reference voltage VH, and the third switch 166 and the fourth switch 168. To select the second reference voltage VL. At this time, since the voltage source is not connected to the right end (node 165) of the capacitor 163, the voltage difference between both ends of the capacitor 163 before and after the time t2 is constant. Therefore, since the voltage at the left end of the capacitor 163 changes by VH−Vsig due to the switching of the second switch 162, the voltage at the right end (node 165) of the capacitor 163, that is, the output output by the first calculation unit 153-1. The voltage Vout (1) is expressed by the following (formula 2).

Further, no voltage source is connected to the right end of the capacitors 167 and 169 as well. Further, both the leftmost potentials are the second reference voltage VL. That is, the voltage difference between both ends of the capacitor 167 and the capacitor 169 is constant, and the left end voltage is changed by VL−Vsig. Therefore, the right end of the voltage or the second computation unit 153-2 ~ output voltage Vout output by the second ^M computing unit 153-2 ^M of capacitor 167 and capacitor 169 (k) (k is a 2 ≦ k ≦ 2 ^M (Integer) is represented by the following (formula 3).

Next, at time t3, the timing control unit 112 causes the third switch 166 to select the first reference voltage VH. That is, after time t3, the timing controller 112 turns off the first switch 164, causes the second switch 162 and the third switch 166 to select the first reference voltage, and causes the fourth switch 168 to apply the second reference voltage VL. Let them choose.

At this time, since the state of the first calculation unit 153-1 does not change, the output voltage Vout (1) of the first calculation unit 153-1 is expressed by the above (formula 2).

Also, the output voltage Vout (k) of the k-th calculation unit 153-k is as follows.

First, before the time t3, the total charge Q _BC charged in the capacitor 167 and the capacitor 169 is expressed by the following (formula 4).

Further, after time t3, the charge Q _B charged in the capacitor 167 is expressed by the following (formula 5).

Further, after time t3, the charge Q _C charged in the capacitor 169 is expressed by the following (formula 6).

In addition, since no voltage source is connected to Vout (k), the electric charge is stored before and after time t3, so the following relationship (Equation 7) holds.

By eliminating Q _BC , Q _B , and Q _C from (Equation 4) to (Equation 7), the following (Equation 8) is obtained.

Furthermore, if this is rewritten with the definition of Vl in (Expression 1) above, the following (Expression 9) is obtained.

For example, in the example shown in FIG. 6, the output voltage Vout (2) of the second calculation unit 153-2 is Vres−Vsig + V3, and the output voltage Vout (3) of the third calculation unit 153-3 is Vres−Vsig + V2. The output voltage Vout (4) of the fourth calculation unit 153-4 is Vres−Vsig + V1.

Next, in the period from time t3 to time t4, after the output voltage Vout (k) is stabilized, each comparator 161 receives the first reference voltage VH input to the second input terminal and the output voltage Vout (k). Compare with. Considering (Equation 8), this is because comparing the magnitude relationship between the differential voltage V0 (= Vres−Vsig) and the threshold voltage Vk (= (k−1) × (VH−VL) / 2 ^M ). The same. In this way, each comparator 161 can compare the corresponding threshold voltage with the differential voltage V0 and output the comparison result signal b indicating the comparison result.

For example, in the example shown in FIG. 6, the output voltages Vout (1) and Vout (2) are larger than the first reference voltage VH, and the output voltages Vout (3) and Vout (4) are smaller than the first reference voltage VH. Therefore, b (1) is LO (low level), b (2) is LO, b (3) is HI (high level), and b (4) is HI.

Here, when the difference between the differential voltage V0 and the jth threshold voltage is Vd, Vd can be expressed by the following equation. J is an integer.

Next, at time t4, the decoder / selection circuit 156 decodes the 2 ^M- bit comparison result signal b to output the first digital signal 130 of higher M bits. In the case of FIG. 6, the first digital signal 130 is 10 in binary notation. The decoder / selection circuit 156 outputs the selection signal sel using the 2 ^M- bit comparison result signal b, and outputs the output voltage Vout (j) of the j-th calculation unit 153-j to the input terminal of the impedance converter 155. Apply to.

For example, in the example shown in FIG. 6, only the switch 154 corresponding to the second calculation unit 153-2 is turned on, and the other switches 154 are turned off.

Also, at time t4, the timing control unit 112 opens the switch 157. At this time, from (Expression 9), Vout (j) is expressed by the following (Expression 11).

That is, the first AD converter 106 outputs a voltage corresponding to (Vd + VH) as the residual voltage 131 after time t4.

For example, in the example shown in FIG. 6, the residual voltage 131 is Vres−Vsig + V3.

Note that the first AD converter 106 outputs the first reference voltage VH as the residual voltage 131 before time t4. Therefore, the second column AD conversion unit 124 calculates these voltage differences. From (Equation 10) and (Equation 11), this voltage difference is Vd. The second column AD converter 124 can generate a second digital signal of lower N bits by AD converting this Vd.

Hereinafter, details of the second column AD conversion unit 124 will be described.

FIG. 7 is a circuit diagram showing a configuration example of the comparator 110.

As shown in FIG. 7, the comparator 110 includes a differential amplifier circuit 170,

capacitors

171 and 172, and a switch 173.

The capacitor 171 is connected between the first input terminal of the comparator 110 and one input terminal of the differential amplifier circuit 170 (the gate of one differential transistor 174). The capacitor 172 is connected between the second input terminal of the comparator 110 and the other input terminal of the differential amplifier circuit 170 (the gate of the other differential transistor 174).

The switch 173 shorts or opens the two input terminals of the differential amplifier circuit 170. The opening and closing of the switch 173 is controlled by the timing control unit 112.

Next, the operation of the comparator 110 will be described.

First, the timing control unit 112 closes the switch 173 and outputs the second input during the period (before time t4 in FIG. 6) in which the residual voltage 131 is input to the first input terminal and is the first reference voltage VH. The ramp voltage RAMP generated by the reference signal generator 113 input to the terminal is made constant.

Next, the timing control unit 112 opens the switch 173 and starts increasing the RAMP voltage at the timing (time t4) when the residual voltage 131 becomes Vd + VH. Further, the timing control unit 112 starts increasing the counter value CNT simultaneously with these.

Thereafter, the logic of the comparison result signal 133 changes at the timing when the potentials of the two input terminals of the differential amplifier circuit 170 coincide.

The counter latch unit 111 stores the counter value CNT at the timing when the logic of the comparison result signal 133 changes, and the lower N-bit AD conversion ends.

Based on the above operation, the AD conversion operation by the solid-state imaging device 100 will be described. FIG. 8 is a timing chart of the AD conversion operation by the solid-state imaging device 100. FIG. 8 shows the time in the horizontal direction, and shows how time elapses from left to right. The vertical direction is a voltage value.

First, in the horizontal blanking period, the pixel 102 performs an imaging operation, and outputs a reset voltage Vres to the vertical signal line 104 in a period from time t11 to time t13. Accordingly, the reset voltage holding unit 105 holds the reset voltage Vres at time t12.

Thereafter, in the period from time t14 to time t17, the pixel 102 outputs the signal voltage Vsig to the vertical signal line 104. As a result, the signal voltage Vsig and the reset voltage Vres are input to the first AD converter 106.

Next, each calculation unit 153 performs the operation shown in FIG. Therefore, at time t15 (corresponding to time t3 in FIG. 6), each output voltage Vout has a value represented by the above (Equation 9).

Further, before time t16 (corresponding to time t4 in FIG. 6), the residual voltage 131 becomes the first reference voltage VH, and at time t16, the residual voltage 131 becomes (Vd + VH) (Vres−Vsig + Vx in FIG. 8). Are described in order.

Next, at time t18, the reference signal generator 113 starts increasing the voltage value of the ramp voltage RAMP. At time t18, the timing control unit 112 starts counting up the counter value CNT.

Next, at time t19, when the voltage values of the residual voltage 131 and the ramp voltage RAMP match, the comparator 110 inverts the logic of the comparison result signal 133. As a result, the counter latch unit 111 stores the counter value CNT at time t19.

Thus, the M + N bit AD conversion operation is completed.

Although not shown in FIG. 8, after that, the column scanning circuit 109 sequentially transfers the M + N-bit third digital signal of each column to the outside of the solid-state imaging device 100. Thus, the operation for one line is completed.

Further, the AD conversion operation shown here is performed during the horizontal scanning period. However, when it is desired to increase the imaging speed (so-called frame rate) of the solid-state imaging device 100, the solid-state imaging device 100 may perform the AD conversion operation in the horizontal blanking period and the horizontal scanning period of other rows. In this case, a circuit or means for performing an AD conversion operation in parallel with the operation of another row may be prepared.

As described above, the solid-state imaging device 100 according to Embodiment 1 of the present invention can further speed up the AD conversion processing as compared with the conventional solid-state imaging device 600 shown in FIG.

Specifically, in the conventional AD converter 601 shown in FIG. 16, an ADC circuit (2-bit ADC 603) and a circuit that outputs an analog residual exist independently. Further, after the AD conversion operation of the ADC circuit is completed, DA conversion is performed by operating a switch connected to the capacitor. Next, the difference between the signal voltage and the reset voltage is calculated, and an analog residual (residual voltage) is generated by subtracting the analog voltage obtained by DA conversion from the difference.

As described above, the conventional AD converter 601 DA-converts the AD converted upper bit digital signal, and calculates the analog residual by subtracting the DA-converted analog voltage from the DA-converted signal voltage.

Further, Patent Document 2 discloses only a case where N = 2 as a specific example of the ADC circuit. In this case, the AD conversion time may be completed in a short time. Since the conversion time increases, there is a concern about speed reduction.

Also, the conventional AD converter 601 shown in FIG. 16 has two blocks, an ADC circuit and an analog residual output circuit, and there is a concern that the circuit scale will increase. However, it is assumed that this circuit is arranged corresponding to each column of the imaging unit, and it is expected that it is difficult to arrange in terms of area.

Furthermore, in the conventional AD converter 601, since the ADC circuit and the amplifier that outputs the analog circuit residual operate simultaneously, there is a concern that the operating power increases.

On the other hand, in the solid-state imaging device 100 according to Embodiment 1 of the present invention, 2 ^M residual voltage generators 160 (160A and 160B) generate 2 ^M residual voltages (output voltage Vout), AD conversion processing is performed using the generated residual voltage. As described above, since the solid-state imaging device 100 according to Embodiment 1 of the present invention does not perform the DA conversion processing performed in the conventional AD converter 601, it is faster than the conventional AD converter 601. AD conversion processing can be performed.

Further, in the solid-state imaging device 100 according to Embodiment 1 of the present invention, the first AD converter 121 calculates the differential voltage V0 at high speed using the charging / discharging of the capacitor, and 2 ^M threshold voltages and the difference By simultaneously comparing the voltages with 2 ^M comparators 161, high-speed AD conversion processing can be realized.

Further, the second AD converter 122 performs an AD conversion process with excellent linearity using the ramp voltage RAMP.

As described above, the solid-state imaging device 100 according to Embodiment 1 of the present invention does not require high accuracy for the upper M-bit AD conversion. For this conversion, a method with excellent linearity but slow speed is used. As a result, the solid-state imaging device 100 according to the present invention can achieve both the trade-off relationship between improving the conversion speed and ensuring the linearity.

(Embodiment 2)
Hereinafter, a solid-state imaging device 100A according to Embodiment 2 of the present invention will be described with reference to the drawings.

FIG. 9 is a diagram showing a configuration of a solid-state imaging device 100A according to Embodiment 2 of the present invention. In addition, the same code | symbol is attached | subjected to the element similar to FIG.

The solid-state imaging device 100A according to Embodiment 2 of the present invention differs from the solid-state imaging device 100 according to Embodiment 1 described above in the configuration of the first AD converter 121A. Hereinafter, differences from the solid-state imaging device 100 according to Embodiment 1 will be mainly described, and overlapping descriptions will be omitted.

The first AD conversion unit 121A performs a first AD conversion process. The first AD converter 121A includes a reference voltage generator 107 and a plurality of first column AD converters 123A, one for each Q column.

Each first column AD conversion unit 123A performs a first AD conversion process on the reset voltage Vres and the signal voltage Vsig generated by the pixels 102 arranged in the corresponding Q column.

Each first column AD conversion unit 123A includes Q reset voltage holding units 105, Q signal voltage holding units 301, a first selection circuit 302, a second selection circuit 303, and a first AD converter 106. , Q first storage units 108, and Q residual voltage holding units 304.

Each reset voltage holding unit 105 is provided for each column, is connected to the vertical signal line 104 of the corresponding column, and holds the reset voltage Vres output by the pixel 102 of the corresponding column.

Each signal voltage holding unit 301 is provided for each column, is connected to the vertical signal line 104 of the corresponding column, and holds the signal voltage Vsig output by the pixel 102 of the corresponding column.

The first selection circuit 302 selects one of the Q columns, the reset voltage Vres held in the reset voltage holding unit 105 provided in the selected column, and the signal voltage holding unit 301 provided in the selected column. And the signal voltage Vsig held at the first AD converter 106.

The first AD converter 106 receives the reset voltage Vres and the signal voltage Vsig output from the first selection circuit 302, and the first reference voltage VH and the second reference voltage VL generated by the reference voltage generation unit 107. The

The first AD converter 106 performs a first AD conversion process on the reset voltage Vres and the signal voltage Vsig output from the first selection circuit 302.

Each first storage unit 108 is provided for each column, and holds the first digital signal 130 of the corresponding column generated by the first AD converter 106.

Each residual voltage holding unit 304 is provided for each column, and holds the residual voltage 131 of the corresponding column generated by the first AD converter 106.

The second selection circuit 303 selects one of the Q columns, and outputs the first digital signal 130 generated by the first AD converter 106 to the first storage unit 108 provided in the selected column. The residual voltage 131 generated by the first AD converter 106 is output to the residual voltage holding unit 304 provided in the column.

Further, the second column AD conversion unit 124 AD converts the residual voltage 131 held in the residual voltage holding unit 304 provided in the corresponding column into an N-bit second digital signal. In other words, each second column AD converter 124 performs a second AD conversion process on the residual voltage 131 output by the second selection circuit 303 provided in the corresponding Q column.

Further, the timing control unit 112 causes the plurality of first column AD conversion units 123A to select each of the Q columns by causing the plurality of first selection circuits 302 and the plurality of second selection circuits 303 to sequentially select the columns of the Q column. The residual voltage 131 and the first digital signal 130 corresponding to the columns are sequentially generated.

Thus, in the solid-state imaging device 100A shown in FIG. 9, the first AD converters 106 are arranged every Q columns. Therefore, the number of first AD converters 106 that the solid-state imaging device 100A requires is 1 / Q compared to the solid-state imaging device 100 according to Embodiment 1 of the present invention. Thereby, the solid-state imaging device 100A can reduce the circuit area. Further, in the solid-state imaging device 100A, the horizontal width of the area where one first AD converter 106 can be arranged is an area corresponding to Q columns, so that circuit arrangement can be facilitated.

Hereinafter, the operation of the solid-state imaging device 100A according to the second embodiment of the present invention will be described focusing on portions that do not overlap with the solid-state imaging device 100 according to the first embodiment of the present invention.

FIG. 10 is a timing chart of the AD conversion operation by the solid-state imaging device 100A according to Embodiment 2 of the present invention. FIG. 10 shows time in the horizontal direction, and shows how time passes from left to right. The vertical direction is a voltage value.

Also, here, it is assumed that the first selection circuit 302 and the second selection circuit 303 sequentially select from the first column to the Qth column. Note that the order in which the columns are selected may be other orders.

First, each pixel 102 arranged in a row selected by the row scanning circuit 103 performs an imaging operation in the horizontal blanking period, outputs the obtained reset voltage Vres to the reset voltage holding unit 105, and obtains the obtained signal. The voltage Vsig is output to the signal voltage holding unit 301 (not described so far in FIG. 10).

Next, in the period from time t21 to time t22, the first selection circuit 302 selects the leftmost first column among the Q columns, and holds the reset voltage holding unit 105 and the signal voltage holding arranged in the first column. The output terminal of the unit 301 is connected to the first AD converter 106. The second selection circuit 303 connects the output terminal of the first AD converter 106 to which the residual voltage 131 is output to the input terminal of the comparator 110 corresponding to the first column.

The first AD converter 106 performs AD conversion by the same operation as that of the first embodiment of the present invention. That is, the first AD converter 106 outputs the residual voltage 131 to the first input terminal of the comparator 110 in the first column via the second selection circuit 303. Specifically, as described in the first embodiment, the first reference voltage VH and then Vd + VH are output as the residual voltage 131. When the circuit shown in FIG. 7 is used as the comparator 110, the timing control unit 112 closes the switch 173 during the period when VH is input, and opens the switch 173 at the timing when Vd + VH is input. The residual voltage 131 (Vd + VH) is held by the residual voltage holding unit 304.

Also, the first AD converter 106 outputs the first M-bit first digital signal 130 to the first storage unit 108 in the first column via the second selection circuit 303.

Thereafter, the first selection circuit 302 and the second selection circuit 303 select the second column on the right of the first column in the period from time t22 to time t23, and the first column AD conversion unit 123A operates in the same manner. I do. The first selection circuit 302 and the second selection circuit 303 select the third column in the period from time t23 to time t24, and the first column AD conversion unit 123A performs the same operation. Thereafter, in the period from time t24 to time t25, the same operation is repeated from the fourth column to the Q-1th column. Finally, in the period from time t25 to time t26, the first selection circuit 302 and the second selection circuit 303 select the Qth column, and the first column AD conversion unit 123A performs the same operation. This operation is simultaneously performed in all the first row AD conversion units 123A mounted on the solid-state imaging device 100A.

With the above operation, the AD conversion processing of the upper M bits of all the columns and the generation processing of the residual voltage 131 are completed.

Thereafter, after time t27, the second column AD conversion units 124 of all the columns of the solid-state imaging device 100A simultaneously perform AD conversion processing of lower N bits.

This completes AD conversion processing for all bits.

As described above, the timing control unit 112 causes the plurality of first column AD conversion units 123A to generate the residual voltages 131 corresponding to all the columns included in the Q column during the period from time t21 to time t26. After time t27, the second AD conversion units 124 are caused to simultaneously perform the second AD conversion processing.

Although not shown in FIG. 10, after that, the column scanning circuit 109 sequentially transfers the M + N-bit third digital signal of each column to the outside of the solid-state imaging device 100A. Thus, the operation for one line is completed.

Further, the AD conversion operation shown here is performed during the horizontal scanning period. However, when it is desired to increase the imaging speed (so-called frame rate) of the solid-state imaging device 100A, the solid-state imaging device 100A may perform the AD conversion operation in the horizontal blanking period and the horizontal scanning period of other rows. In this case, a circuit or means for performing an AD conversion operation in parallel with the operation of another row may be prepared.

Here, the time required for all AD conversion processing is a value obtained by adding the time required for AD conversion processing for the lower N bits to Q times the time required for AD conversion processing for the upper M bits. This is inferior to the solid-state imaging device 100 according to Embodiment 1 of the present invention, but is faster than the solid-state imaging device 700 described in Patent Document 3 that shares several AD converters. Because the first AD converter 106 according to the present invention is high-speed as described in the first embodiment, the entire conversion time can be reduced by operating the AD conversion processing of lower bits, which is relatively low-speed, for all columns simultaneously. This is because it can be shortened.

(Embodiment 3)
Hereinafter, the operation of the solid-state imaging device according to Embodiment 3 of the present invention will be described with reference to the drawings.

In Embodiment 3 of the present invention, a modification of the first AD converter 106 according to Embodiment 1 and Embodiment 2 described above will be described. Other elements are the same as those in the first embodiment or the second embodiment, and a description thereof will be omitted.

FIG. 11 is a diagram showing a configuration of the first AD converter 106A of the solid-state imaging device according to Embodiment 3 of the present invention. Note that the same elements as those in FIG. 5 are denoted by the same reference numerals, and redundant description is omitted.

Hereinafter, a specific configuration and operation of the first AD converter 106A will be described. In the following, description will be made including the capacitance value of the capacitor, but the capacitance value of each capacitor may be different from the following description. However, depending on the capacitance value, there may be a case where a correct AD conversion result cannot be obtained, but if a means for calibrating it is prepared separately, it is possible to correctly perform AD conversion as a result.

In the first AD converter 106A shown in FIG. 11, the configuration of the calculation unit 153A is different from the calculation unit 153 described above.

Specifically, the first calculation unit 153A-1 includes a residual voltage generation unit 160C and a waveform shaping circuit 313. The second calculation unit 153A-2 to the second ^M calculation unit 153A- ^2M include a residual voltage generation unit 160D and a waveform shaping circuit 313.

The residual voltage generator 160C includes an operational amplifier 310, a capacitor 311 and a switch 312 in addition to the configuration of the residual voltage generator 160A shown in FIG. Similarly, the residual voltage generator 160D includes an operational amplifier 310, a capacitor 311 and a switch 312 in addition to the configuration of the residual voltage generator 160B shown in FIG.

The operational amplifier 310, the capacitor 311, and the switch 312 include an output terminal (corresponding to a first terminal and a second terminal of the present invention) from which an output voltage Vout is output, and a node 165 (a first node and a second node of the present invention). Equivalent).

The inverting input terminal of the operational amplifier 310 is connected to the node 165. A reset voltage Vres is applied to the non-inverting input terminal of the operational amplifier 310.

The capacitor 311 is connected between the inverting input terminal and the output terminal of the operational amplifier 310. The capacitance of the capacitor 311 is 2 ^MC .

The switch 312 is connected between the inverting input terminal and the output terminal of the operational amplifier 310 in parallel with the capacitor 311.

The operational amplifier 310 outputs the output voltage Vout to the output terminal. This output voltage Vout is input to the waveform shaping circuit 313 and the switch 154.

The waveform shaping circuit 313 digitally determines 0/1 based on the magnitude relationship between the input output voltage Vout and the first reference voltage VH. That is, the waveform shaping circuit 313 corresponds to the comparator 161 shown in FIG. 5, and generates the comparison result signal b by comparing the residual voltage (output voltage Vout) with the first reference voltage VH.

Hereinafter, the operation of the first AD converter 106A shown in FIG. 11 will be described. In the following, the case of M = 2, VL = 0V, VH = 1V, Vres = 1.5V, and Vsig = 1.2V will be described as an example, but it goes without saying that the same operation is performed in other cases. FIG. 12 is a timing chart showing the operation of the first AD converter 106A. FIG. 12 shows the time in the horizontal direction, and shows how time elapses from left to right. The vertical direction in FIG. 12 is a voltage value.

FIG. 12 shows values of the output voltages Vout (1) to Vout (4) of the first calculation unit to the fourth calculation unit and the residual voltage 131 at each time. Further, the description here is a case where no offset voltage is applied to the reset voltage Vres. When applied, the threshold value used in the waveform shaping circuit 313 may be set to a value obtained by adding an offset voltage to the first reference voltage VH. In the description here, the gain of all the operational amplifiers 310 is assumed to be infinite. There is no infinite operational amplifier, but usually the operational amplifier has a large gain so that it can be considered infinite. Alternatively, an operational amplifier having a sufficiently large gain can be manufactured.

First, in the period from time t31 to time t32, the timing control unit 112 turns on the first switch 164 and the switch 312 to cause the second switch 162 and the third switch 166 to select VH and set the fourth switch 168 to VL. Let them choose. At this time, the voltages at all terminals of all the operational amplifiers 310 become Vres.

In the period from time t31 to time t34, the timing control unit 112 turns on the switch 154 and turns off the switch 157. As a result, the first reference voltage VH is supplied to the input terminal of the impedance converter 155. Therefore, the residual voltage 131 is VH.

Next, in the period from time t32 to time t33, the timing control unit 112 turns off the first switch 164 and the switch 312 and causes the second switch 162 to select Vsig and causes the third switch 166 and the fourth switch 168 to perform VL. To select. At this time, the voltage at the left end of the capacitor 163 changes by Vsig−VH due to the switching of the second switch 162.

This change is amplified by the operational amplifier 310. However, the operational amplifier 310 receives negative feedback due to the capacitor 311 connected between the output terminal of the operational amplifier 310 and the inverting input terminal of the operational amplifier 310, and the output voltage Vout (1) becomes a finite value. At this time, since the gain of the operational amplifier 310 is infinite, in order for the output voltage Vout (1) of the operational amplifier 310 to have a finite value, the voltage at the inverting input terminal of the operational amplifier 310 is the voltage at the non-inverting input terminal (that is, Vres). Must be equal. For this reason, the voltage at the right end of the capacitor 163 (the voltage at the node 165) does not change. As a result, the voltage difference between both ends of the capacitor 163 increases by (Vsig−VH), so that the charge Q _A accumulated in the capacitor 163 increases as shown by the following (formula 12), with the left end charge being positive. .

Further, since the voltage source or the current source is not connected to the inverting input terminal of the operational amplifier 310, the increased charge moves from the capacitor 311. Here, since the capacitances of the capacitor 311 and the capacitor 163 are equal, the voltage difference between both ends of the capacitor 311 changes by (VH−Vsig) by this charge movement, and this change is the change of the output voltage Vout (1). It becomes. Therefore, the output voltage Vout (1) of the operational amplifier 310 of the first calculation unit 153A-1 is expressed by the following (formula 13).

Similarly, regarding the k-th calculation unit 153A-k (k is an integer of 2 ≦ k ≦ 2 ^M ), the voltage difference between both ends of the capacitor 167 changes by VL−VH. (Expression 14)

Considering the change in the voltage difference between both ends of the capacitor 311 due to the movement of this charge from the capacitor 311, the output voltage Vout (k) of the kth calculation unit 153A-k is obtained as shown in the following (formula 15).

Next, at time t33, the timing control unit 112 causes the third switch 166 and the fourth switch 168 to select Vsig. In other words, the timing control unit 112 turns off the first switch 164 and the switch 312 after time t33, causes the second switch 162 to select Vsig, and causes the third switch 166 and fourth switch 168 to select Vsig.

At this time, since the state of the first calculation unit 153A-1 does not change, the output voltage Vout (1) is expressed by the above (formula 13).

On the other hand, in the k-th calculation unit 153A-k, the charge transfer due to the change in the voltage difference between both ends of the capacitor 167 and the capacitor 169 by (Vsig−VL) similarly occurs. Here, since the total capacity of the capacitors 167 and 169 is equal to the capacity of the capacitor 311, this voltage change (absolute value) occurs in the capacitor 311 as it is, so that the output voltage Vout (k) is expressed as ( It is expressed by equation 16).

That is, Vout (k) has the same value as the above (formula 8). (Expression 13) is the same as (Expression 2). Therefore, after time t33, the upper M-bit AD conversion process can be performed by operating the first AD converter 106A in the same manner as after time t3 shown in FIG. The subsequent processing is the same as in the first embodiment.

As described above, even when the first AD converter 106A according to Embodiment 3 of the present invention is used, the same effect as that obtained when the first AD converter 106 is used can be obtained.

(Embodiment 4)
Hereinafter, the operation of the solid-state imaging device according to Embodiment 4 of the present invention will be described with reference to the drawings.

In Embodiment 4 of the present invention, a modification of the driving method of the solid-state imaging device 100A according to Embodiment 2 described above will be described.

FIG. 13 is a timing chart of the AD conversion operation by the solid-state imaging device 100A according to Embodiment 4 of the present invention. Note that the configuration of the solid-state imaging device 100A is the same as that of the second embodiment. Hereinafter, an example in which the solid-state imaging device 100A includes the first AD converter 106 described in the first embodiment will be described. However, the solid-state imaging device 100A includes the first AD converter 106A described in the third embodiment. You may prepare.

First, each pixel 102 arranged in a row selected by the row scanning circuit 103 performs an imaging operation in the horizontal blanking period, outputs the obtained reset voltage Vres to the reset voltage holding unit 105, and obtains the obtained signal. The voltage Vsig is output to the signal voltage holding unit 301.

Next, in the period from time t41 to time t42, the first selection circuit 302 and the second selection circuit 303 select the first column. As a result, the first AD converter 106 performs upper M-bit AD conversion processing on the first column, and outputs the residual voltage 131 to the comparator.

Next, in the period from time t42 to time t43, the first selection circuit 302 and the second selection circuit 303 select the second column. As a result, the first AD converter 106 performs upper M-bit AD conversion processing on the second column. At the same time as the AD conversion process of the upper M bits in the second column, the timing control unit 112 starts counting up the counter value CNT at time t42. Further, at time t42, the ramp voltage RAMP input to the reference signal generator 113 and the comparator 110 in the first column starts to increase. The counter latch unit 111 stores the counter value CNT when the voltages at both input terminals of the comparator 110 match.

Thus, in the solid-state imaging device 100A according to Embodiment 4 of the present invention, the lower N-bit AD conversion processing in the first column and the upper M-bit AD conversion processing in the second column are performed simultaneously.

In other words, the timing control unit 112 causes the plurality of first column AD conversion units 123A to generate the residual voltage 131 corresponding to the first column included in the Q column, and at the same time, includes the first column included in the Q column. A plurality of second column AD conversion units 124 provided in different second columns are caused to perform the second AD conversion process on the residual voltage 131 of the corresponding column already generated by the first column AD conversion unit 123A. .

Similarly, in the period from time t43 to time t44, the AD conversion processing of the lower N bits in the second column is performed simultaneously with the AD conversion processing of the upper M bits in the third column. Thus, by time t45, the processing up to the lower N-bit AD conversion processing of the P-th column is performed (P is an integer of 1 or more and less than Q).

Next, after time t45, the solid-state imaging device 100A continues to perform AD conversion for the (P + 1) th column. At the same time, the column scanning circuit 109 starts from the first column after the AD conversion processing for all bits is completed. Transfers digital values up to P column to the outside.

Thereafter, in the period from time t46 to time t47, AD conversion processing of the upper M bits of the Qth column is performed, and in the period of time t47 to time t48, AD conversion processing of the lower N bits of the Qth column is performed.

After the time t48 when the AD conversion processing for all the columns is completed, the column scanning circuit 109 transfers the digital values of the P + 1th column to the Qth column to the outside.

Thus, the AD conversion process for one line is completed.

As described above, the timing control unit 112 corresponds to the first column group (first column to Pth column) included in the Q column in the plurality of first column AD conversion units 123A in the period from time t41 to time t45. Residual voltage 131 and first digital signal 130 are sequentially generated, and a plurality of second column AD converters 124 provided in the first column group are supplied to residual voltage 131 corresponding to the first column group. Then, the second digital signal is sequentially generated by performing the second AD conversion process.

Further, the timing control unit 112, during the period from time t45 to time t48, includes a second column group (P + 1st column to Qth column) included in the Q column in the plurality of first column AD conversion units 123A. The residual voltage 131 and the first digital signal 130 corresponding to the second column group are sequentially generated, and a plurality of second column AD conversion units 124 provided in the second column group are also provided with the remaining voltage corresponding to the second column group. The second AD conversion process is performed on the difference voltage 131, and at the same time, the column scanning circuit 109 sequentially transfers the third digital signal corresponding to the first column group to the outside.

In addition, according to the solid-state imaging device 100A according to Embodiment 4 of the present invention, the operation of each unit operates in parallel, thereby reducing the number of operations waiting for other processing, thereby enabling a high-speed AD conversion operation as a whole. Become.

Note that the above description is merely an example, and other timing charts are naturally obtained when other columns perform AD conversion processing of upper M bits and simultaneously perform lower N bits of AD conversion processing in other columns. Conceivable. Furthermore, another timing chart can be considered if a digital value is transferred to the outside simultaneously with performing some AD conversion operation in another column.

For example, the solid-state imaging device 100A may divide a digital signal that has undergone all-bit AD conversion processing into three or more divisions and output it to the outside.

Further, the solid-state imaging device 100A may simultaneously perform AD conversion processing of lower M bits of another plurality of columns at the same time as performing AD conversion processing of upper M bits of a plurality of columns sequentially. For example, after the AD conversion processing of the upper M bits from the first column to the Pth column is sequentially performed, the AD conversion processing of the lower N bits from the first column to the Pth column is simultaneously performed, and then the first column to The third digital signal up to the P-th column may be transferred to the outside. In this case, at least one of the lower N-bit AD conversion processing and transfer processing and the upper M-bit AD conversion processing from the (P + 1) -th column to the Q-th column may be performed simultaneously.

Further, each processing unit included in the solid-

state imaging devices

100 and 100A according to the first to fourth embodiments is typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.

Further, the integration of circuits is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI or a reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.

Further, some or all of the functions of the solid-

state imaging devices

100 and 100A according to Embodiments 1 to 4 of the present invention may be realized by a processor such as a CPU executing a program.

Furthermore, the present invention may be the above program or a recording medium on which the above program is recorded. Needless to say, the program can be distributed via a transmission medium such as the Internet.

Further, the present invention may be realized as an AD converter that is a part or all of the AD conversion circuit 120 included in the solid-

state imaging device

100 or 100A.

Further, at least a part of the functions of the solid-

state imaging devices

100 and 100A and the modifications thereof according to the first to fourth embodiments may be combined.

Also, the numbers used above are all exemplified for specifically describing the present invention, and the present invention is not limited to the illustrated numbers. Furthermore, the logic levels represented by high / low or the switching states represented by on / off are illustrative for the purpose of illustrating the present invention, and different combinations of the illustrated logic levels or switching states. Therefore, it is possible to obtain an equivalent result. In addition, n-type and p-type transistors and the like are illustrated to specifically describe the present invention, and it is possible to obtain equivalent results by inverting them. In addition, the connection relationship between the components is exemplified for specifically explaining the present invention, and the connection relationship for realizing the function of the present invention is not limited to this.

In the above description, an example using a MOS transistor is shown, but another transistor such as a bipolar transistor may be used.

Furthermore, various modifications in which the present embodiment is modified within the scope conceived by those skilled in the art are also included in the present invention without departing from the gist of the present invention.

The present invention can be applied to a solid-state imaging device. Further, the present invention can be used for a digital still camera, a digital video camera, a surveillance camera, and the like provided with a solid-state imaging device.

100, 100A, 500, 600, 700 Solid-state imaging device 101 Imaging unit 102, 501 Pixel 103 Row scanning circuit 104 Vertical signal line 105 Reset

voltage holding unit

106, 106A First AD converter 107 Reference voltage generation unit 108 First storage unit 109

Column scanning circuit

110, 503 Comparator 111 Counter latch unit 112 Timing control unit 113 Reference signal generation unit 120

AD conversion circuit

121, 121A First AD conversion unit 122 Second

AD conversion unit

123, 123A First column AD conversion unit 124 Second column AD conversion unit 130 First digital signal 131 Residual voltage 133 Comparison result signal 151 Calculation unit 152 Selection unit 153,

153A Calculation unit

154, 157, 173, 312 Switch 155 Impedance converter 156 Decoder /

selection circuit

160, 60A, 160B, 160C, 160D Residual voltage generator 161 Comparator 162

Second switch

163, 167, 169, 171, 172, 311 Capacitor 164 First switch 165 Node 166 Third switch 168 Fourth switch 170 Differential amplifier circuit 174 Differential transistor 201 Reset transistor 202 Photodiode (PD)
203 Transfer transistor 204 Floating diffusion (FD)
205 Amplifier Transistor 206 Pixel Selection Transistor 301 Signal Voltage Holding Unit 302 First Selection Circuit 303 Second Selection Circuit 304 Residual Voltage Holding Unit 310 Operational Amplifier 313

Waveform Shaping Circuit

502, 601, 602, 701 AD Converter 504 DA Converter 603 2 Bit ADC
b Comparison result signal CNT Counter value RAMP Ramp voltage RSCELL Reset signal line sel Select signal SELECT Select signal line TRANS Transfer signal line V0, Va Differential voltage VDD Power supply line VH First reference voltage VL Second reference voltage Vout Output voltage Vres Reset voltage Vsig Signal voltage

Claims

A plurality of pixels arranged in a matrix and outputting a reset voltage and a signal voltage corresponding to the amount of incident light;
AD conversion of the signal voltage into a third digital signal of M + N bits including a first digital signal of M (M is an integer of 1 or more) bits and a second digital signal of N (N is an integer of 1 or more) bits. And an AD conversion circuit that
The AD conversion circuit includes:
A differential voltage indicating a difference between the reset voltage and the signal voltage is calculated, the calculated differential voltage is AD-converted into the first digital signal, and corresponding to the digital value of the differential voltage and the first digital signal. A first AD converter that performs a first AD conversion process for generating a first residual voltage indicating a difference from the analog voltage;
A second AD converter that performs a second AD conversion process for AD converting the first residual voltage into the second digital signal;
The first AD converter is
To calculate the differential voltage, the difference voltage and the 2 M-number of shows the difference between the respective threshold voltages, 2 M number of second residual corresponding to each of the 2 M pieces of digital values represented by M bits A residual voltage generator for generating a differential voltage;
A first comparison unit that generates a 2 M- bit first comparison result signal by comparing each of the 2 M second residual voltages with a first reference voltage;
A decoder for converting the 2 M- bit first comparison result signal into the M-bit first digital signal;
Of the 2 M second residual voltages, a second residual voltage corresponding to the digital value of the first digital signal converted by the decoder is selected, and the selected second residual voltage is selected as the first residual voltage. A solid-state imaging device comprising: a selection unit that outputs as a residual voltage.
The second AD converter is
A plurality of second column AD conversion units, one for each column,
The first AD converter is
A plurality of first column AD conversion units that are provided for each Q column and perform the first AD conversion processing on the reset voltage and the signal voltage output by the plurality of pixels arranged in the corresponding Q column. Prepared,
Each of the first column AD conversion units is
A first selection circuit that selects one of the Q columns and outputs the reset voltage and the differential voltage output by a pixel arranged in the selected column;
A first AD converter that performs the first AD conversion processing on the reset voltage and the signal voltage output by the first selection circuit;
A second selection circuit that selects one of the Q columns and outputs the first residual voltage generated by the first AD converter to the second column AD converter provided in the selected column; With
2. The solid-state imaging according to claim 1, wherein each of the second column AD conversion units performs the second AD conversion processing on the first residual voltage output by the second selection circuit provided in the corresponding Q column. apparatus.
The solid-state imaging device further includes:
By causing the first selection circuit and the second selection circuit to sequentially select each column of the Q columns, the first column AD conversion unit causes the first residual voltage corresponding to each column of the Q columns and the A first controller that sequentially generates a first digital signal;
The first control unit causes the first column AD conversion unit to generate the first residual voltage corresponding to the first column included in the Q column, and at the same time includes the first column included in the Q column. The second AD conversion process is performed on the first residual voltage of the corresponding column already generated by the first column AD conversion unit in the second column AD conversion unit provided in the second column different from The solid-state imaging device according to claim 2.
The solid-state imaging device further includes:
A column scanning circuit for sequentially transferring the third digital signal AD-converted by the AD conversion circuit to the outside;
The first control unit further includes:
The first column AD conversion unit sequentially generates the first residual voltage and the first digital signal corresponding to the first column group included in the Q column, and the first column AD provided in the first column group By causing the two-column AD conversion unit to perform the second AD conversion processing on the first residual voltage corresponding to the first column group, the second digital signal is sequentially generated,
The first column AD conversion unit sequentially generates the first residual voltage and the first digital signal corresponding to a second column group included in the Q column and different from the first column group, and the second column The second column AD converter provided in the column group performs the second AD conversion process on the first residual voltage corresponding to the second column group, and at the same time, the column scanning circuit The solid-state imaging device according to claim 3, wherein the third digital signals corresponding to the first column group are sequentially transferred to the outside.
The solid-state imaging device further includes:
By causing the first selection circuit and the second selection circuit to sequentially select each column of the Q columns, the first column AD conversion unit causes the first residual voltage corresponding to each column of the Q columns and the A first controller that sequentially generates a first digital signal;
The first control unit causes the first column AD conversion unit to generate the first residual voltage corresponding to all the columns included in the Q column, and then causes the second column AD conversion unit to 3. The solid-state imaging device according to claim 2, wherein the second AD conversion processing is simultaneously performed on the first residual voltage corresponding to the first column.
The first AD converter is
A plurality of first column AD conversion units that are provided for each column and perform the first AD conversion processing on the reset voltage and the signal voltage output by the pixels arranged in the corresponding column,
The second AD converter is
A plurality of second column AD conversion units that are provided for each column and perform the second AD conversion processing on the first residual voltage generated by the first column AD conversion unit provided in the corresponding column The solid-state imaging device according to claim 1.
The second AD converter is
A reference signal generator that generates a ramp voltage whose voltage value changes with the passage of time from the first time;
A second comparison unit that compares the ramp voltage with the first residual voltage and generates a second comparison result signal indicating a comparison result;
The solid-state imaging device according to claim 1, further comprising: a first holding unit that holds, as the second digital signal, a time from the first time until the logic of the second comparison result signal is inverted.
The residual voltage generator includes a first residue voltage generating unit generated by each one of the 2 M-number of the second residue voltage, (2 M -1) pieces of the second residue voltage generator Including
The first residual voltage generator is
A first terminal from which the second residual voltage generated by the first residual voltage generator is output; a first capacitor having one end connected to the first terminal;
A first switch that switches between a closed state in which the reset voltage is supplied to the first terminal and an open state in which the reset voltage is not supplied;
A second switch that selects one of the signal voltage and the first reference voltage and supplies the selected voltage to the other end of the first capacitor;
Each of the second residual voltage generators is
A second terminal from which the second residual voltage generated by the second residual voltage generator is output;
A second capacitor and a third capacitor having one end connected to the second terminal;
A third switch that selects one of the signal voltage, the first reference voltage, and the second reference voltage, and supplies the selected voltage to the other end of the second capacitor;
A fourth switch that selects one of the signal voltage and the second reference voltage and supplies the selected voltage to the other end of the third capacitor;
The solid-state imaging device according to claim 1, further comprising a fifth switch that switches between a closed state in which the reset voltage is supplied to the second terminal and an open state in which the reset voltage is not supplied.
The solid-state imaging device further includes:
A second control unit for controlling the first switch, the second switch, the third switch, the fourth switch, and the fifth switch;
The second controller is
In the first period, the first switch and the fifth switch are closed, the second switch, the third switch and the fourth switch to select the signal voltage,
In a second period after the first period, the first switch and the fifth switch are opened, the second switch selects the first reference voltage, and the third switch and the fourth switch Selecting the second reference voltage;
In a third period after the second period, the first switch and the fifth switch are opened, the second switch and the third switch select the first reference voltage, and the fourth switch The solid-state imaging device according to claim 8, wherein the second reference voltage is selected.
The residual voltage generator includes a first residue voltage generating unit generated by each one of the 2 M-number of the second residue voltage, (2 M -1) pieces of the second residue voltage generator Including
The first residual voltage generator is
A first terminal from which the second residual voltage generated by the first residual voltage generator is output;
A first node;
A first capacitor having one end connected to the first node;
A first switch that switches between a closed state in which the reset voltage is supplied to the first node and an open state in which the reset voltage is not supplied;
A second switch for selecting one of the signal voltage and the first reference voltage and supplying the selected voltage to the other end of the first capacitor;
A first operational amplifier having an inverting input terminal connected to the first node, a non-inverting input terminal to which the reset voltage is applied, and an output terminal connected to the first terminal;
A fourth capacitor and a sixth switch connected in parallel with each other between the non-inverting input terminal and the output terminal of the first operational amplifier;
Each of the second residual voltage generators is
A second terminal from which the second residual voltage generated by the second residual voltage generator is output;
A second node;
A second capacitor and a third capacitor having one end connected to the second node;
A third switch that selects one of the signal voltage, the first reference voltage, and the second reference voltage, and supplies the selected voltage to the other end of the second capacitor;
A fourth switch for selecting one of the signal voltage and the second reference voltage and supplying the selected voltage to the other end of the third capacitor;
A fifth switch for switching between a closed state in which the reset voltage is supplied to the second node and an open state in which the reset voltage is not supplied;
A second operational amplifier in which an inverting input terminal is connected to the second node, the reset voltage is applied to a non-inverting input terminal, and an output terminal is connected to the second terminal;
The solid-state imaging device according to claim 1, further comprising a fifth capacitor and a seventh switch connected in parallel to each other between the non-inverting input terminal and the output terminal of the second operational amplifier.
The solid-state imaging device further includes:
A second control unit for controlling the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, and the seventh switch;
The second controller is
In the first period, the first switch, the fifth switch, the sixth switch, and the seventh switch are closed, the second switch and the third switch select the first reference voltage, and the first switch 4 switches to select the second reference voltage,
In a second period after the first period, the first switch, the fifth switch, the sixth switch, and the seventh switch are opened, the second switch selects the signal voltage, and the second switch 3 switches and the fourth switch to select the second reference voltage,
In a third period after the second period, the first switch, the fifth switch, the sixth switch, and the seventh switch are opened, and the second switch, the third switch, and the fourth switch The solid-state imaging device according to claim 10, wherein the signal voltage is selected.
An AD conversion method in a solid-state imaging device including a plurality of pixels arranged in a matrix and outputting a reset voltage and a signal voltage corresponding to the amount of incident light,
AD conversion of the signal voltage into a third digital signal of M + N bits including a first digital signal of M (M is an integer of 1 or more) bits and a second digital signal of N (N is an integer of 1 or more) bits. Including an AD conversion step to
The AD conversion step includes
A differential voltage indicating a difference between the reset voltage and the signal voltage is calculated, the calculated differential voltage is AD-converted into a first digital signal, and an analog corresponding to the digital value of the differential voltage and the first digital signal is calculated. A first AD conversion step for performing a first AD conversion process for generating a first residual voltage indicating a difference from the voltage;
A second AD conversion step of performing a second AD conversion process for AD converting the first residual voltage into the second digital signal,
The first AD conversion step includes:
To calculate the differential voltage, the difference voltage and the 2 M-number of shows the difference between the respective threshold voltages, 2 M number of second residual corresponding to each of the 2 M pieces of digital values represented by M bits A residual voltage generating step for generating a differential voltage;
A first comparison step of generating a 2 M- bit first comparison result signal by comparing each of the 2 M second residual voltages with a first reference voltage;
A decoding step of converting the 2 M- bit first comparison result signal into the M-bit first digital signal;
Of the 2 M second residual voltages, a second residual voltage corresponding to the digital value of the first digital signal converted in the decoding step is selected, and the selected second residual voltage is selected as the first residual voltage. And a selection step of outputting as one residual voltage.
The signal voltage is AD-converted into an M + N-bit third digital signal including a first digital signal of M (M is an integer of 1 or more) bits and a second digital signal of N (N is an integer of 1 or more) bits. An AD converter,
AD conversion of the signal voltage into the first digital signal and a first AD conversion process for generating a first residual voltage indicating a difference between the signal voltage and an analog voltage corresponding to a digital value of the first digital signal A first AD converter to perform;
A second AD converter that performs a second AD conversion process for AD converting the first residual voltage into the second digital signal;
The first AD converter is
To calculate the differential voltage, the difference voltage and the 2 M-number of shows the difference between the respective threshold voltages, 2 M number of second residual corresponding to each of the 2 M pieces of digital values represented by M bits A residual voltage generator for generating a differential voltage;
A first comparison unit that generates a 2 M- bit first comparison result signal by comparing each of the 2 M second residual voltages with a first reference voltage;
A decoder for converting the 2 M- bit first comparison result signal into the M-bit first digital signal;
Of the 2 M second residual voltages, a second residual voltage corresponding to the digital value of the first digital signal converted by the decoder is selected, and the selected second residual voltage is selected as the first residual voltage. An AD converter comprising a selection unit that outputs as a residual voltage.